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10#include "qemu/osdep.h"
11#include "hw/qdev-properties.h"
12#include "migration/vmstate.h"
13#include "trace.h"
14#include "qapi/error.h"
15#include "hcd-xhci-sysbus.h"
16#include "hw/acpi/aml-build.h"
17#include "hw/irq.h"
18
19static void xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level)
20{
21 XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci);
22
23 qemu_set_irq(s->irq[n], level);
24}
25
26void xhci_sysbus_reset(DeviceState *dev)
27{
28 XHCISysbusState *s = XHCI_SYSBUS(dev);
29
30 device_legacy_reset(DEVICE(&s->xhci));
31}
32
33static void xhci_sysbus_realize(DeviceState *dev, Error **errp)
34{
35 XHCISysbusState *s = XHCI_SYSBUS(dev);
36
37 object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
38 if (!qdev_realize(DEVICE(&s->xhci), NULL, errp)) {
39 return;
40 }
41 s->irq = g_new0(qemu_irq, s->xhci.numintrs);
42 qdev_init_gpio_out_named(dev, s->irq, SYSBUS_DEVICE_GPIO_IRQ,
43 s->xhci.numintrs);
44 if (s->xhci.dma_mr) {
45 s->xhci.as = g_malloc0(sizeof(AddressSpace));
46 address_space_init(s->xhci.as, s->xhci.dma_mr, NULL);
47 } else {
48 s->xhci.as = &address_space_memory;
49 }
50
51 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->xhci.mem);
52}
53
54static void xhci_sysbus_instance_init(Object *obj)
55{
56 XHCISysbusState *s = XHCI_SYSBUS(obj);
57
58 object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI);
59 qdev_alias_all_properties(DEVICE(&s->xhci), obj);
60
61 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
62 (Object **)&s->xhci.dma_mr,
63 qdev_prop_allow_set_link_before_realize,
64 OBJ_PROP_LINK_STRONG);
65 s->xhci.intr_update = NULL;
66 s->xhci.intr_raise = xhci_sysbus_intr_raise;
67}
68
69void xhci_sysbus_build_aml(Aml *scope, uint32_t mmio, unsigned int irq)
70{
71 Aml *dev = aml_device("XHCI");
72 Aml *crs = aml_resource_template();
73
74 aml_append(crs, aml_memory32_fixed(mmio, XHCI_LEN_REGS, AML_READ_WRITE));
75 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
76 AML_EXCLUSIVE, &irq, 1));
77
78 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0D10")));
79 aml_append(dev, aml_name_decl("_CRS", crs));
80 aml_append(scope, dev);
81}
82
83static Property xhci_sysbus_props[] = {
84 DEFINE_PROP_UINT32("intrs", XHCISysbusState, xhci.numintrs, XHCI_MAXINTRS),
85 DEFINE_PROP_UINT32("slots", XHCISysbusState, xhci.numslots, XHCI_MAXSLOTS),
86 DEFINE_PROP_END_OF_LIST(),
87};
88
89static const VMStateDescription vmstate_xhci_sysbus = {
90 .name = "xhci-sysbus",
91 .version_id = 1,
92 .fields = (VMStateField[]) {
93 VMSTATE_STRUCT(xhci, XHCISysbusState, 1, vmstate_xhci, XHCIState),
94 VMSTATE_END_OF_LIST()
95 }
96};
97
98static void xhci_sysbus_class_init(ObjectClass *klass, void *data)
99{
100 DeviceClass *dc = DEVICE_CLASS(klass);
101
102 dc->reset = xhci_sysbus_reset;
103 dc->realize = xhci_sysbus_realize;
104 dc->vmsd = &vmstate_xhci_sysbus;
105 device_class_set_props(dc, xhci_sysbus_props);
106}
107
108static const TypeInfo xhci_sysbus_info = {
109 .name = TYPE_XHCI_SYSBUS,
110 .parent = TYPE_SYS_BUS_DEVICE,
111 .instance_size = sizeof(XHCISysbusState),
112 .class_init = xhci_sysbus_class_init,
113 .instance_init = xhci_sysbus_instance_init
114};
115
116static void xhci_sysbus_register_types(void)
117{
118 type_register_static(&xhci_sysbus_info);
119}
120
121type_init(xhci_sysbus_register_types);
122
