1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38#ifndef VIRTIO_GPU_HW_H
39#define VIRTIO_GPU_HW_H
40
41#include "standard-headers/linux/types.h"
42
43
44
45
46
47#define VIRTIO_GPU_F_VIRGL 0
48
49
50
51
52#define VIRTIO_GPU_F_EDID 1
53
54
55
56#define VIRTIO_GPU_F_RESOURCE_UUID 2
57
58
59
60
61#define VIRTIO_GPU_F_RESOURCE_BLOB 3
62
63enum virtio_gpu_ctrl_type {
64 VIRTIO_GPU_UNDEFINED = 0,
65
66
67 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
68 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
69 VIRTIO_GPU_CMD_RESOURCE_UNREF,
70 VIRTIO_GPU_CMD_SET_SCANOUT,
71 VIRTIO_GPU_CMD_RESOURCE_FLUSH,
72 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
73 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
74 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
75 VIRTIO_GPU_CMD_GET_CAPSET_INFO,
76 VIRTIO_GPU_CMD_GET_CAPSET,
77 VIRTIO_GPU_CMD_GET_EDID,
78 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
79 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
80 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
81
82
83 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
84 VIRTIO_GPU_CMD_CTX_DESTROY,
85 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
86 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
87 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
88 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
89 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
90 VIRTIO_GPU_CMD_SUBMIT_3D,
91 VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
92 VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
93
94
95 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
96 VIRTIO_GPU_CMD_MOVE_CURSOR,
97
98
99 VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
100 VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
101 VIRTIO_GPU_RESP_OK_CAPSET_INFO,
102 VIRTIO_GPU_RESP_OK_CAPSET,
103 VIRTIO_GPU_RESP_OK_EDID,
104 VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
105 VIRTIO_GPU_RESP_OK_MAP_INFO,
106
107
108 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
109 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
110 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
111 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
112 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
113 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
114};
115
116enum virtio_gpu_shm_id {
117 VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
118
119
120
121
122 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
123};
124
125#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
126
127struct virtio_gpu_ctrl_hdr {
128 uint32_t type;
129 uint32_t flags;
130 uint64_t fence_id;
131 uint32_t ctx_id;
132 uint32_t padding;
133};
134
135
136
137struct virtio_gpu_cursor_pos {
138 uint32_t scanout_id;
139 uint32_t x;
140 uint32_t y;
141 uint32_t padding;
142};
143
144
145struct virtio_gpu_update_cursor {
146 struct virtio_gpu_ctrl_hdr hdr;
147 struct virtio_gpu_cursor_pos pos;
148 uint32_t resource_id;
149 uint32_t hot_x;
150 uint32_t hot_y;
151 uint32_t padding;
152};
153
154
155
156struct virtio_gpu_rect {
157 uint32_t x;
158 uint32_t y;
159 uint32_t width;
160 uint32_t height;
161};
162
163
164struct virtio_gpu_resource_unref {
165 struct virtio_gpu_ctrl_hdr hdr;
166 uint32_t resource_id;
167 uint32_t padding;
168};
169
170
171struct virtio_gpu_resource_create_2d {
172 struct virtio_gpu_ctrl_hdr hdr;
173 uint32_t resource_id;
174 uint32_t format;
175 uint32_t width;
176 uint32_t height;
177};
178
179
180struct virtio_gpu_set_scanout {
181 struct virtio_gpu_ctrl_hdr hdr;
182 struct virtio_gpu_rect r;
183 uint32_t scanout_id;
184 uint32_t resource_id;
185};
186
187
188struct virtio_gpu_resource_flush {
189 struct virtio_gpu_ctrl_hdr hdr;
190 struct virtio_gpu_rect r;
191 uint32_t resource_id;
192 uint32_t padding;
193};
194
195
196struct virtio_gpu_transfer_to_host_2d {
197 struct virtio_gpu_ctrl_hdr hdr;
198 struct virtio_gpu_rect r;
199 uint64_t offset;
200 uint32_t resource_id;
201 uint32_t padding;
202};
203
204struct virtio_gpu_mem_entry {
205 uint64_t addr;
206 uint32_t length;
207 uint32_t padding;
208};
209
210
211struct virtio_gpu_resource_attach_backing {
212 struct virtio_gpu_ctrl_hdr hdr;
213 uint32_t resource_id;
214 uint32_t nr_entries;
215};
216
217
218struct virtio_gpu_resource_detach_backing {
219 struct virtio_gpu_ctrl_hdr hdr;
220 uint32_t resource_id;
221 uint32_t padding;
222};
223
224
225#define VIRTIO_GPU_MAX_SCANOUTS 16
226struct virtio_gpu_resp_display_info {
227 struct virtio_gpu_ctrl_hdr hdr;
228 struct virtio_gpu_display_one {
229 struct virtio_gpu_rect r;
230 uint32_t enabled;
231 uint32_t flags;
232 } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
233};
234
235
236
237struct virtio_gpu_box {
238 uint32_t x, y, z;
239 uint32_t w, h, d;
240};
241
242
243struct virtio_gpu_transfer_host_3d {
244 struct virtio_gpu_ctrl_hdr hdr;
245 struct virtio_gpu_box box;
246 uint64_t offset;
247 uint32_t resource_id;
248 uint32_t level;
249 uint32_t stride;
250 uint32_t layer_stride;
251};
252
253
254#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
255struct virtio_gpu_resource_create_3d {
256 struct virtio_gpu_ctrl_hdr hdr;
257 uint32_t resource_id;
258 uint32_t target;
259 uint32_t format;
260 uint32_t bind;
261 uint32_t width;
262 uint32_t height;
263 uint32_t depth;
264 uint32_t array_size;
265 uint32_t last_level;
266 uint32_t nr_samples;
267 uint32_t flags;
268 uint32_t padding;
269};
270
271
272struct virtio_gpu_ctx_create {
273 struct virtio_gpu_ctrl_hdr hdr;
274 uint32_t nlen;
275 uint32_t padding;
276 char debug_name[64];
277};
278
279
280struct virtio_gpu_ctx_destroy {
281 struct virtio_gpu_ctrl_hdr hdr;
282};
283
284
285struct virtio_gpu_ctx_resource {
286 struct virtio_gpu_ctrl_hdr hdr;
287 uint32_t resource_id;
288 uint32_t padding;
289};
290
291
292struct virtio_gpu_cmd_submit {
293 struct virtio_gpu_ctrl_hdr hdr;
294 uint32_t size;
295 uint32_t padding;
296};
297
298#define VIRTIO_GPU_CAPSET_VIRGL 1
299#define VIRTIO_GPU_CAPSET_VIRGL2 2
300
301
302struct virtio_gpu_get_capset_info {
303 struct virtio_gpu_ctrl_hdr hdr;
304 uint32_t capset_index;
305 uint32_t padding;
306};
307
308
309struct virtio_gpu_resp_capset_info {
310 struct virtio_gpu_ctrl_hdr hdr;
311 uint32_t capset_id;
312 uint32_t capset_max_version;
313 uint32_t capset_max_size;
314 uint32_t padding;
315};
316
317
318struct virtio_gpu_get_capset {
319 struct virtio_gpu_ctrl_hdr hdr;
320 uint32_t capset_id;
321 uint32_t capset_version;
322};
323
324
325struct virtio_gpu_resp_capset {
326 struct virtio_gpu_ctrl_hdr hdr;
327 uint8_t capset_data[];
328};
329
330
331struct virtio_gpu_cmd_get_edid {
332 struct virtio_gpu_ctrl_hdr hdr;
333 uint32_t scanout;
334 uint32_t padding;
335};
336
337
338struct virtio_gpu_resp_edid {
339 struct virtio_gpu_ctrl_hdr hdr;
340 uint32_t size;
341 uint32_t padding;
342 uint8_t edid[1024];
343};
344
345#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
346
347struct virtio_gpu_config {
348 uint32_t events_read;
349 uint32_t events_clear;
350 uint32_t num_scanouts;
351 uint32_t num_capsets;
352};
353
354
355enum virtio_gpu_formats {
356 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
357 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
358 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
359 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
360
361 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
362 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
363
364 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
365 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
366};
367
368
369struct virtio_gpu_resource_assign_uuid {
370 struct virtio_gpu_ctrl_hdr hdr;
371 uint32_t resource_id;
372 uint32_t padding;
373};
374
375
376struct virtio_gpu_resp_resource_uuid {
377 struct virtio_gpu_ctrl_hdr hdr;
378 uint8_t uuid[16];
379};
380
381
382struct virtio_gpu_resource_create_blob {
383 struct virtio_gpu_ctrl_hdr hdr;
384 uint32_t resource_id;
385#define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001
386#define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002
387#define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003
388
389#define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001
390#define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002
391#define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
392
393 uint32_t blob_mem;
394 uint32_t blob_flags;
395 uint32_t nr_entries;
396 uint64_t blob_id;
397 uint64_t size;
398
399
400
401};
402
403
404struct virtio_gpu_set_scanout_blob {
405 struct virtio_gpu_ctrl_hdr hdr;
406 struct virtio_gpu_rect r;
407 uint32_t scanout_id;
408 uint32_t resource_id;
409 uint32_t width;
410 uint32_t height;
411 uint32_t format;
412 uint32_t padding;
413 uint32_t strides[4];
414 uint32_t offsets[4];
415};
416
417
418struct virtio_gpu_resource_map_blob {
419 struct virtio_gpu_ctrl_hdr hdr;
420 uint32_t resource_id;
421 uint32_t padding;
422 uint64_t offset;
423};
424
425
426#define VIRTIO_GPU_MAP_CACHE_MASK 0x0f
427#define VIRTIO_GPU_MAP_CACHE_NONE 0x00
428#define VIRTIO_GPU_MAP_CACHE_CACHED 0x01
429#define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
430#define VIRTIO_GPU_MAP_CACHE_WC 0x03
431struct virtio_gpu_resp_map_info {
432 struct virtio_gpu_ctrl_hdr hdr;
433 uint32_t map_info;
434 uint32_t padding;
435};
436
437
438struct virtio_gpu_resource_unmap_blob {
439 struct virtio_gpu_ctrl_hdr hdr;
440 uint32_t resource_id;
441 uint32_t padding;
442};
443
444#endif
445