1
2#ifndef _ASM_X86_KVM_H
3#define _ASM_X86_KVM_H
4
5
6
7
8
9
10#include <linux/types.h>
11#include <linux/ioctl.h>
12
13#define KVM_PIO_PAGE_OFFSET 1
14#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
15#define KVM_DIRTY_LOG_PAGE_OFFSET 64
16
17#define DE_VECTOR 0
18#define DB_VECTOR 1
19#define BP_VECTOR 3
20#define OF_VECTOR 4
21#define BR_VECTOR 5
22#define UD_VECTOR 6
23#define NM_VECTOR 7
24#define DF_VECTOR 8
25#define TS_VECTOR 10
26#define NP_VECTOR 11
27#define SS_VECTOR 12
28#define GP_VECTOR 13
29#define PF_VECTOR 14
30#define MF_VECTOR 16
31#define AC_VECTOR 17
32#define MC_VECTOR 18
33#define XM_VECTOR 19
34#define VE_VECTOR 20
35
36
37#define __KVM_HAVE_PIT
38#define __KVM_HAVE_IOAPIC
39#define __KVM_HAVE_IRQ_LINE
40#define __KVM_HAVE_MSI
41#define __KVM_HAVE_USER_NMI
42#define __KVM_HAVE_GUEST_DEBUG
43#define __KVM_HAVE_MSIX
44#define __KVM_HAVE_MCE
45#define __KVM_HAVE_PIT_STATE2
46#define __KVM_HAVE_XEN_HVM
47#define __KVM_HAVE_VCPU_EVENTS
48#define __KVM_HAVE_DEBUGREGS
49#define __KVM_HAVE_XSAVE
50#define __KVM_HAVE_XCRS
51#define __KVM_HAVE_READONLY_MEM
52
53
54#define KVM_NR_INTERRUPTS 256
55
56struct kvm_memory_alias {
57 __u32 slot;
58 __u32 flags;
59 __u64 guest_phys_addr;
60 __u64 memory_size;
61 __u64 target_phys_addr;
62};
63
64
65struct kvm_pic_state {
66 __u8 last_irr;
67 __u8 irr;
68 __u8 imr;
69 __u8 isr;
70 __u8 priority_add;
71 __u8 irq_base;
72 __u8 read_reg_select;
73 __u8 poll;
74 __u8 special_mask;
75 __u8 init_state;
76 __u8 auto_eoi;
77 __u8 rotate_on_auto_eoi;
78 __u8 special_fully_nested_mode;
79 __u8 init4;
80 __u8 elcr;
81 __u8 elcr_mask;
82};
83
84#define KVM_IOAPIC_NUM_PINS 24
85struct kvm_ioapic_state {
86 __u64 base_address;
87 __u32 ioregsel;
88 __u32 id;
89 __u32 irr;
90 __u32 pad;
91 union {
92 __u64 bits;
93 struct {
94 __u8 vector;
95 __u8 delivery_mode:3;
96 __u8 dest_mode:1;
97 __u8 delivery_status:1;
98 __u8 polarity:1;
99 __u8 remote_irr:1;
100 __u8 trig_mode:1;
101 __u8 mask:1;
102 __u8 reserve:7;
103 __u8 reserved[4];
104 __u8 dest_id;
105 } fields;
106 } redirtbl[KVM_IOAPIC_NUM_PINS];
107};
108
109#define KVM_IRQCHIP_PIC_MASTER 0
110#define KVM_IRQCHIP_PIC_SLAVE 1
111#define KVM_IRQCHIP_IOAPIC 2
112#define KVM_NR_IRQCHIPS 3
113
114#define KVM_RUN_X86_SMM (1 << 0)
115
116
117struct kvm_regs {
118
119 __u64 rax, rbx, rcx, rdx;
120 __u64 rsi, rdi, rsp, rbp;
121 __u64 r8, r9, r10, r11;
122 __u64 r12, r13, r14, r15;
123 __u64 rip, rflags;
124};
125
126
127#define KVM_APIC_REG_SIZE 0x400
128struct kvm_lapic_state {
129 char regs[KVM_APIC_REG_SIZE];
130};
131
132struct kvm_segment {
133 __u64 base;
134 __u32 limit;
135 __u16 selector;
136 __u8 type;
137 __u8 present, dpl, db, s, l, g, avl;
138 __u8 unusable;
139 __u8 padding;
140};
141
142struct kvm_dtable {
143 __u64 base;
144 __u16 limit;
145 __u16 padding[3];
146};
147
148
149
150struct kvm_sregs {
151
152 struct kvm_segment cs, ds, es, fs, gs, ss;
153 struct kvm_segment tr, ldt;
154 struct kvm_dtable gdt, idt;
155 __u64 cr0, cr2, cr3, cr4, cr8;
156 __u64 efer;
157 __u64 apic_base;
158 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
159};
160
161
162struct kvm_fpu {
163 __u8 fpr[8][16];
164 __u16 fcw;
165 __u16 fsw;
166 __u8 ftwx;
167 __u8 pad1;
168 __u16 last_opcode;
169 __u64 last_ip;
170 __u64 last_dp;
171 __u8 xmm[16][16];
172 __u32 mxcsr;
173 __u32 pad2;
174};
175
176struct kvm_msr_entry {
177 __u32 index;
178 __u32 reserved;
179 __u64 data;
180};
181
182
183struct kvm_msrs {
184 __u32 nmsrs;
185 __u32 pad;
186
187 struct kvm_msr_entry entries[0];
188};
189
190
191struct kvm_msr_list {
192 __u32 nmsrs;
193 __u32 indices[0];
194};
195
196
197#define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600
198
199
200struct kvm_msr_filter_range {
201#define KVM_MSR_FILTER_READ (1 << 0)
202#define KVM_MSR_FILTER_WRITE (1 << 1)
203 __u32 flags;
204 __u32 nmsrs;
205 __u32 base;
206 __u8 *bitmap;
207};
208
209#define KVM_MSR_FILTER_MAX_RANGES 16
210struct kvm_msr_filter {
211#define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0)
212#define KVM_MSR_FILTER_DEFAULT_DENY (1 << 0)
213 __u32 flags;
214 struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES];
215};
216
217struct kvm_cpuid_entry {
218 __u32 function;
219 __u32 eax;
220 __u32 ebx;
221 __u32 ecx;
222 __u32 edx;
223 __u32 padding;
224};
225
226
227struct kvm_cpuid {
228 __u32 nent;
229 __u32 padding;
230 struct kvm_cpuid_entry entries[0];
231};
232
233struct kvm_cpuid_entry2 {
234 __u32 function;
235 __u32 index;
236 __u32 flags;
237 __u32 eax;
238 __u32 ebx;
239 __u32 ecx;
240 __u32 edx;
241 __u32 padding[3];
242};
243
244#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0)
245#define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1)
246#define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2)
247
248
249struct kvm_cpuid2 {
250 __u32 nent;
251 __u32 padding;
252 struct kvm_cpuid_entry2 entries[0];
253};
254
255
256struct kvm_pit_channel_state {
257 __u32 count;
258 __u16 latched_count;
259 __u8 count_latched;
260 __u8 status_latched;
261 __u8 status;
262 __u8 read_state;
263 __u8 write_state;
264 __u8 write_latch;
265 __u8 rw_mode;
266 __u8 mode;
267 __u8 bcd;
268 __u8 gate;
269 __s64 count_load_time;
270};
271
272struct kvm_debug_exit_arch {
273 __u32 exception;
274 __u32 pad;
275 __u64 pc;
276 __u64 dr6;
277 __u64 dr7;
278};
279
280#define KVM_GUESTDBG_USE_SW_BP 0x00010000
281#define KVM_GUESTDBG_USE_HW_BP 0x00020000
282#define KVM_GUESTDBG_INJECT_DB 0x00040000
283#define KVM_GUESTDBG_INJECT_BP 0x00080000
284
285
286struct kvm_guest_debug_arch {
287 __u64 debugreg[8];
288};
289
290struct kvm_pit_state {
291 struct kvm_pit_channel_state channels[3];
292};
293
294#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
295
296struct kvm_pit_state2 {
297 struct kvm_pit_channel_state channels[3];
298 __u32 flags;
299 __u32 reserved[9];
300};
301
302struct kvm_reinject_control {
303 __u8 pit_reinject;
304 __u8 reserved[31];
305};
306
307
308#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
309#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
310#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
311#define KVM_VCPUEVENT_VALID_SMM 0x00000008
312#define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010
313
314
315#define KVM_X86_SHADOW_INT_MOV_SS 0x01
316#define KVM_X86_SHADOW_INT_STI 0x02
317
318
319struct kvm_vcpu_events {
320 struct {
321 __u8 injected;
322 __u8 nr;
323 __u8 has_error_code;
324 __u8 pending;
325 __u32 error_code;
326 } exception;
327 struct {
328 __u8 injected;
329 __u8 nr;
330 __u8 soft;
331 __u8 shadow;
332 } interrupt;
333 struct {
334 __u8 injected;
335 __u8 pending;
336 __u8 masked;
337 __u8 pad;
338 } nmi;
339 __u32 sipi_vector;
340 __u32 flags;
341 struct {
342 __u8 smm;
343 __u8 pending;
344 __u8 smm_inside_nmi;
345 __u8 latched_init;
346 } smi;
347 __u8 reserved[27];
348 __u8 exception_has_payload;
349 __u64 exception_payload;
350};
351
352
353struct kvm_debugregs {
354 __u64 db[4];
355 __u64 dr6;
356 __u64 dr7;
357 __u64 flags;
358 __u64 reserved[9];
359};
360
361
362struct kvm_xsave {
363 __u32 region[1024];
364};
365
366#define KVM_MAX_XCRS 16
367
368struct kvm_xcr {
369 __u32 xcr;
370 __u32 reserved;
371 __u64 value;
372};
373
374struct kvm_xcrs {
375 __u32 nr_xcrs;
376 __u32 flags;
377 struct kvm_xcr xcrs[KVM_MAX_XCRS];
378 __u64 padding[16];
379};
380
381#define KVM_SYNC_X86_REGS (1UL << 0)
382#define KVM_SYNC_X86_SREGS (1UL << 1)
383#define KVM_SYNC_X86_EVENTS (1UL << 2)
384
385#define KVM_SYNC_X86_VALID_FIELDS \
386 (KVM_SYNC_X86_REGS| \
387 KVM_SYNC_X86_SREGS| \
388 KVM_SYNC_X86_EVENTS)
389
390
391struct kvm_sync_regs {
392
393
394
395
396
397 struct kvm_regs regs;
398 struct kvm_sregs sregs;
399 struct kvm_vcpu_events events;
400};
401
402#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0)
403#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1)
404#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2)
405#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3)
406#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4)
407
408#define KVM_STATE_NESTED_FORMAT_VMX 0
409#define KVM_STATE_NESTED_FORMAT_SVM 1
410
411#define KVM_STATE_NESTED_GUEST_MODE 0x00000001
412#define KVM_STATE_NESTED_RUN_PENDING 0x00000002
413#define KVM_STATE_NESTED_EVMCS 0x00000004
414#define KVM_STATE_NESTED_MTF_PENDING 0x00000008
415#define KVM_STATE_NESTED_GIF_SET 0x00000100
416
417#define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001
418#define KVM_STATE_NESTED_SMM_VMXON 0x00000002
419
420#define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000
421
422#define KVM_STATE_NESTED_SVM_VMCB_SIZE 0x1000
423
424#define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001
425
426struct kvm_vmx_nested_state_data {
427 __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
428 __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
429};
430
431struct kvm_vmx_nested_state_hdr {
432 __u64 vmxon_pa;
433 __u64 vmcs12_pa;
434
435 struct {
436 __u16 flags;
437 } smm;
438
439 __u32 flags;
440 __u64 preemption_timer_deadline;
441};
442
443struct kvm_svm_nested_state_data {
444
445 __u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE];
446};
447
448struct kvm_svm_nested_state_hdr {
449 __u64 vmcb_pa;
450};
451
452
453struct kvm_nested_state {
454 __u16 flags;
455 __u16 format;
456 __u32 size;
457
458 union {
459 struct kvm_vmx_nested_state_hdr vmx;
460 struct kvm_svm_nested_state_hdr svm;
461
462
463 __u8 pad[120];
464 } hdr;
465
466
467
468
469
470
471 union {
472 struct kvm_vmx_nested_state_data vmx[0];
473 struct kvm_svm_nested_state_data svm[0];
474 } data;
475};
476
477
478struct kvm_pmu_event_filter {
479 __u32 action;
480 __u32 nevents;
481 __u32 fixed_counter_bitmap;
482 __u32 flags;
483 __u32 pad[4];
484 __u64 events[0];
485};
486
487#define KVM_PMU_EVENT_ALLOW 0
488#define KVM_PMU_EVENT_DENY 1
489
490#endif
491
