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20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "hw/registerfields.h"
25#include "cpu-qom.h"
26#include "exec/cpu-defs.h"
27#include "qapi/qapi-types-common.h"
28
29
30#define TCG_GUEST_DEFAULT_MO (0)
31
32#ifdef TARGET_AARCH64
33#define KVM_HAVE_MCE_INJECTION 1
34#endif
35
36#define EXCP_UDEF 1
37#define EXCP_SWI 2
38#define EXCP_PREFETCH_ABORT 3
39#define EXCP_DATA_ABORT 4
40#define EXCP_IRQ 5
41#define EXCP_FIQ 6
42#define EXCP_BKPT 7
43#define EXCP_EXCEPTION_EXIT 8
44#define EXCP_KERNEL_TRAP 9
45#define EXCP_HVC 11
46#define EXCP_HYP_TRAP 12
47#define EXCP_SMC 13
48#define EXCP_VIRQ 14
49#define EXCP_VFIQ 15
50#define EXCP_SEMIHOST 16
51#define EXCP_NOCP 17
52#define EXCP_INVSTATE 18
53#define EXCP_STKOF 19
54#define EXCP_LAZYFP 20
55#define EXCP_LSERR 21
56#define EXCP_UNALIGNED 22
57
58
59#define ARMV7M_EXCP_RESET 1
60#define ARMV7M_EXCP_NMI 2
61#define ARMV7M_EXCP_HARD 3
62#define ARMV7M_EXCP_MEM 4
63#define ARMV7M_EXCP_BUS 5
64#define ARMV7M_EXCP_USAGE 6
65#define ARMV7M_EXCP_SECURE 7
66#define ARMV7M_EXCP_SVC 11
67#define ARMV7M_EXCP_DEBUG 12
68#define ARMV7M_EXCP_PENDSV 14
69#define ARMV7M_EXCP_SYSTICK 15
70
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79
80enum {
81 M_REG_NS = 0,
82 M_REG_S = 1,
83 M_REG_NUM_BANKS = 2,
84};
85
86
87#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
88#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
89#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
90
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96
97#ifdef HOST_WORDS_BIGENDIAN
98#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
99#define offsetofhigh32(S, M) offsetof(S, M)
100#else
101#define offsetoflow32(S, M) offsetof(S, M)
102#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
103#endif
104
105
106#define ARM_CPU_IRQ 0
107#define ARM_CPU_FIQ 1
108#define ARM_CPU_VIRQ 2
109#define ARM_CPU_VFIQ 3
110
111
112
113
114
115#define TARGET_INSN_START_EXTRA_WORDS 2
116
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121
122#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
123#define ARM_INSN_START_WORD2_SHIFT 14
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141
142typedef struct DynamicGDBXMLInfo {
143 char *desc;
144 int num;
145 union {
146 struct {
147 uint32_t *keys;
148 } cpregs;
149 } data;
150} DynamicGDBXMLInfo;
151
152
153typedef struct ARMGenericTimer {
154 uint64_t cval;
155 uint64_t ctl;
156} ARMGenericTimer;
157
158#define GTIMER_PHYS 0
159#define GTIMER_VIRT 1
160#define GTIMER_HYP 2
161#define GTIMER_SEC 3
162#define GTIMER_HYPVIRT 4
163#define NUM_GTIMERS 5
164
165typedef struct {
166 uint64_t raw_tcr;
167 uint32_t mask;
168 uint32_t base_mask;
169} TCR;
170
171#define VTCR_NSW (1u << 29)
172#define VTCR_NSA (1u << 30)
173#define VSTCR_SW VTCR_NSW
174#define VSTCR_SA VTCR_NSA
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202#ifdef TARGET_AARCH64
203# define ARM_MAX_VQ 16
204void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
205void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
206#else
207# define ARM_MAX_VQ 1
208static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
209static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { }
210#endif
211
212typedef struct ARMVectorReg {
213 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
214} ARMVectorReg;
215
216#ifdef TARGET_AARCH64
217
218typedef struct ARMPredicateReg {
219 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
220} ARMPredicateReg;
221
222
223typedef struct ARMPACKey {
224 uint64_t lo, hi;
225} ARMPACKey;
226#endif
227
228
229typedef struct CPUARMState {
230
231 uint32_t regs[16];
232
233
234
235
236
237
238 uint64_t xregs[32];
239 uint64_t pc;
240
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251
252 uint32_t pstate;
253 uint32_t aarch64;
254
255
256 uint32_t hflags;
257
258
259
260
261 uint32_t uncached_cpsr;
262 uint32_t spsr;
263
264
265 uint64_t banked_spsr[8];
266 uint32_t banked_r13[8];
267 uint32_t banked_r14[8];
268
269
270 uint32_t usr_regs[5];
271 uint32_t fiq_regs[5];
272
273
274 uint32_t CF;
275 uint32_t VF;
276 uint32_t NF;
277 uint32_t ZF;
278 uint32_t QF;
279 uint32_t GE;
280 uint32_t thumb;
281 uint32_t condexec_bits;
282 uint32_t btype;
283 uint64_t daif;
284
285 uint64_t elr_el[4];
286 uint64_t sp_el[4];
287
288
289 struct {
290 uint32_t c0_cpuid;
291 union {
292 struct {
293 uint64_t _unused_csselr0;
294 uint64_t csselr_ns;
295 uint64_t _unused_csselr1;
296 uint64_t csselr_s;
297 };
298 uint64_t csselr_el[4];
299 };
300 union {
301 struct {
302 uint64_t _unused_sctlr;
303 uint64_t sctlr_ns;
304 uint64_t hsctlr;
305 uint64_t sctlr_s;
306 };
307 uint64_t sctlr_el[4];
308 };
309 uint64_t cpacr_el1;
310 uint64_t cptr_el[4];
311 uint32_t c1_xscaleauxcr;
312 uint64_t sder;
313 uint32_t nsacr;
314 union {
315 struct {
316 uint64_t _unused_ttbr0_0;
317 uint64_t ttbr0_ns;
318 uint64_t _unused_ttbr0_1;
319 uint64_t ttbr0_s;
320 };
321 uint64_t ttbr0_el[4];
322 };
323 union {
324 struct {
325 uint64_t _unused_ttbr1_0;
326 uint64_t ttbr1_ns;
327 uint64_t _unused_ttbr1_1;
328 uint64_t ttbr1_s;
329 };
330 uint64_t ttbr1_el[4];
331 };
332 uint64_t vttbr_el2;
333 uint64_t vsttbr_el2;
334
335 TCR tcr_el[4];
336 TCR vtcr_el2;
337 TCR vstcr_el2;
338 uint32_t c2_data;
339 uint32_t c2_insn;
340 union {
341
342
343 struct {
344 uint64_t dacr_ns;
345 uint64_t dacr_s;
346 };
347 struct {
348 uint64_t dacr32_el2;
349 };
350 };
351 uint32_t pmsav5_data_ap;
352 uint32_t pmsav5_insn_ap;
353 uint64_t hcr_el2;
354 uint64_t scr_el3;
355 union {
356 struct {
357 uint64_t ifsr_ns;
358 uint64_t ifsr_s;
359 };
360 struct {
361 uint64_t ifsr32_el2;
362 };
363 };
364 union {
365 struct {
366 uint64_t _unused_dfsr;
367 uint64_t dfsr_ns;
368 uint64_t hsr;
369 uint64_t dfsr_s;
370 };
371 uint64_t esr_el[4];
372 };
373 uint32_t c6_region[8];
374 union {
375 struct {
376 uint64_t _unused_far0;
377#ifdef HOST_WORDS_BIGENDIAN
378 uint32_t ifar_ns;
379 uint32_t dfar_ns;
380 uint32_t ifar_s;
381 uint32_t dfar_s;
382#else
383 uint32_t dfar_ns;
384 uint32_t ifar_ns;
385 uint32_t dfar_s;
386 uint32_t ifar_s;
387#endif
388 uint64_t _unused_far3;
389 };
390 uint64_t far_el[4];
391 };
392 uint64_t hpfar_el2;
393 uint64_t hstr_el2;
394 union {
395 struct {
396 uint64_t _unused_par_0;
397 uint64_t par_ns;
398 uint64_t _unused_par_1;
399 uint64_t par_s;
400 };
401 uint64_t par_el[4];
402 };
403
404 uint32_t c9_insn;
405 uint32_t c9_data;
406 uint64_t c9_pmcr;
407 uint64_t c9_pmcnten;
408 uint64_t c9_pmovsr;
409 uint64_t c9_pmuserenr;
410 uint64_t c9_pmselr;
411 uint64_t c9_pminten;
412 union {
413 struct {
414#ifdef HOST_WORDS_BIGENDIAN
415 uint64_t _unused_mair_0;
416 uint32_t mair1_ns;
417 uint32_t mair0_ns;
418 uint64_t _unused_mair_1;
419 uint32_t mair1_s;
420 uint32_t mair0_s;
421#else
422 uint64_t _unused_mair_0;
423 uint32_t mair0_ns;
424 uint32_t mair1_ns;
425 uint64_t _unused_mair_1;
426 uint32_t mair0_s;
427 uint32_t mair1_s;
428#endif
429 };
430 uint64_t mair_el[4];
431 };
432 union {
433 struct {
434 uint64_t _unused_vbar;
435 uint64_t vbar_ns;
436 uint64_t hvbar;
437 uint64_t vbar_s;
438 };
439 uint64_t vbar_el[4];
440 };
441 uint32_t mvbar;
442 struct {
443 uint32_t fcseidr_ns;
444 uint32_t fcseidr_s;
445 };
446 union {
447 struct {
448 uint64_t _unused_contextidr_0;
449 uint64_t contextidr_ns;
450 uint64_t _unused_contextidr_1;
451 uint64_t contextidr_s;
452 };
453 uint64_t contextidr_el[4];
454 };
455 union {
456 struct {
457 uint64_t tpidrurw_ns;
458 uint64_t tpidrprw_ns;
459 uint64_t htpidr;
460 uint64_t _tpidr_el3;
461 };
462 uint64_t tpidr_el[4];
463 };
464
465 uint64_t tpidrurw_s;
466 uint64_t tpidrprw_s;
467 uint64_t tpidruro_s;
468
469 union {
470 uint64_t tpidruro_ns;
471 uint64_t tpidrro_el[1];
472 };
473 uint64_t c14_cntfrq;
474 uint64_t c14_cntkctl;
475 uint32_t cnthctl_el2;
476 uint64_t cntvoff_el2;
477 ARMGenericTimer c14_timer[NUM_GTIMERS];
478 uint32_t c15_cpar;
479 uint32_t c15_ticonfig;
480 uint32_t c15_i_max;
481 uint32_t c15_i_min;
482 uint32_t c15_threadid;
483 uint32_t c15_config_base_address;
484 uint32_t c15_diagnostic;
485 uint32_t c15_power_diagnostic;
486 uint32_t c15_power_control;
487 uint64_t dbgbvr[16];
488 uint64_t dbgbcr[16];
489 uint64_t dbgwvr[16];
490 uint64_t dbgwcr[16];
491 uint64_t mdscr_el1;
492 uint64_t oslsr_el1;
493 uint64_t mdcr_el2;
494 uint64_t mdcr_el3;
495
496
497
498
499
500 uint64_t c15_ccnt;
501
502
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507
508 uint64_t c15_ccnt_delta;
509 uint64_t c14_pmevcntr[31];
510 uint64_t c14_pmevcntr_delta[31];
511 uint64_t c14_pmevtyper[31];
512 uint64_t pmccfiltr_el0;
513 uint64_t vpidr_el2;
514 uint64_t vmpidr_el2;
515 uint64_t tfsr_el[4];
516 uint64_t gcr_el1;
517 uint64_t rgsr_el1;
518 } cp15;
519
520 struct {
521
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531
532 uint32_t other_sp;
533 uint32_t other_ss_msp;
534 uint32_t other_ss_psp;
535 uint32_t vecbase[M_REG_NUM_BANKS];
536 uint32_t basepri[M_REG_NUM_BANKS];
537 uint32_t control[M_REG_NUM_BANKS];
538 uint32_t ccr[M_REG_NUM_BANKS];
539 uint32_t cfsr[M_REG_NUM_BANKS];
540 uint32_t hfsr;
541 uint32_t dfsr;
542 uint32_t sfsr;
543 uint32_t mmfar[M_REG_NUM_BANKS];
544 uint32_t bfar;
545 uint32_t sfar;
546 unsigned mpu_ctrl[M_REG_NUM_BANKS];
547 int exception;
548 uint32_t primask[M_REG_NUM_BANKS];
549 uint32_t faultmask[M_REG_NUM_BANKS];
550 uint32_t aircr;
551 uint32_t secure;
552 uint32_t csselr[M_REG_NUM_BANKS];
553 uint32_t scr[M_REG_NUM_BANKS];
554 uint32_t msplim[M_REG_NUM_BANKS];
555 uint32_t psplim[M_REG_NUM_BANKS];
556 uint32_t fpcar[M_REG_NUM_BANKS];
557 uint32_t fpccr[M_REG_NUM_BANKS];
558 uint32_t fpdscr[M_REG_NUM_BANKS];
559 uint32_t cpacr[M_REG_NUM_BANKS];
560 uint32_t nsacr;
561 int ltpsize;
562 } v7m;
563
564
565
566
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568
569
570 struct {
571 uint32_t syndrome;
572 uint32_t fsr;
573 uint64_t vaddress;
574 uint32_t target_el;
575
576
577
578 } exception;
579
580
581 struct {
582 uint8_t pending;
583 uint8_t has_esr;
584 uint64_t esr;
585 } serror;
586
587 uint8_t ext_dabt_raised;
588
589
590 uint32_t irq_line_state;
591
592
593 uint32_t teecr;
594 uint32_t teehbr;
595
596
597 struct {
598 ARMVectorReg zregs[32];
599
600#ifdef TARGET_AARCH64
601
602#define FFR_PRED_NUM 16
603 ARMPredicateReg pregs[17];
604
605 ARMPredicateReg preg_tmp;
606#endif
607
608
609 uint32_t qc[4] QEMU_ALIGNED(16);
610 int vec_len;
611 int vec_stride;
612
613 uint32_t xregs[16];
614
615
616 uint32_t scratch[8];
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645 float_status fp_status;
646 float_status fp_status_f16;
647 float_status standard_fp_status;
648 float_status standard_fp_status_f16;
649
650
651 uint64_t zcr_el[4];
652 } vfp;
653 uint64_t exclusive_addr;
654 uint64_t exclusive_val;
655 uint64_t exclusive_high;
656
657
658 struct {
659 uint64_t regs[16];
660 uint64_t val;
661
662 uint32_t cregs[16];
663 } iwmmxt;
664
665#ifdef TARGET_AARCH64
666 struct {
667 ARMPACKey apia;
668 ARMPACKey apib;
669 ARMPACKey apda;
670 ARMPACKey apdb;
671 ARMPACKey apga;
672 } keys;
673#endif
674
675#if defined(CONFIG_USER_ONLY)
676
677 int eabi;
678#endif
679
680 struct CPUBreakpoint *cpu_breakpoint[16];
681 struct CPUWatchpoint *cpu_watchpoint[16];
682
683
684 struct {} end_reset_fields;
685
686
687
688
689 uint64_t features;
690
691
692 struct {
693 uint32_t *drbar;
694 uint32_t *drsr;
695 uint32_t *dracr;
696 uint32_t rnr[M_REG_NUM_BANKS];
697 } pmsav7;
698
699
700 struct {
701
702
703
704
705
706 uint32_t *rbar[M_REG_NUM_BANKS];
707 uint32_t *rlar[M_REG_NUM_BANKS];
708 uint32_t mair0[M_REG_NUM_BANKS];
709 uint32_t mair1[M_REG_NUM_BANKS];
710 } pmsav8;
711
712
713 struct {
714 uint32_t *rbar;
715 uint32_t *rlar;
716 uint32_t rnr;
717 uint32_t ctrl;
718 } sau;
719
720 void *nvic;
721 const struct arm_boot_info *boot_info;
722
723 void *gicv3state;
724
725#ifdef TARGET_TAGGED_ADDRESSES
726
727 bool tagged_addr_enable;
728#endif
729} CPUARMState;
730
731static inline void set_feature(CPUARMState *env, int feature)
732{
733 env->features |= 1ULL << feature;
734}
735
736static inline void unset_feature(CPUARMState *env, int feature)
737{
738 env->features &= ~(1ULL << feature);
739}
740
741
742
743
744
745
746typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
747typedef struct ARMELChangeHook ARMELChangeHook;
748struct ARMELChangeHook {
749 ARMELChangeHookFn *hook;
750 void *opaque;
751 QLIST_ENTRY(ARMELChangeHook) node;
752};
753
754
755
756typedef enum ARMPSCIState {
757 PSCI_ON = 0,
758 PSCI_OFF = 1,
759 PSCI_ON_PENDING = 2
760} ARMPSCIState;
761
762typedef struct ARMISARegisters ARMISARegisters;
763
764
765
766
767
768
769
770struct ARMCPU {
771
772 CPUState parent_obj;
773
774
775 CPUNegativeOffsetState neg;
776 CPUARMState env;
777
778
779 GHashTable *cp_regs;
780
781
782
783
784
785
786
787 uint64_t *cpreg_indexes;
788
789 uint64_t *cpreg_values;
790
791 int32_t cpreg_array_len;
792
793
794
795
796 uint64_t *cpreg_vmstate_indexes;
797 uint64_t *cpreg_vmstate_values;
798 int32_t cpreg_vmstate_array_len;
799
800 DynamicGDBXMLInfo dyn_sysreg_xml;
801 DynamicGDBXMLInfo dyn_svereg_xml;
802
803
804 QEMUTimer *gt_timer[NUM_GTIMERS];
805
806
807
808
809 QEMUTimer *pmu_timer;
810
811 qemu_irq gt_timer_outputs[NUM_GTIMERS];
812
813 qemu_irq gicv3_maintenance_interrupt;
814
815 qemu_irq pmu_interrupt;
816
817
818 MemoryRegion *secure_memory;
819
820
821 MemoryRegion *tag_memory;
822 MemoryRegion *secure_tag_memory;
823
824
825 Object *idau;
826
827
828 const char *dtb_compatible;
829
830
831
832
833
834 uint32_t psci_version;
835
836
837 ARMPSCIState power_state;
838
839
840 bool has_el2;
841
842 bool has_el3;
843
844 bool has_pmu;
845
846 bool has_vfp;
847
848 bool has_neon;
849
850 bool has_dsp;
851
852
853 bool has_mpu;
854
855 uint32_t pmsav7_dregion;
856
857 uint32_t sau_sregion;
858
859
860
861
862 uint32_t psci_conduit;
863
864
865 uint32_t init_svtor;
866
867
868
869
870 uint32_t kvm_target;
871
872
873 uint32_t kvm_init_features[7];
874
875
876
877
878 bool kvm_adjvtime;
879 bool kvm_vtime_dirty;
880 uint64_t kvm_vtime;
881
882
883 OnOffAuto kvm_steal_time;
884
885
886 bool mp_is_up;
887
888
889
890
891 bool host_cpu_probe_failed;
892
893
894
895
896 int32_t core_count;
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914
915 struct ARMISARegisters {
916 uint32_t id_isar0;
917 uint32_t id_isar1;
918 uint32_t id_isar2;
919 uint32_t id_isar3;
920 uint32_t id_isar4;
921 uint32_t id_isar5;
922 uint32_t id_isar6;
923 uint32_t id_mmfr0;
924 uint32_t id_mmfr1;
925 uint32_t id_mmfr2;
926 uint32_t id_mmfr3;
927 uint32_t id_mmfr4;
928 uint32_t id_pfr0;
929 uint32_t id_pfr1;
930 uint32_t id_pfr2;
931 uint32_t mvfr0;
932 uint32_t mvfr1;
933 uint32_t mvfr2;
934 uint32_t id_dfr0;
935 uint32_t dbgdidr;
936 uint64_t id_aa64isar0;
937 uint64_t id_aa64isar1;
938 uint64_t id_aa64pfr0;
939 uint64_t id_aa64pfr1;
940 uint64_t id_aa64mmfr0;
941 uint64_t id_aa64mmfr1;
942 uint64_t id_aa64mmfr2;
943 uint64_t id_aa64dfr0;
944 uint64_t id_aa64dfr1;
945 } isar;
946 uint64_t midr;
947 uint32_t revidr;
948 uint32_t reset_fpsid;
949 uint64_t ctr;
950 uint32_t reset_sctlr;
951 uint64_t pmceid0;
952 uint64_t pmceid1;
953 uint32_t id_afr0;
954 uint64_t id_aa64afr0;
955 uint64_t id_aa64afr1;
956 uint64_t clidr;
957 uint64_t mp_affinity;
958
959
960
961 uint64_t ccsidr[16];
962 uint64_t reset_cbar;
963 uint32_t reset_auxcr;
964 bool reset_hivecs;
965
966
967
968
969
970 bool prop_pauth;
971 bool prop_pauth_impdef;
972
973
974 uint32_t dcz_blocksize;
975 uint64_t rvbar;
976
977
978 int gic_num_lrs;
979 int gic_vpribits;
980 int gic_vprebits;
981
982
983
984
985
986
987 bool cfgend;
988
989 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
990 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
991
992 int32_t node_id;
993
994
995 uint8_t device_irq_level;
996
997
998 uint32_t sve_max_vq;
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
1010 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
1011
1012
1013 uint64_t gt_cntfrq_hz;
1014};
1015
1016unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1017
1018void arm_cpu_post_init(Object *obj);
1019
1020uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
1021
1022#ifndef CONFIG_USER_ONLY
1023extern const VMStateDescription vmstate_arm_cpu;
1024#endif
1025
1026void arm_cpu_do_interrupt(CPUState *cpu);
1027void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1028bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
1029
1030hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1031 MemTxAttrs *attrs);
1032
1033int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1034int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1035
1036
1037
1038
1039
1040int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1041int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1042
1043
1044
1045
1046
1047const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1048
1049int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1050 int cpuid, void *opaque);
1051int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1052 int cpuid, void *opaque);
1053
1054#ifdef TARGET_AARCH64
1055int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1056int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1057void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1058void aarch64_sve_change_el(CPUARMState *env, int old_el,
1059 int new_el, bool el0_a64);
1060void aarch64_add_sve_properties(Object *obj);
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1072{
1073#ifdef HOST_WORDS_BIGENDIAN
1074 int i;
1075
1076 for (i = 0; i < nr; ++i) {
1077 dst[i] = bswap64(src[i]);
1078 }
1079
1080 return dst;
1081#else
1082 return src;
1083#endif
1084}
1085
1086#else
1087static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1088static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1089 int n, bool a)
1090{ }
1091static inline void aarch64_add_sve_properties(Object *obj) { }
1092#endif
1093
1094void aarch64_sync_32_to_64(CPUARMState *env);
1095void aarch64_sync_64_to_32(CPUARMState *env);
1096
1097int fp_exception_el(CPUARMState *env, int cur_el);
1098int sve_exception_el(CPUARMState *env, int cur_el);
1099uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1100
1101static inline bool is_a64(CPUARMState *env)
1102{
1103 return env->aarch64;
1104}
1105
1106
1107
1108
1109int cpu_arm_signal_handler(int host_signum, void *pinfo,
1110 void *puc);
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120void pmu_op_start(CPUARMState *env);
1121void pmu_op_finish(CPUARMState *env);
1122
1123
1124
1125
1126void arm_pmu_timer_cb(void *opaque);
1127
1128
1129
1130
1131void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1132void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1133
1134
1135
1136
1137
1138
1139
1140
1141void pmu_init(ARMCPU *cpu);
1142
1143
1144
1145
1146
1147
1148
1149#define SCTLR_M (1U << 0)
1150#define SCTLR_A (1U << 1)
1151#define SCTLR_C (1U << 2)
1152#define SCTLR_W (1U << 3)
1153#define SCTLR_nTLSMD_32 (1U << 3)
1154#define SCTLR_SA (1U << 3)
1155#define SCTLR_P (1U << 4)
1156#define SCTLR_LSMAOE_32 (1U << 4)
1157#define SCTLR_SA0 (1U << 4)
1158#define SCTLR_D (1U << 5)
1159#define SCTLR_CP15BEN (1U << 5)
1160#define SCTLR_L (1U << 6)
1161#define SCTLR_nAA (1U << 6)
1162#define SCTLR_B (1U << 7)
1163#define SCTLR_ITD (1U << 7)
1164#define SCTLR_S (1U << 8)
1165#define SCTLR_SED (1U << 8)
1166#define SCTLR_R (1U << 9)
1167#define SCTLR_UMA (1U << 9)
1168#define SCTLR_F (1U << 10)
1169#define SCTLR_SW (1U << 10)
1170#define SCTLR_EnRCTX (1U << 10)
1171#define SCTLR_Z (1U << 11)
1172#define SCTLR_EOS (1U << 11)
1173#define SCTLR_I (1U << 12)
1174#define SCTLR_V (1U << 13)
1175#define SCTLR_EnDB (1U << 13)
1176#define SCTLR_RR (1U << 14)
1177#define SCTLR_DZE (1U << 14)
1178#define SCTLR_L4 (1U << 15)
1179#define SCTLR_UCT (1U << 15)
1180#define SCTLR_DT (1U << 16)
1181#define SCTLR_nTWI (1U << 16)
1182#define SCTLR_HA (1U << 17)
1183#define SCTLR_BR (1U << 17)
1184#define SCTLR_IT (1U << 18)
1185#define SCTLR_nTWE (1U << 18)
1186#define SCTLR_WXN (1U << 19)
1187#define SCTLR_ST (1U << 20)
1188#define SCTLR_UWXN (1U << 20)
1189#define SCTLR_FI (1U << 21)
1190#define SCTLR_IESB (1U << 21)
1191#define SCTLR_U (1U << 22)
1192#define SCTLR_EIS (1U << 22)
1193#define SCTLR_XP (1U << 23)
1194#define SCTLR_SPAN (1U << 23)
1195#define SCTLR_VE (1U << 24)
1196#define SCTLR_E0E (1U << 24)
1197#define SCTLR_EE (1U << 25)
1198#define SCTLR_L2 (1U << 26)
1199#define SCTLR_UCI (1U << 26)
1200#define SCTLR_NMFI (1U << 27)
1201#define SCTLR_EnDA (1U << 27)
1202#define SCTLR_TRE (1U << 28)
1203#define SCTLR_nTLSMD_64 (1U << 28)
1204#define SCTLR_AFE (1U << 29)
1205#define SCTLR_LSMAOE_64 (1U << 29)
1206#define SCTLR_TE (1U << 30)
1207#define SCTLR_EnIB (1U << 30)
1208#define SCTLR_EnIA (1U << 31)
1209#define SCTLR_DSSBS_32 (1U << 31)
1210#define SCTLR_BT0 (1ULL << 35)
1211#define SCTLR_BT1 (1ULL << 36)
1212#define SCTLR_ITFSB (1ULL << 37)
1213#define SCTLR_TCF0 (3ULL << 38)
1214#define SCTLR_TCF (3ULL << 40)
1215#define SCTLR_ATA0 (1ULL << 42)
1216#define SCTLR_ATA (1ULL << 43)
1217#define SCTLR_DSSBS_64 (1ULL << 44)
1218
1219#define CPTR_TCPAC (1U << 31)
1220#define CPTR_TTA (1U << 20)
1221#define CPTR_TFP (1U << 10)
1222#define CPTR_TZ (1U << 8)
1223#define CPTR_EZ (1U << 8)
1224
1225#define MDCR_EPMAD (1U << 21)
1226#define MDCR_EDAD (1U << 20)
1227#define MDCR_SPME (1U << 17)
1228#define MDCR_HPMD (1U << 17)
1229#define MDCR_SDD (1U << 16)
1230#define MDCR_SPD (3U << 14)
1231#define MDCR_TDRA (1U << 11)
1232#define MDCR_TDOSA (1U << 10)
1233#define MDCR_TDA (1U << 9)
1234#define MDCR_TDE (1U << 8)
1235#define MDCR_HPME (1U << 7)
1236#define MDCR_TPM (1U << 6)
1237#define MDCR_TPMCR (1U << 5)
1238#define MDCR_HPMN (0x1fU)
1239
1240
1241#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1242
1243#define CPSR_M (0x1fU)
1244#define CPSR_T (1U << 5)
1245#define CPSR_F (1U << 6)
1246#define CPSR_I (1U << 7)
1247#define CPSR_A (1U << 8)
1248#define CPSR_E (1U << 9)
1249#define CPSR_IT_2_7 (0xfc00U)
1250#define CPSR_GE (0xfU << 16)
1251#define CPSR_IL (1U << 20)
1252#define CPSR_DIT (1U << 21)
1253#define CPSR_PAN (1U << 22)
1254#define CPSR_SSBS (1U << 23)
1255#define CPSR_J (1U << 24)
1256#define CPSR_IT_0_1 (3U << 25)
1257#define CPSR_Q (1U << 27)
1258#define CPSR_V (1U << 28)
1259#define CPSR_C (1U << 29)
1260#define CPSR_Z (1U << 30)
1261#define CPSR_N (1U << 31)
1262#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1263#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1264
1265#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1266#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1267 | CPSR_NZCV)
1268
1269#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1270
1271#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1272
1273
1274#define XPSR_EXCP 0x1ffU
1275#define XPSR_SPREALIGN (1U << 9)
1276#define XPSR_IT_2_7 CPSR_IT_2_7
1277#define XPSR_GE CPSR_GE
1278#define XPSR_SFPA (1U << 20)
1279#define XPSR_T (1U << 24)
1280#define XPSR_IT_0_1 CPSR_IT_0_1
1281#define XPSR_Q CPSR_Q
1282#define XPSR_V CPSR_V
1283#define XPSR_C CPSR_C
1284#define XPSR_Z CPSR_Z
1285#define XPSR_N CPSR_N
1286#define XPSR_NZCV CPSR_NZCV
1287#define XPSR_IT CPSR_IT
1288
1289#define TTBCR_N (7U << 0)
1290#define TTBCR_T0SZ (7U << 0)
1291#define TTBCR_PD0 (1U << 4)
1292#define TTBCR_PD1 (1U << 5)
1293#define TTBCR_EPD0 (1U << 7)
1294#define TTBCR_IRGN0 (3U << 8)
1295#define TTBCR_ORGN0 (3U << 10)
1296#define TTBCR_SH0 (3U << 12)
1297#define TTBCR_T1SZ (3U << 16)
1298#define TTBCR_A1 (1U << 22)
1299#define TTBCR_EPD1 (1U << 23)
1300#define TTBCR_IRGN1 (3U << 24)
1301#define TTBCR_ORGN1 (3U << 26)
1302#define TTBCR_SH1 (1U << 28)
1303#define TTBCR_EAE (1U << 31)
1304
1305
1306
1307
1308
1309#define PSTATE_SP (1U)
1310#define PSTATE_M (0xFU)
1311#define PSTATE_nRW (1U << 4)
1312#define PSTATE_F (1U << 6)
1313#define PSTATE_I (1U << 7)
1314#define PSTATE_A (1U << 8)
1315#define PSTATE_D (1U << 9)
1316#define PSTATE_BTYPE (3U << 10)
1317#define PSTATE_SSBS (1U << 12)
1318#define PSTATE_IL (1U << 20)
1319#define PSTATE_SS (1U << 21)
1320#define PSTATE_PAN (1U << 22)
1321#define PSTATE_UAO (1U << 23)
1322#define PSTATE_DIT (1U << 24)
1323#define PSTATE_TCO (1U << 25)
1324#define PSTATE_V (1U << 28)
1325#define PSTATE_C (1U << 29)
1326#define PSTATE_Z (1U << 30)
1327#define PSTATE_N (1U << 31)
1328#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1329#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1330#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1331
1332#define PSTATE_MODE_EL3h 13
1333#define PSTATE_MODE_EL3t 12
1334#define PSTATE_MODE_EL2h 9
1335#define PSTATE_MODE_EL2t 8
1336#define PSTATE_MODE_EL1h 5
1337#define PSTATE_MODE_EL1t 4
1338#define PSTATE_MODE_EL0t 0
1339
1340
1341
1342
1343void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1344
1345
1346static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1347{
1348 return (el << 2) | handler;
1349}
1350
1351
1352
1353
1354
1355static inline uint32_t pstate_read(CPUARMState *env)
1356{
1357 int ZF;
1358
1359 ZF = (env->ZF == 0);
1360 return (env->NF & 0x80000000) | (ZF << 30)
1361 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1362 | env->pstate | env->daif | (env->btype << 10);
1363}
1364
1365static inline void pstate_write(CPUARMState *env, uint32_t val)
1366{
1367 env->ZF = (~val) & PSTATE_Z;
1368 env->NF = val;
1369 env->CF = (val >> 29) & 1;
1370 env->VF = (val << 3) & 0x80000000;
1371 env->daif = val & PSTATE_DAIF;
1372 env->btype = (val >> 10) & 3;
1373 env->pstate = val & ~CACHED_PSTATE_BITS;
1374}
1375
1376
1377uint32_t cpsr_read(CPUARMState *env);
1378
1379typedef enum CPSRWriteType {
1380 CPSRWriteByInstr = 0,
1381 CPSRWriteExceptionReturn = 1,
1382 CPSRWriteRaw = 2,
1383 CPSRWriteByGDBStub = 3,
1384} CPSRWriteType;
1385
1386
1387void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1388 CPSRWriteType write_type);
1389
1390
1391static inline uint32_t xpsr_read(CPUARMState *env)
1392{
1393 int ZF;
1394 ZF = (env->ZF == 0);
1395 return (env->NF & 0x80000000) | (ZF << 30)
1396 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1397 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1398 | ((env->condexec_bits & 0xfc) << 8)
1399 | (env->GE << 16)
1400 | env->v7m.exception;
1401}
1402
1403
1404static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1405{
1406 if (mask & XPSR_NZCV) {
1407 env->ZF = (~val) & XPSR_Z;
1408 env->NF = val;
1409 env->CF = (val >> 29) & 1;
1410 env->VF = (val << 3) & 0x80000000;
1411 }
1412 if (mask & XPSR_Q) {
1413 env->QF = ((val & XPSR_Q) != 0);
1414 }
1415 if (mask & XPSR_GE) {
1416 env->GE = (val & XPSR_GE) >> 16;
1417 }
1418#ifndef CONFIG_USER_ONLY
1419 if (mask & XPSR_T) {
1420 env->thumb = ((val & XPSR_T) != 0);
1421 }
1422 if (mask & XPSR_IT_0_1) {
1423 env->condexec_bits &= ~3;
1424 env->condexec_bits |= (val >> 25) & 3;
1425 }
1426 if (mask & XPSR_IT_2_7) {
1427 env->condexec_bits &= 3;
1428 env->condexec_bits |= (val >> 8) & 0xfc;
1429 }
1430 if (mask & XPSR_EXCP) {
1431
1432 write_v7m_exception(env, val & XPSR_EXCP);
1433 }
1434#endif
1435}
1436
1437#define HCR_VM (1ULL << 0)
1438#define HCR_SWIO (1ULL << 1)
1439#define HCR_PTW (1ULL << 2)
1440#define HCR_FMO (1ULL << 3)
1441#define HCR_IMO (1ULL << 4)
1442#define HCR_AMO (1ULL << 5)
1443#define HCR_VF (1ULL << 6)
1444#define HCR_VI (1ULL << 7)
1445#define HCR_VSE (1ULL << 8)
1446#define HCR_FB (1ULL << 9)
1447#define HCR_BSU_MASK (3ULL << 10)
1448#define HCR_DC (1ULL << 12)
1449#define HCR_TWI (1ULL << 13)
1450#define HCR_TWE (1ULL << 14)
1451#define HCR_TID0 (1ULL << 15)
1452#define HCR_TID1 (1ULL << 16)
1453#define HCR_TID2 (1ULL << 17)
1454#define HCR_TID3 (1ULL << 18)
1455#define HCR_TSC (1ULL << 19)
1456#define HCR_TIDCP (1ULL << 20)
1457#define HCR_TACR (1ULL << 21)
1458#define HCR_TSW (1ULL << 22)
1459#define HCR_TPCP (1ULL << 23)
1460#define HCR_TPU (1ULL << 24)
1461#define HCR_TTLB (1ULL << 25)
1462#define HCR_TVM (1ULL << 26)
1463#define HCR_TGE (1ULL << 27)
1464#define HCR_TDZ (1ULL << 28)
1465#define HCR_HCD (1ULL << 29)
1466#define HCR_TRVM (1ULL << 30)
1467#define HCR_RW (1ULL << 31)
1468#define HCR_CD (1ULL << 32)
1469#define HCR_ID (1ULL << 33)
1470#define HCR_E2H (1ULL << 34)
1471#define HCR_TLOR (1ULL << 35)
1472#define HCR_TERR (1ULL << 36)
1473#define HCR_TEA (1ULL << 37)
1474#define HCR_MIOCNCE (1ULL << 38)
1475
1476#define HCR_APK (1ULL << 40)
1477#define HCR_API (1ULL << 41)
1478#define HCR_NV (1ULL << 42)
1479#define HCR_NV1 (1ULL << 43)
1480#define HCR_AT (1ULL << 44)
1481#define HCR_NV2 (1ULL << 45)
1482#define HCR_FWB (1ULL << 46)
1483#define HCR_FIEN (1ULL << 47)
1484
1485#define HCR_TID4 (1ULL << 49)
1486#define HCR_TICAB (1ULL << 50)
1487#define HCR_AMVOFFEN (1ULL << 51)
1488#define HCR_TOCU (1ULL << 52)
1489#define HCR_ENSCXT (1ULL << 53)
1490#define HCR_TTLBIS (1ULL << 54)
1491#define HCR_TTLBOS (1ULL << 55)
1492#define HCR_ATA (1ULL << 56)
1493#define HCR_DCT (1ULL << 57)
1494#define HCR_TID5 (1ULL << 58)
1495#define HCR_TWEDEN (1ULL << 59)
1496#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1497
1498#define HPFAR_NS (1ULL << 63)
1499
1500#define SCR_NS (1U << 0)
1501#define SCR_IRQ (1U << 1)
1502#define SCR_FIQ (1U << 2)
1503#define SCR_EA (1U << 3)
1504#define SCR_FW (1U << 4)
1505#define SCR_AW (1U << 5)
1506#define SCR_NET (1U << 6)
1507#define SCR_SMD (1U << 7)
1508#define SCR_HCE (1U << 8)
1509#define SCR_SIF (1U << 9)
1510#define SCR_RW (1U << 10)
1511#define SCR_ST (1U << 11)
1512#define SCR_TWI (1U << 12)
1513#define SCR_TWE (1U << 13)
1514#define SCR_TLOR (1U << 14)
1515#define SCR_TERR (1U << 15)
1516#define SCR_APK (1U << 16)
1517#define SCR_API (1U << 17)
1518#define SCR_EEL2 (1U << 18)
1519#define SCR_EASE (1U << 19)
1520#define SCR_NMEA (1U << 20)
1521#define SCR_FIEN (1U << 21)
1522#define SCR_ENSCXT (1U << 25)
1523#define SCR_ATA (1U << 26)
1524
1525
1526uint32_t vfp_get_fpscr(CPUARMState *env);
1527void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1528
1529
1530
1531
1532
1533
1534
1535
1536#define FPSR_MASK 0xf800009f
1537#define FPCR_MASK 0x07ff9f00
1538
1539#define FPCR_IOE (1 << 8)
1540#define FPCR_DZE (1 << 9)
1541#define FPCR_OFE (1 << 10)
1542#define FPCR_UFE (1 << 11)
1543#define FPCR_IXE (1 << 12)
1544#define FPCR_IDE (1 << 15)
1545#define FPCR_FZ16 (1 << 19)
1546#define FPCR_RMODE_MASK (3 << 22)
1547#define FPCR_FZ (1 << 24)
1548#define FPCR_DN (1 << 25)
1549#define FPCR_AHP (1 << 26)
1550#define FPCR_QC (1 << 27)
1551#define FPCR_V (1 << 28)
1552#define FPCR_C (1 << 29)
1553#define FPCR_Z (1 << 30)
1554#define FPCR_N (1 << 31)
1555
1556#define FPCR_LTPSIZE_SHIFT 16
1557#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1558
1559#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1560#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1561
1562static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1563{
1564 return vfp_get_fpscr(env) & FPSR_MASK;
1565}
1566
1567static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1568{
1569 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1570 vfp_set_fpscr(env, new_fpscr);
1571}
1572
1573static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1574{
1575 return vfp_get_fpscr(env) & FPCR_MASK;
1576}
1577
1578static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1579{
1580 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1581 vfp_set_fpscr(env, new_fpscr);
1582}
1583
1584enum arm_cpu_mode {
1585 ARM_CPU_MODE_USR = 0x10,
1586 ARM_CPU_MODE_FIQ = 0x11,
1587 ARM_CPU_MODE_IRQ = 0x12,
1588 ARM_CPU_MODE_SVC = 0x13,
1589 ARM_CPU_MODE_MON = 0x16,
1590 ARM_CPU_MODE_ABT = 0x17,
1591 ARM_CPU_MODE_HYP = 0x1a,
1592 ARM_CPU_MODE_UND = 0x1b,
1593 ARM_CPU_MODE_SYS = 0x1f
1594};
1595
1596
1597#define ARM_VFP_FPSID 0
1598#define ARM_VFP_FPSCR 1
1599#define ARM_VFP_MVFR2 5
1600#define ARM_VFP_MVFR1 6
1601#define ARM_VFP_MVFR0 7
1602#define ARM_VFP_FPEXC 8
1603#define ARM_VFP_FPINST 9
1604#define ARM_VFP_FPINST2 10
1605
1606#define ARM_VFP_FPSCR_NZCVQC 2
1607#define ARM_VFP_VPR 12
1608#define ARM_VFP_P0 13
1609#define ARM_VFP_FPCXT_NS 14
1610#define ARM_VFP_FPCXT_S 15
1611
1612
1613#define QEMU_VFP_FPSCR_NZCV 0xffff
1614
1615
1616#define ARM_IWMMXT_wCID 0
1617#define ARM_IWMMXT_wCon 1
1618#define ARM_IWMMXT_wCSSF 2
1619#define ARM_IWMMXT_wCASF 3
1620#define ARM_IWMMXT_wCGR0 8
1621#define ARM_IWMMXT_wCGR1 9
1622#define ARM_IWMMXT_wCGR2 10
1623#define ARM_IWMMXT_wCGR3 11
1624
1625
1626FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1627FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1628FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1629FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1630FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1631FIELD(V7M_CCR, STKALIGN, 9, 1)
1632FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1633FIELD(V7M_CCR, DC, 16, 1)
1634FIELD(V7M_CCR, IC, 17, 1)
1635FIELD(V7M_CCR, BP, 18, 1)
1636FIELD(V7M_CCR, LOB, 19, 1)
1637FIELD(V7M_CCR, TRD, 20, 1)
1638
1639
1640FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1641FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1642FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1643FIELD(V7M_SCR, SEVONPEND, 4, 1)
1644
1645
1646FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1647FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1648FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1649FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1650FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1651FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1652FIELD(V7M_AIRCR, PRIS, 14, 1)
1653FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1654FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1655
1656
1657FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1658FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1659FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1660FIELD(V7M_CFSR, MSTKERR, 4, 1)
1661FIELD(V7M_CFSR, MLSPERR, 5, 1)
1662FIELD(V7M_CFSR, MMARVALID, 7, 1)
1663
1664
1665FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1666FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1667FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1668FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1669FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1670FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1671FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1672
1673
1674FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1675FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1676FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1677FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1678FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1679FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1680FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1681
1682
1683FIELD(V7M_CFSR, MMFSR, 0, 8)
1684FIELD(V7M_CFSR, BFSR, 8, 8)
1685FIELD(V7M_CFSR, UFSR, 16, 16)
1686
1687
1688FIELD(V7M_HFSR, VECTTBL, 1, 1)
1689FIELD(V7M_HFSR, FORCED, 30, 1)
1690FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1691
1692
1693FIELD(V7M_DFSR, HALTED, 0, 1)
1694FIELD(V7M_DFSR, BKPT, 1, 1)
1695FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1696FIELD(V7M_DFSR, VCATCH, 3, 1)
1697FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1698
1699
1700FIELD(V7M_SFSR, INVEP, 0, 1)
1701FIELD(V7M_SFSR, INVIS, 1, 1)
1702FIELD(V7M_SFSR, INVER, 2, 1)
1703FIELD(V7M_SFSR, AUVIOL, 3, 1)
1704FIELD(V7M_SFSR, INVTRAN, 4, 1)
1705FIELD(V7M_SFSR, LSPERR, 5, 1)
1706FIELD(V7M_SFSR, SFARVALID, 6, 1)
1707FIELD(V7M_SFSR, LSERR, 7, 1)
1708
1709
1710FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1711FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1712FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1713
1714
1715FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1716FIELD(V7M_CLIDR, LOUIS, 21, 3)
1717FIELD(V7M_CLIDR, LOC, 24, 3)
1718FIELD(V7M_CLIDR, LOUU, 27, 3)
1719FIELD(V7M_CLIDR, ICB, 30, 2)
1720
1721FIELD(V7M_CSSELR, IND, 0, 1)
1722FIELD(V7M_CSSELR, LEVEL, 1, 3)
1723
1724
1725
1726
1727FIELD(V7M_CSSELR, INDEX, 0, 4)
1728
1729
1730FIELD(V7M_FPCCR, LSPACT, 0, 1)
1731FIELD(V7M_FPCCR, USER, 1, 1)
1732FIELD(V7M_FPCCR, S, 2, 1)
1733FIELD(V7M_FPCCR, THREAD, 3, 1)
1734FIELD(V7M_FPCCR, HFRDY, 4, 1)
1735FIELD(V7M_FPCCR, MMRDY, 5, 1)
1736FIELD(V7M_FPCCR, BFRDY, 6, 1)
1737FIELD(V7M_FPCCR, SFRDY, 7, 1)
1738FIELD(V7M_FPCCR, MONRDY, 8, 1)
1739FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1740FIELD(V7M_FPCCR, UFRDY, 10, 1)
1741FIELD(V7M_FPCCR, RES0, 11, 15)
1742FIELD(V7M_FPCCR, TS, 26, 1)
1743FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1744FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1745FIELD(V7M_FPCCR, LSPENS, 29, 1)
1746FIELD(V7M_FPCCR, LSPEN, 30, 1)
1747FIELD(V7M_FPCCR, ASPEN, 31, 1)
1748
1749#define R_V7M_FPCCR_BANKED_MASK \
1750 (R_V7M_FPCCR_LSPACT_MASK | \
1751 R_V7M_FPCCR_USER_MASK | \
1752 R_V7M_FPCCR_THREAD_MASK | \
1753 R_V7M_FPCCR_MMRDY_MASK | \
1754 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1755 R_V7M_FPCCR_UFRDY_MASK | \
1756 R_V7M_FPCCR_ASPEN_MASK)
1757
1758
1759
1760
1761FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1762FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1763FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1764FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1765FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1766FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1767FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1768FIELD(CLIDR_EL1, LOUIS, 21, 3)
1769FIELD(CLIDR_EL1, LOC, 24, 3)
1770FIELD(CLIDR_EL1, LOUU, 27, 3)
1771FIELD(CLIDR_EL1, ICB, 30, 3)
1772
1773
1774FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
1775FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
1776FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
1777
1778
1779FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
1780FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
1781FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
1782
1783FIELD(CTR_EL0, IMINLINE, 0, 4)
1784FIELD(CTR_EL0, L1IP, 14, 2)
1785FIELD(CTR_EL0, DMINLINE, 16, 4)
1786FIELD(CTR_EL0, ERG, 20, 4)
1787FIELD(CTR_EL0, CWG, 24, 4)
1788FIELD(CTR_EL0, IDC, 28, 1)
1789FIELD(CTR_EL0, DIC, 29, 1)
1790FIELD(CTR_EL0, TMINLINE, 32, 6)
1791
1792FIELD(MIDR_EL1, REVISION, 0, 4)
1793FIELD(MIDR_EL1, PARTNUM, 4, 12)
1794FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1795FIELD(MIDR_EL1, VARIANT, 20, 4)
1796FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1797
1798FIELD(ID_ISAR0, SWAP, 0, 4)
1799FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1800FIELD(ID_ISAR0, BITFIELD, 8, 4)
1801FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1802FIELD(ID_ISAR0, COPROC, 16, 4)
1803FIELD(ID_ISAR0, DEBUG, 20, 4)
1804FIELD(ID_ISAR0, DIVIDE, 24, 4)
1805
1806FIELD(ID_ISAR1, ENDIAN, 0, 4)
1807FIELD(ID_ISAR1, EXCEPT, 4, 4)
1808FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1809FIELD(ID_ISAR1, EXTEND, 12, 4)
1810FIELD(ID_ISAR1, IFTHEN, 16, 4)
1811FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1812FIELD(ID_ISAR1, INTERWORK, 24, 4)
1813FIELD(ID_ISAR1, JAZELLE, 28, 4)
1814
1815FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1816FIELD(ID_ISAR2, MEMHINT, 4, 4)
1817FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1818FIELD(ID_ISAR2, MULT, 12, 4)
1819FIELD(ID_ISAR2, MULTS, 16, 4)
1820FIELD(ID_ISAR2, MULTU, 20, 4)
1821FIELD(ID_ISAR2, PSR_AR, 24, 4)
1822FIELD(ID_ISAR2, REVERSAL, 28, 4)
1823
1824FIELD(ID_ISAR3, SATURATE, 0, 4)
1825FIELD(ID_ISAR3, SIMD, 4, 4)
1826FIELD(ID_ISAR3, SVC, 8, 4)
1827FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1828FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1829FIELD(ID_ISAR3, T32COPY, 20, 4)
1830FIELD(ID_ISAR3, TRUENOP, 24, 4)
1831FIELD(ID_ISAR3, T32EE, 28, 4)
1832
1833FIELD(ID_ISAR4, UNPRIV, 0, 4)
1834FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1835FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1836FIELD(ID_ISAR4, SMC, 12, 4)
1837FIELD(ID_ISAR4, BARRIER, 16, 4)
1838FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1839FIELD(ID_ISAR4, PSR_M, 24, 4)
1840FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1841
1842FIELD(ID_ISAR5, SEVL, 0, 4)
1843FIELD(ID_ISAR5, AES, 4, 4)
1844FIELD(ID_ISAR5, SHA1, 8, 4)
1845FIELD(ID_ISAR5, SHA2, 12, 4)
1846FIELD(ID_ISAR5, CRC32, 16, 4)
1847FIELD(ID_ISAR5, RDM, 24, 4)
1848FIELD(ID_ISAR5, VCMA, 28, 4)
1849
1850FIELD(ID_ISAR6, JSCVT, 0, 4)
1851FIELD(ID_ISAR6, DP, 4, 4)
1852FIELD(ID_ISAR6, FHM, 8, 4)
1853FIELD(ID_ISAR6, SB, 12, 4)
1854FIELD(ID_ISAR6, SPECRES, 16, 4)
1855FIELD(ID_ISAR6, BF16, 20, 4)
1856FIELD(ID_ISAR6, I8MM, 24, 4)
1857
1858FIELD(ID_MMFR0, VMSA, 0, 4)
1859FIELD(ID_MMFR0, PMSA, 4, 4)
1860FIELD(ID_MMFR0, OUTERSHR, 8, 4)
1861FIELD(ID_MMFR0, SHARELVL, 12, 4)
1862FIELD(ID_MMFR0, TCM, 16, 4)
1863FIELD(ID_MMFR0, AUXREG, 20, 4)
1864FIELD(ID_MMFR0, FCSE, 24, 4)
1865FIELD(ID_MMFR0, INNERSHR, 28, 4)
1866
1867FIELD(ID_MMFR1, L1HVDVA, 0, 4)
1868FIELD(ID_MMFR1, L1UNIVA, 4, 4)
1869FIELD(ID_MMFR1, L1HVDSW, 8, 4)
1870FIELD(ID_MMFR1, L1UNISW, 12, 4)
1871FIELD(ID_MMFR1, L1HVD, 16, 4)
1872FIELD(ID_MMFR1, L1UNI, 20, 4)
1873FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
1874FIELD(ID_MMFR1, BPRED, 28, 4)
1875
1876FIELD(ID_MMFR2, L1HVDFG, 0, 4)
1877FIELD(ID_MMFR2, L1HVDBG, 4, 4)
1878FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
1879FIELD(ID_MMFR2, HVDTLB, 12, 4)
1880FIELD(ID_MMFR2, UNITLB, 16, 4)
1881FIELD(ID_MMFR2, MEMBARR, 20, 4)
1882FIELD(ID_MMFR2, WFISTALL, 24, 4)
1883FIELD(ID_MMFR2, HWACCFLG, 28, 4)
1884
1885FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1886FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1887FIELD(ID_MMFR3, BPMAINT, 8, 4)
1888FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1889FIELD(ID_MMFR3, PAN, 16, 4)
1890FIELD(ID_MMFR3, COHWALK, 20, 4)
1891FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1892FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1893
1894FIELD(ID_MMFR4, SPECSEI, 0, 4)
1895FIELD(ID_MMFR4, AC2, 4, 4)
1896FIELD(ID_MMFR4, XNX, 8, 4)
1897FIELD(ID_MMFR4, CNP, 12, 4)
1898FIELD(ID_MMFR4, HPDS, 16, 4)
1899FIELD(ID_MMFR4, LSM, 20, 4)
1900FIELD(ID_MMFR4, CCIDX, 24, 4)
1901FIELD(ID_MMFR4, EVT, 28, 4)
1902
1903FIELD(ID_MMFR5, ETS, 0, 4)
1904
1905FIELD(ID_PFR0, STATE0, 0, 4)
1906FIELD(ID_PFR0, STATE1, 4, 4)
1907FIELD(ID_PFR0, STATE2, 8, 4)
1908FIELD(ID_PFR0, STATE3, 12, 4)
1909FIELD(ID_PFR0, CSV2, 16, 4)
1910FIELD(ID_PFR0, AMU, 20, 4)
1911FIELD(ID_PFR0, DIT, 24, 4)
1912FIELD(ID_PFR0, RAS, 28, 4)
1913
1914FIELD(ID_PFR1, PROGMOD, 0, 4)
1915FIELD(ID_PFR1, SECURITY, 4, 4)
1916FIELD(ID_PFR1, MPROGMOD, 8, 4)
1917FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
1918FIELD(ID_PFR1, GENTIMER, 16, 4)
1919FIELD(ID_PFR1, SEC_FRAC, 20, 4)
1920FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
1921FIELD(ID_PFR1, GIC, 28, 4)
1922
1923FIELD(ID_PFR2, CSV3, 0, 4)
1924FIELD(ID_PFR2, SSBS, 4, 4)
1925FIELD(ID_PFR2, RAS_FRAC, 8, 4)
1926
1927FIELD(ID_AA64ISAR0, AES, 4, 4)
1928FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1929FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1930FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1931FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1932FIELD(ID_AA64ISAR0, RDM, 28, 4)
1933FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1934FIELD(ID_AA64ISAR0, SM3, 36, 4)
1935FIELD(ID_AA64ISAR0, SM4, 40, 4)
1936FIELD(ID_AA64ISAR0, DP, 44, 4)
1937FIELD(ID_AA64ISAR0, FHM, 48, 4)
1938FIELD(ID_AA64ISAR0, TS, 52, 4)
1939FIELD(ID_AA64ISAR0, TLB, 56, 4)
1940FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1941
1942FIELD(ID_AA64ISAR1, DPB, 0, 4)
1943FIELD(ID_AA64ISAR1, APA, 4, 4)
1944FIELD(ID_AA64ISAR1, API, 8, 4)
1945FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1946FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1947FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1948FIELD(ID_AA64ISAR1, GPA, 24, 4)
1949FIELD(ID_AA64ISAR1, GPI, 28, 4)
1950FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1951FIELD(ID_AA64ISAR1, SB, 36, 4)
1952FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1953FIELD(ID_AA64ISAR1, BF16, 44, 4)
1954FIELD(ID_AA64ISAR1, DGH, 48, 4)
1955FIELD(ID_AA64ISAR1, I8MM, 52, 4)
1956
1957FIELD(ID_AA64PFR0, EL0, 0, 4)
1958FIELD(ID_AA64PFR0, EL1, 4, 4)
1959FIELD(ID_AA64PFR0, EL2, 8, 4)
1960FIELD(ID_AA64PFR0, EL3, 12, 4)
1961FIELD(ID_AA64PFR0, FP, 16, 4)
1962FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1963FIELD(ID_AA64PFR0, GIC, 24, 4)
1964FIELD(ID_AA64PFR0, RAS, 28, 4)
1965FIELD(ID_AA64PFR0, SVE, 32, 4)
1966FIELD(ID_AA64PFR0, SEL2, 36, 4)
1967FIELD(ID_AA64PFR0, MPAM, 40, 4)
1968FIELD(ID_AA64PFR0, AMU, 44, 4)
1969FIELD(ID_AA64PFR0, DIT, 48, 4)
1970FIELD(ID_AA64PFR0, CSV2, 56, 4)
1971FIELD(ID_AA64PFR0, CSV3, 60, 4)
1972
1973FIELD(ID_AA64PFR1, BT, 0, 4)
1974FIELD(ID_AA64PFR1, SSBS, 4, 4)
1975FIELD(ID_AA64PFR1, MTE, 8, 4)
1976FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1977FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
1978
1979FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
1980FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
1981FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
1982FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
1983FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
1984FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
1985FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
1986FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
1987FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
1988FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
1989FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
1990FIELD(ID_AA64MMFR0, EXS, 44, 4)
1991FIELD(ID_AA64MMFR0, FGT, 56, 4)
1992FIELD(ID_AA64MMFR0, ECV, 60, 4)
1993
1994FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
1995FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
1996FIELD(ID_AA64MMFR1, VH, 8, 4)
1997FIELD(ID_AA64MMFR1, HPDS, 12, 4)
1998FIELD(ID_AA64MMFR1, LO, 16, 4)
1999FIELD(ID_AA64MMFR1, PAN, 20, 4)
2000FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2001FIELD(ID_AA64MMFR1, XNX, 28, 4)
2002FIELD(ID_AA64MMFR1, TWED, 32, 4)
2003FIELD(ID_AA64MMFR1, ETS, 36, 4)
2004
2005FIELD(ID_AA64MMFR2, CNP, 0, 4)
2006FIELD(ID_AA64MMFR2, UAO, 4, 4)
2007FIELD(ID_AA64MMFR2, LSM, 8, 4)
2008FIELD(ID_AA64MMFR2, IESB, 12, 4)
2009FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2010FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2011FIELD(ID_AA64MMFR2, NV, 24, 4)
2012FIELD(ID_AA64MMFR2, ST, 28, 4)
2013FIELD(ID_AA64MMFR2, AT, 32, 4)
2014FIELD(ID_AA64MMFR2, IDS, 36, 4)
2015FIELD(ID_AA64MMFR2, FWB, 40, 4)
2016FIELD(ID_AA64MMFR2, TTL, 48, 4)
2017FIELD(ID_AA64MMFR2, BBM, 52, 4)
2018FIELD(ID_AA64MMFR2, EVT, 56, 4)
2019FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2020
2021FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2022FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2023FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2024FIELD(ID_AA64DFR0, BRPS, 12, 4)
2025FIELD(ID_AA64DFR0, WRPS, 20, 4)
2026FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2027FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2028FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2029FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2030FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2031
2032FIELD(ID_DFR0, COPDBG, 0, 4)
2033FIELD(ID_DFR0, COPSDBG, 4, 4)
2034FIELD(ID_DFR0, MMAPDBG, 8, 4)
2035FIELD(ID_DFR0, COPTRC, 12, 4)
2036FIELD(ID_DFR0, MMAPTRC, 16, 4)
2037FIELD(ID_DFR0, MPROFDBG, 20, 4)
2038FIELD(ID_DFR0, PERFMON, 24, 4)
2039FIELD(ID_DFR0, TRACEFILT, 28, 4)
2040
2041FIELD(ID_DFR1, MTPMU, 0, 4)
2042
2043FIELD(DBGDIDR, SE_IMP, 12, 1)
2044FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2045FIELD(DBGDIDR, VERSION, 16, 4)
2046FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2047FIELD(DBGDIDR, BRPS, 24, 4)
2048FIELD(DBGDIDR, WRPS, 28, 4)
2049
2050FIELD(MVFR0, SIMDREG, 0, 4)
2051FIELD(MVFR0, FPSP, 4, 4)
2052FIELD(MVFR0, FPDP, 8, 4)
2053FIELD(MVFR0, FPTRAP, 12, 4)
2054FIELD(MVFR0, FPDIVIDE, 16, 4)
2055FIELD(MVFR0, FPSQRT, 20, 4)
2056FIELD(MVFR0, FPSHVEC, 24, 4)
2057FIELD(MVFR0, FPROUND, 28, 4)
2058
2059FIELD(MVFR1, FPFTZ, 0, 4)
2060FIELD(MVFR1, FPDNAN, 4, 4)
2061FIELD(MVFR1, SIMDLS, 8, 4)
2062FIELD(MVFR1, SIMDINT, 12, 4)
2063FIELD(MVFR1, SIMDSP, 16, 4)
2064FIELD(MVFR1, SIMDHP, 20, 4)
2065FIELD(MVFR1, MVE, 8, 4)
2066FIELD(MVFR1, FP16, 20, 4)
2067FIELD(MVFR1, FPHP, 24, 4)
2068FIELD(MVFR1, SIMDFMAC, 28, 4)
2069
2070FIELD(MVFR2, SIMDMISC, 0, 4)
2071FIELD(MVFR2, FPMISC, 4, 4)
2072
2073QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2074
2075
2076
2077
2078
2079enum arm_features {
2080 ARM_FEATURE_AUXCR,
2081 ARM_FEATURE_XSCALE,
2082 ARM_FEATURE_IWMMXT,
2083 ARM_FEATURE_V6,
2084 ARM_FEATURE_V6K,
2085 ARM_FEATURE_V7,
2086 ARM_FEATURE_THUMB2,
2087 ARM_FEATURE_PMSA,
2088 ARM_FEATURE_NEON,
2089 ARM_FEATURE_M,
2090 ARM_FEATURE_OMAPCP,
2091 ARM_FEATURE_THUMB2EE,
2092 ARM_FEATURE_V7MP,
2093 ARM_FEATURE_V7VE,
2094 ARM_FEATURE_V4T,
2095 ARM_FEATURE_V5,
2096 ARM_FEATURE_STRONGARM,
2097 ARM_FEATURE_VAPA,
2098 ARM_FEATURE_GENERIC_TIMER,
2099 ARM_FEATURE_MVFR,
2100 ARM_FEATURE_DUMMY_C15_REGS,
2101 ARM_FEATURE_CACHE_TEST_CLEAN,
2102 ARM_FEATURE_CACHE_DIRTY_REG,
2103 ARM_FEATURE_CACHE_BLOCK_OPS,
2104 ARM_FEATURE_MPIDR,
2105 ARM_FEATURE_LPAE,
2106 ARM_FEATURE_V8,
2107 ARM_FEATURE_AARCH64,
2108 ARM_FEATURE_CBAR,
2109 ARM_FEATURE_CBAR_RO,
2110 ARM_FEATURE_EL2,
2111 ARM_FEATURE_EL3,
2112 ARM_FEATURE_THUMB_DSP,
2113 ARM_FEATURE_PMU,
2114 ARM_FEATURE_VBAR,
2115 ARM_FEATURE_M_SECURITY,
2116 ARM_FEATURE_M_MAIN,
2117 ARM_FEATURE_V8_1M,
2118};
2119
2120static inline int arm_feature(CPUARMState *env, int feature)
2121{
2122 return (env->features & (1ULL << feature)) != 0;
2123}
2124
2125void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2126
2127#if !defined(CONFIG_USER_ONLY)
2128
2129
2130
2131
2132
2133
2134static inline bool arm_is_secure_below_el3(CPUARMState *env)
2135{
2136 if (arm_feature(env, ARM_FEATURE_EL3)) {
2137 return !(env->cp15.scr_el3 & SCR_NS);
2138 } else {
2139
2140
2141
2142 return false;
2143 }
2144}
2145
2146
2147static inline bool arm_is_el3_or_mon(CPUARMState *env)
2148{
2149 if (arm_feature(env, ARM_FEATURE_EL3)) {
2150 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2151
2152 return true;
2153 } else if (!is_a64(env) &&
2154 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2155
2156 return true;
2157 }
2158 }
2159 return false;
2160}
2161
2162
2163static inline bool arm_is_secure(CPUARMState *env)
2164{
2165 if (arm_is_el3_or_mon(env)) {
2166 return true;
2167 }
2168 return arm_is_secure_below_el3(env);
2169}
2170
2171
2172
2173
2174
2175static inline bool arm_is_el2_enabled(CPUARMState *env)
2176{
2177 if (arm_feature(env, ARM_FEATURE_EL2)) {
2178 if (arm_is_secure_below_el3(env)) {
2179 return (env->cp15.scr_el3 & SCR_EEL2) != 0;
2180 }
2181 return true;
2182 }
2183 return false;
2184}
2185
2186#else
2187static inline bool arm_is_secure_below_el3(CPUARMState *env)
2188{
2189 return false;
2190}
2191
2192static inline bool arm_is_secure(CPUARMState *env)
2193{
2194 return false;
2195}
2196
2197static inline bool arm_is_el2_enabled(CPUARMState *env)
2198{
2199 return false;
2200}
2201#endif
2202
2203
2204
2205
2206
2207
2208
2209uint64_t arm_hcr_el2_eff(CPUARMState *env);
2210
2211
2212static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2213{
2214
2215
2216
2217 assert(el >= 1 && el <= 3);
2218 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2219
2220
2221
2222
2223
2224 if (el == 3) {
2225 return aa64;
2226 }
2227
2228 if (arm_feature(env, ARM_FEATURE_EL3) &&
2229 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
2230 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2231 }
2232
2233 if (el == 2) {
2234 return aa64;
2235 }
2236
2237 if (arm_is_el2_enabled(env)) {
2238 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2239 }
2240
2241 return aa64;
2242}
2243
2244
2245
2246
2247
2248
2249
2250
2251static inline bool access_secure_reg(CPUARMState *env)
2252{
2253 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2254 !arm_el_is_aa64(env, 3) &&
2255 !(env->cp15.scr_el3 & SCR_NS));
2256
2257 return ret;
2258}
2259
2260
2261#define A32_BANKED_REG_GET(_env, _regname, _secure) \
2262 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2263
2264#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2265 do { \
2266 if (_secure) { \
2267 (_env)->cp15._regname##_s = (_val); \
2268 } else { \
2269 (_env)->cp15._regname##_ns = (_val); \
2270 } \
2271 } while (0)
2272
2273
2274
2275
2276
2277
2278#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2279 A32_BANKED_REG_GET((_env), _regname, \
2280 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2281
2282#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2283 A32_BANKED_REG_SET((_env), _regname, \
2284 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2285 (_val))
2286
2287void arm_cpu_list(void);
2288uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2289 uint32_t cur_el, bool secure);
2290
2291
2292#ifndef CONFIG_USER_ONLY
2293bool armv7m_nvic_can_take_pending_exception(void *opaque);
2294#else
2295static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2296{
2297 return true;
2298}
2299#endif
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2352 bool *ptargets_secure);
2353
2354
2355
2356
2357
2358
2359
2360
2361void armv7m_nvic_acknowledge_irq(void *opaque);
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397int armv7m_nvic_raw_execution_priority(void *opaque);
2398
2399
2400
2401
2402
2403
2404
2405#ifndef CONFIG_USER_ONLY
2406bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2407#else
2408static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2409{
2410 return false;
2411}
2412#endif
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440#define CP_REG_AA64_SHIFT 28
2441#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2442
2443
2444
2445
2446
2447#define CP_REG_NS_SHIFT 29
2448#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2449
2450#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2451 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2452 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2453
2454#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2455 (CP_REG_AA64_MASK | \
2456 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2457 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2458 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2459 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2460 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2461 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2462
2463
2464
2465
2466static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2467{
2468 uint32_t cpregid = kvmid;
2469 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2470 cpregid |= CP_REG_AA64_MASK;
2471 } else {
2472 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2473 cpregid |= (1 << 15);
2474 }
2475
2476
2477
2478
2479 cpregid |= 1 << CP_REG_NS_SHIFT;
2480 }
2481 return cpregid;
2482}
2483
2484
2485
2486
2487static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2488{
2489 uint64_t kvmid;
2490
2491 if (cpregid & CP_REG_AA64_MASK) {
2492 kvmid = cpregid & ~CP_REG_AA64_MASK;
2493 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2494 } else {
2495 kvmid = cpregid & ~(1 << 15);
2496 if (cpregid & (1 << 15)) {
2497 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2498 } else {
2499 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2500 }
2501 }
2502 return kvmid;
2503}
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533#define ARM_CP_SPECIAL 0x0001
2534#define ARM_CP_CONST 0x0002
2535#define ARM_CP_64BIT 0x0004
2536#define ARM_CP_SUPPRESS_TB_END 0x0008
2537#define ARM_CP_OVERRIDE 0x0010
2538#define ARM_CP_ALIAS 0x0020
2539#define ARM_CP_IO 0x0040
2540#define ARM_CP_NO_RAW 0x0080
2541#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2542#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2543#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2544#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2545#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2546#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600)
2547#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700)
2548#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA
2549#define ARM_CP_FPU 0x1000
2550#define ARM_CP_SVE 0x2000
2551#define ARM_CP_NO_GDB 0x4000
2552#define ARM_CP_RAISES_EXC 0x8000
2553#define ARM_CP_NEWEL 0x10000
2554
2555#define ARM_CP_SENTINEL 0xfffff
2556
2557#define ARM_CP_FLAG_MASK 0x1f0ff
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568enum {
2569 ARM_CP_STATE_AA32 = 0,
2570 ARM_CP_STATE_AA64 = 1,
2571 ARM_CP_STATE_BOTH = 2,
2572};
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584enum {
2585 ARM_CP_SECSTATE_S = (1 << 0),
2586 ARM_CP_SECSTATE_NS = (1 << 1),
2587};
2588
2589
2590
2591
2592
2593static inline bool cptype_valid(int cptype)
2594{
2595 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2596 || ((cptype & ARM_CP_SPECIAL) &&
2597 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2598}
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617#define PL3_R 0x80
2618#define PL3_W 0x40
2619#define PL2_R (0x20 | PL3_R)
2620#define PL2_W (0x10 | PL3_W)
2621#define PL1_R (0x08 | PL2_R)
2622#define PL1_W (0x04 | PL2_W)
2623#define PL0_R (0x02 | PL1_R)
2624#define PL0_W (0x01 | PL1_W)
2625
2626
2627
2628
2629
2630
2631
2632#ifdef CONFIG_USER_ONLY
2633#define PL0U_R PL0_R
2634#else
2635#define PL0U_R PL1_R
2636#endif
2637
2638#define PL3_RW (PL3_R | PL3_W)
2639#define PL2_RW (PL2_R | PL2_W)
2640#define PL1_RW (PL1_R | PL1_W)
2641#define PL0_RW (PL0_R | PL0_W)
2642
2643
2644static inline int arm_highest_el(CPUARMState *env)
2645{
2646 if (arm_feature(env, ARM_FEATURE_EL3)) {
2647 return 3;
2648 }
2649 if (arm_feature(env, ARM_FEATURE_EL2)) {
2650 return 2;
2651 }
2652 return 1;
2653}
2654
2655
2656static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2657{
2658 return env->v7m.exception != 0;
2659}
2660
2661
2662
2663
2664static inline int arm_current_el(CPUARMState *env)
2665{
2666 if (arm_feature(env, ARM_FEATURE_M)) {
2667 return arm_v7m_is_handler_mode(env) ||
2668 !(env->v7m.control[env->v7m.secure] & 1);
2669 }
2670
2671 if (is_a64(env)) {
2672 return extract32(env->pstate, 2, 2);
2673 }
2674
2675 switch (env->uncached_cpsr & 0x1f) {
2676 case ARM_CPU_MODE_USR:
2677 return 0;
2678 case ARM_CPU_MODE_HYP:
2679 return 2;
2680 case ARM_CPU_MODE_MON:
2681 return 3;
2682 default:
2683 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2684
2685
2686
2687 return 3;
2688 }
2689
2690 return 1;
2691 }
2692}
2693
2694typedef struct ARMCPRegInfo ARMCPRegInfo;
2695
2696typedef enum CPAccessResult {
2697
2698 CP_ACCESS_OK = 0,
2699
2700
2701
2702
2703
2704
2705 CP_ACCESS_TRAP = 1,
2706
2707
2708
2709
2710 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2711
2712 CP_ACCESS_TRAP_EL2 = 3,
2713 CP_ACCESS_TRAP_EL3 = 4,
2714
2715 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2716 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2717
2718
2719
2720 CP_ACCESS_TRAP_FP_EL2 = 7,
2721 CP_ACCESS_TRAP_FP_EL3 = 8,
2722} CPAccessResult;
2723
2724
2725
2726
2727typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2728typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2729 uint64_t value);
2730
2731typedef CPAccessResult CPAccessFn(CPUARMState *env,
2732 const ARMCPRegInfo *opaque,
2733 bool isread);
2734
2735typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2736
2737#define CP_ANY 0xff
2738
2739
2740struct ARMCPRegInfo {
2741
2742 const char *name;
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760 uint8_t cp;
2761 uint8_t crn;
2762 uint8_t crm;
2763 uint8_t opc0;
2764 uint8_t opc1;
2765 uint8_t opc2;
2766
2767 int state;
2768
2769 int type;
2770
2771 int access;
2772
2773 int secure;
2774
2775
2776
2777
2778 void *opaque;
2779
2780
2781
2782 uint64_t resetvalue;
2783
2784
2785
2786
2787
2788
2789 ptrdiff_t fieldoffset;
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802 ptrdiff_t bank_fieldoffsets[2];
2803
2804
2805
2806
2807
2808
2809 CPAccessFn *accessfn;
2810
2811
2812
2813
2814 CPReadFn *readfn;
2815
2816
2817
2818
2819 CPWriteFn *writefn;
2820
2821
2822
2823
2824
2825 CPReadFn *raw_readfn;
2826
2827
2828
2829
2830
2831
2832 CPWriteFn *raw_writefn;
2833
2834
2835
2836
2837 CPResetFn *resetfn;
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849 CPReadFn *orig_readfn;
2850 CPWriteFn *orig_writefn;
2851};
2852
2853
2854
2855
2856#define CPREG_FIELD32(env, ri) \
2857 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2858#define CPREG_FIELD64(env, ri) \
2859 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2860
2861#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2862
2863void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2864 const ARMCPRegInfo *regs, void *opaque);
2865void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2866 const ARMCPRegInfo *regs, void *opaque);
2867static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2868{
2869 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2870}
2871static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2872{
2873 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2874}
2875const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2876
2877
2878
2879
2880
2881
2882
2883typedef struct ARMCPRegUserSpaceInfo {
2884
2885 const char *name;
2886
2887
2888 bool is_glob;
2889
2890
2891 uint64_t exported_bits;
2892
2893
2894 uint64_t fixed_bits;
2895} ARMCPRegUserSpaceInfo;
2896
2897#define REGUSERINFO_SENTINEL { .name = NULL }
2898
2899void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2900
2901
2902void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2903 uint64_t value);
2904
2905uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2906
2907
2908
2909
2910void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2911
2912
2913
2914
2915static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2916{
2917 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2918}
2919
2920static inline bool cp_access_ok(int current_el,
2921 const ARMCPRegInfo *ri, int isread)
2922{
2923 return (ri->access >> ((current_el * 2) + isread)) & 1;
2924}
2925
2926
2927uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943bool write_list_to_cpustate(ARMCPU *cpu);
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2967
2968#define ARM_CPUID_TI915T 0x54029152
2969#define ARM_CPUID_TI925T 0x54029252
2970
2971#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2972#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2973#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2974
2975#define cpu_signal_handler cpu_arm_signal_handler
2976#define cpu_list arm_cpu_list
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072#define ARM_MMU_IDX_A 0x10
3073#define ARM_MMU_IDX_NOTLB 0x20
3074#define ARM_MMU_IDX_M 0x40
3075
3076
3077#define ARM_MMU_IDX_A_NS 0x8
3078
3079
3080#define ARM_MMU_IDX_M_PRIV 0x1
3081#define ARM_MMU_IDX_M_NEGPRI 0x2
3082#define ARM_MMU_IDX_M_S 0x4
3083
3084#define ARM_MMU_IDX_TYPE_MASK \
3085 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
3086#define ARM_MMU_IDX_COREIDX_MASK 0xf
3087
3088typedef enum ARMMMUIdx {
3089
3090
3091
3092 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A,
3093 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A,
3094 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A,
3095 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A,
3096 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A,
3097 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A,
3098 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A,
3099 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A,
3100
3101 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS,
3102 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS,
3103 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS,
3104 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS,
3105 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS,
3106 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS,
3107 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS,
3108
3109
3110
3111
3112
3113 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
3114 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
3115 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
3116 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB,
3117 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB,
3118 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB,
3119
3120
3121
3122
3123
3124
3125
3126 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB,
3127 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB,
3128
3129
3130
3131
3132 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
3133 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
3134 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
3135 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
3136 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
3137 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
3138 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
3139 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
3140} ARMMMUIdx;
3141
3142
3143
3144
3145
3146#define TO_CORE_BIT(NAME) \
3147 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
3148
3149typedef enum ARMMMUIdxBit {
3150 TO_CORE_BIT(E10_0),
3151 TO_CORE_BIT(E20_0),
3152 TO_CORE_BIT(E10_1),
3153 TO_CORE_BIT(E10_1_PAN),
3154 TO_CORE_BIT(E2),
3155 TO_CORE_BIT(E20_2),
3156 TO_CORE_BIT(E20_2_PAN),
3157 TO_CORE_BIT(SE10_0),
3158 TO_CORE_BIT(SE20_0),
3159 TO_CORE_BIT(SE10_1),
3160 TO_CORE_BIT(SE20_2),
3161 TO_CORE_BIT(SE10_1_PAN),
3162 TO_CORE_BIT(SE20_2_PAN),
3163 TO_CORE_BIT(SE2),
3164 TO_CORE_BIT(SE3),
3165
3166 TO_CORE_BIT(MUser),
3167 TO_CORE_BIT(MPriv),
3168 TO_CORE_BIT(MUserNegPri),
3169 TO_CORE_BIT(MPrivNegPri),
3170 TO_CORE_BIT(MSUser),
3171 TO_CORE_BIT(MSPriv),
3172 TO_CORE_BIT(MSUserNegPri),
3173 TO_CORE_BIT(MSPrivNegPri),
3174} ARMMMUIdxBit;
3175
3176#undef TO_CORE_BIT
3177
3178#define MMU_USER_IDX 0
3179
3180
3181typedef enum ARMASIdx {
3182 ARMASIdx_NS = 0,
3183 ARMASIdx_S = 1,
3184 ARMASIdx_TagNS = 2,
3185 ARMASIdx_TagS = 3,
3186} ARMASIdx;
3187
3188
3189static inline int arm_debug_target_el(CPUARMState *env)
3190{
3191 bool secure = arm_is_secure(env);
3192 bool route_to_el2 = false;
3193
3194 if (arm_is_el2_enabled(env)) {
3195 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
3196 env->cp15.mdcr_el2 & MDCR_TDE;
3197 }
3198
3199 if (route_to_el2) {
3200 return 2;
3201 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
3202 !arm_el_is_aa64(env, 3) && secure) {
3203 return 3;
3204 } else {
3205 return 1;
3206 }
3207}
3208
3209static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3210{
3211
3212
3213
3214 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3215}
3216
3217
3218static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
3219{
3220 int cur_el = arm_current_el(env);
3221 int debug_el;
3222
3223 if (cur_el == 3) {
3224 return false;
3225 }
3226
3227
3228 if (arm_is_secure_below_el3(env)
3229 && extract32(env->cp15.mdcr_el3, 16, 1)) {
3230 return false;
3231 }
3232
3233
3234
3235
3236
3237 debug_el = arm_debug_target_el(env);
3238
3239 if (cur_el == debug_el) {
3240 return extract32(env->cp15.mdscr_el1, 13, 1)
3241 && !(env->daif & PSTATE_D);
3242 }
3243
3244
3245 return debug_el > cur_el;
3246}
3247
3248static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3249{
3250 int el = arm_current_el(env);
3251
3252 if (el == 0 && arm_el_is_aa64(env, 1)) {
3253 return aa64_generate_debug_exceptions(env);
3254 }
3255
3256 if (arm_is_secure(env)) {
3257 int spd;
3258
3259 if (el == 0 && (env->cp15.sder & 1)) {
3260
3261
3262
3263
3264 return true;
3265 }
3266
3267 spd = extract32(env->cp15.mdcr_el3, 14, 2);
3268 switch (spd) {
3269 case 1:
3270
3271 case 0:
3272
3273
3274
3275
3276
3277 return true;
3278 case 2:
3279 return false;
3280 case 3:
3281 return true;
3282 }
3283 }
3284
3285 return el != 2;
3286}
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3300{
3301 if (env->aarch64) {
3302 return aa64_generate_debug_exceptions(env);
3303 } else {
3304 return aa32_generate_debug_exceptions(env);
3305 }
3306}
3307
3308
3309
3310
3311static inline bool arm_singlestep_active(CPUARMState *env)
3312{
3313 return extract32(env->cp15.mdscr_el1, 0, 1)
3314 && arm_el_is_aa64(env, arm_debug_target_el(env))
3315 && arm_generate_debug_exceptions(env);
3316}
3317
3318static inline bool arm_sctlr_b(CPUARMState *env)
3319{
3320 return
3321
3322
3323
3324
3325#ifndef CONFIG_USER_ONLY
3326 !arm_feature(env, ARM_FEATURE_V7) &&
3327#endif
3328 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3329}
3330
3331uint64_t arm_sctlr(CPUARMState *env, int el);
3332
3333static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3334 bool sctlr_b)
3335{
3336#ifdef CONFIG_USER_ONLY
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349 if (sctlr_b) {
3350 return true;
3351 }
3352#endif
3353
3354 return env->uncached_cpsr & CPSR_E;
3355}
3356
3357static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3358{
3359 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3360}
3361
3362
3363static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3364{
3365 if (!is_a64(env)) {
3366 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3367 } else {
3368 int cur_el = arm_current_el(env);
3369 uint64_t sctlr = arm_sctlr(env, cur_el);
3370 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3371 }
3372}
3373
3374typedef CPUARMState CPUArchState;
3375typedef ARMCPU ArchCPU;
3376
3377#include "exec/cpu-all.h"
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
3398FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
3399FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1)
3400FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
3401FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
3402
3403FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
3404
3405FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
3406
3407
3408
3409
3410FIELD(TBFLAG_AM32, CONDEXEC, 0, 8)
3411FIELD(TBFLAG_AM32, THUMB, 8, 1)
3412
3413
3414
3415
3416FIELD(TBFLAG_A32, VECLEN, 9, 3)
3417FIELD(TBFLAG_A32, VECSTRIDE, 12, 2)
3418
3419
3420
3421
3422
3423
3424FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
3425FIELD(TBFLAG_A32, VFPEN, 14, 1)
3426FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
3427FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
3428
3429
3430
3431
3432
3433FIELD(TBFLAG_A32, NS, 17, 1)
3434
3435
3436
3437
3438
3439FIELD(TBFLAG_M32, HANDLER, 9, 1)
3440
3441FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
3442
3443FIELD(TBFLAG_M32, LSPACT, 11, 1)
3444
3445FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1)
3446
3447FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1)
3448
3449
3450
3451
3452FIELD(TBFLAG_A64, TBII, 0, 2)
3453FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3454FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3455FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3456FIELD(TBFLAG_A64, BT, 9, 1)
3457FIELD(TBFLAG_A64, BTYPE, 10, 2)
3458FIELD(TBFLAG_A64, TBID, 12, 2)
3459FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3460FIELD(TBFLAG_A64, ATA, 15, 1)
3461FIELD(TBFLAG_A64, TCMA, 16, 2)
3462FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3463FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3474{
3475 return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX);
3476}
3477
3478static inline bool bswap_code(bool sctlr_b)
3479{
3480#ifdef CONFIG_USER_ONLY
3481
3482
3483
3484
3485 return
3486#ifdef TARGET_WORDS_BIGENDIAN
3487 1 ^
3488#endif
3489 sctlr_b;
3490#else
3491
3492
3493
3494 return 0;
3495#endif
3496}
3497
3498#ifdef CONFIG_USER_ONLY
3499static inline bool arm_cpu_bswap_data(CPUARMState *env)
3500{
3501 return
3502#ifdef TARGET_WORDS_BIGENDIAN
3503 1 ^
3504#endif
3505 arm_cpu_data_is_big_endian(env);
3506}
3507#endif
3508
3509void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3510 target_ulong *cs_base, uint32_t *flags);
3511
3512enum {
3513 QEMU_PSCI_CONDUIT_DISABLED = 0,
3514 QEMU_PSCI_CONDUIT_SMC = 1,
3515 QEMU_PSCI_CONDUIT_HVC = 2,
3516};
3517
3518#ifndef CONFIG_USER_ONLY
3519
3520static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3521{
3522 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3523}
3524
3525
3526
3527
3528
3529static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3530{
3531 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3532}
3533#endif
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3546 void *opaque);
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3558 *opaque);
3559
3560
3561
3562
3563
3564void arm_rebuild_hflags(CPUARMState *env);
3565
3566
3567
3568
3569
3570static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3571{
3572 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3573}
3574
3575
3576
3577
3578
3579static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3580{
3581 return &env->vfp.zregs[regno].d[0];
3582}
3583
3584
3585
3586
3587
3588static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3589{
3590 return &env->vfp.zregs[regno].d[0];
3591}
3592
3593
3594extern const uint64_t pred_esz_masks[4];
3595
3596
3597static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
3598{
3599 return x;
3600}
3601
3602
3603
3604
3605
3606
3607#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
3608#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
3609
3610
3611
3612
3613#define PAGE_BTI PAGE_TARGET_1
3614#define PAGE_MTE PAGE_TARGET_2
3615
3616#ifdef TARGET_TAGGED_ADDRESSES
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
3629{
3630 ARMCPU *cpu = ARM_CPU(cs);
3631 if (cpu->env.tagged_addr_enable) {
3632
3633
3634
3635
3636 x &= sextract64(x, 0, 56);
3637 }
3638 return x;
3639}
3640#endif
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3662{
3663 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3664}
3665
3666static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3667{
3668 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3669}
3670
3671static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
3672{
3673
3674 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
3675}
3676
3677static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3678{
3679 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3680}
3681
3682static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3683{
3684 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3685}
3686
3687static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3688{
3689 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3690}
3691
3692static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3693{
3694 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3695}
3696
3697static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3698{
3699 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3700}
3701
3702static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3703{
3704 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3705}
3706
3707static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3708{
3709 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3710}
3711
3712static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3713{
3714 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3715}
3716
3717static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3718{
3719 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3720}
3721
3722static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3723{
3724 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3725}
3726
3727static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3728{
3729 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3730}
3731
3732static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3733{
3734 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3735}
3736
3737static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3738{
3739 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3740}
3741
3742static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
3743{
3744 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
3745}
3746
3747static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
3748{
3749 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
3750}
3751
3752static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
3753{
3754
3755
3756
3757
3758 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
3759}
3760
3761static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3762{
3763
3764 if (isar_feature_aa32_mprofile(id)) {
3765 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
3766 } else {
3767 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
3768 }
3769}
3770
3771static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3772{
3773
3774
3775
3776
3777 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3778}
3779
3780static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3781{
3782
3783 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3784}
3785
3786static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3787{
3788 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3789}
3790
3791static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3792{
3793
3794 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3795}
3796
3797static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3798{
3799
3800 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3801}
3802
3803static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3804{
3805
3806 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3807}
3808
3809static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3810{
3811
3812 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3813}
3814
3815static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3816{
3817 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3818}
3819
3820
3821
3822
3823
3824
3825static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3826{
3827 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3828}
3829
3830static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3831{
3832 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3833}
3834
3835
3836
3837
3838
3839
3840
3841
3842static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3843{
3844 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3845}
3846
3847static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3848{
3849 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3850}
3851
3852static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3853{
3854 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3855}
3856
3857static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3858{
3859 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3860}
3861
3862static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3863{
3864 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3865}
3866
3867static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
3868{
3869 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
3870}
3871
3872static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3873{
3874 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3875}
3876
3877static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3878{
3879 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3880}
3881
3882static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
3883{
3884
3885 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3886 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3887}
3888
3889static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
3890{
3891
3892 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3893 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3894}
3895
3896static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3897{
3898 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
3899}
3900
3901static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
3902{
3903 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
3904}
3905
3906static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
3907{
3908 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
3909}
3910
3911static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
3912{
3913 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
3914}
3915
3916static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
3917{
3918 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
3919}
3920
3921static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
3922{
3923 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
3924}
3925
3926
3927
3928
3929static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3930{
3931 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3932}
3933
3934static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3935{
3936 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3937}
3938
3939static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3940{
3941 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3942}
3943
3944static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3945{
3946 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3947}
3948
3949static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3950{
3951 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3952}
3953
3954static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3955{
3956 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3957}
3958
3959static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3960{
3961 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3962}
3963
3964static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3965{
3966 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3967}
3968
3969static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3970{
3971 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3972}
3973
3974static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3975{
3976 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3977}
3978
3979static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3980{
3981 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3982}
3983
3984static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3985{
3986 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3987}
3988
3989static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3990{
3991 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3992}
3993
3994static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3995{
3996 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3997}
3998
3999static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
4000{
4001 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
4002}
4003
4004static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
4005{
4006 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
4007}
4008
4009static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
4010{
4011 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
4012}
4013
4014static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
4015{
4016 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
4017}
4018
4019static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
4020{
4021
4022
4023
4024
4025 return (id->id_aa64isar1 &
4026 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
4027 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
4028 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
4029 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
4030}
4031
4032static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
4033{
4034
4035
4036
4037
4038 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
4039}
4040
4041static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
4042{
4043 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
4044}
4045
4046static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
4047{
4048 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
4049}
4050
4051static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
4052{
4053 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
4054}
4055
4056static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
4057{
4058 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
4059}
4060
4061static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
4062{
4063 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
4064}
4065
4066static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
4067{
4068
4069 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
4070}
4071
4072static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
4073{
4074
4075 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
4076}
4077
4078static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
4079{
4080 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
4081}
4082
4083static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
4084{
4085 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
4086}
4087
4088static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
4089{
4090 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
4091}
4092
4093static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
4094{
4095 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
4096}
4097
4098static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
4099{
4100 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
4101}
4102
4103static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
4104{
4105 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
4106}
4107
4108static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
4109{
4110 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
4111}
4112
4113static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
4114{
4115 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
4116}
4117
4118static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
4119{
4120 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
4121}
4122
4123static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
4124{
4125 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
4126}
4127
4128static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
4129{
4130 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
4131}
4132
4133static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
4134{
4135 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
4136}
4137
4138static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
4139{
4140 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
4141}
4142
4143static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
4144{
4145 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
4146 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4147}
4148
4149static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
4150{
4151 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
4152 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4153}
4154
4155static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
4156{
4157 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
4158}
4159
4160static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
4161{
4162 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
4163}
4164
4165static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
4166{
4167 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
4168}
4169
4170static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
4171{
4172 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
4173}
4174
4175static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
4176{
4177 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
4178}
4179
4180static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
4181{
4182 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
4183}
4184
4185
4186
4187
4188static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
4189{
4190 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
4191}
4192
4193static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
4194{
4195 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
4196}
4197
4198static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
4199{
4200 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
4201}
4202
4203static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
4204{
4205 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
4206}
4207
4208static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
4209{
4210 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
4211}
4212
4213static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
4214{
4215 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
4216}
4217
4218
4219
4220
4221#define cpu_isar_feature(name, cpu) \
4222 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
4223
4224#endif
4225