1#ifndef TARGET_ARM_TRANSLATE_H
2#define TARGET_ARM_TRANSLATE_H
3
4#include "exec/translator.h"
5#include "internals.h"
6
7
8
9typedef struct DisasContext {
10 DisasContextBase base;
11 const ARMISARegisters *isar;
12
13
14 target_ulong pc_curr;
15 target_ulong page_start;
16 uint32_t insn;
17
18 int condjmp;
19
20 TCGLabel *condlabel;
21
22 int condexec_mask;
23 int condexec_cond;
24 int thumb;
25 int sctlr_b;
26 MemOp be_data;
27#if !defined(CONFIG_USER_ONLY)
28 int user;
29#endif
30 ARMMMUIdx mmu_idx;
31 uint8_t tbii;
32 uint8_t tbid;
33 uint8_t tcma;
34 bool ns;
35 int fp_excp_el;
36 int sve_excp_el;
37 int sve_len;
38
39 bool secure_routed_to_el3;
40 bool vfp_enabled;
41 int vec_len;
42 int vec_stride;
43 bool v7m_handler_mode;
44 bool v8m_secure;
45 bool v8m_stackcheck;
46 bool v8m_fpccr_s_wrong;
47 bool v7m_new_fp_ctxt_needed;
48 bool v7m_lspact;
49
50
51
52 uint32_t svc_imm;
53 int aarch64;
54 int current_el;
55
56 int debug_target_el;
57 GHashTable *cp_regs;
58 uint64_t features;
59
60
61
62
63
64
65
66 bool fp_access_checked;
67 bool sve_access_checked;
68
69
70
71 bool ss_active;
72 bool pstate_ss;
73
74
75
76
77 bool is_ldex;
78
79 bool unpriv;
80
81 bool pauth_active;
82
83 bool ata;
84
85 bool mte_active[2];
86
87 bool bt;
88
89 bool hstr_active;
90
91
92
93
94 int8_t btype;
95
96 uint8_t dcz_blocksize;
97
98 bool guarded_page;
99
100 int c15_cpar;
101
102 TCGOp *insn_start;
103#define TMP_A64_MAX 16
104 int tmp_a64_count;
105 TCGv_i64 tmp_a64[TMP_A64_MAX];
106} DisasContext;
107
108typedef struct DisasCompare {
109 TCGCond cond;
110 TCGv_i32 value;
111 bool value_global;
112} DisasCompare;
113
114
115extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
116extern TCGv_i64 cpu_exclusive_addr;
117extern TCGv_i64 cpu_exclusive_val;
118
119static inline int arm_dc_feature(DisasContext *dc, int feature)
120{
121 return (dc->features & (1ULL << feature)) != 0;
122}
123
124static inline int get_mem_index(DisasContext *s)
125{
126 return arm_to_core_mmu_idx(s->mmu_idx);
127}
128
129
130
131
132static inline int default_exception_el(DisasContext *s)
133{
134
135
136
137
138
139 return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
140 ? 3 : MAX(1, s->current_el);
141}
142
143static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
144{
145
146
147
148 syn &= ARM_INSN_START_WORD2_MASK;
149 syn >>= ARM_INSN_START_WORD2_SHIFT;
150
151
152 assert(s->insn_start != NULL);
153 tcg_set_insn_start_param(s->insn_start, 2, syn);
154 s->insn_start = NULL;
155}
156
157
158#define DISAS_JUMP DISAS_TARGET_0
159
160#define DISAS_UPDATE_EXIT DISAS_TARGET_1
161
162
163
164
165#define DISAS_WFI DISAS_TARGET_2
166#define DISAS_SWI DISAS_TARGET_3
167
168#define DISAS_WFE DISAS_TARGET_4
169#define DISAS_HVC DISAS_TARGET_5
170#define DISAS_SMC DISAS_TARGET_6
171#define DISAS_YIELD DISAS_TARGET_7
172
173
174
175#define DISAS_BX_EXCRET DISAS_TARGET_8
176
177
178
179
180
181
182
183#define DISAS_EXIT DISAS_TARGET_9
184
185#define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10
186
187#ifdef TARGET_AARCH64
188void a64_translate_init(void);
189void gen_a64_set_pc_im(uint64_t val);
190extern const TranslatorOps aarch64_translator_ops;
191#else
192static inline void a64_translate_init(void)
193{
194}
195
196static inline void gen_a64_set_pc_im(uint64_t val)
197{
198}
199#endif
200
201void arm_test_cc(DisasCompare *cmp, int cc);
202void arm_free_cc(DisasCompare *cmp);
203void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
204void arm_gen_test_cc(int cc, TCGLabel *label);
205
206
207static inline TCGv_i32 get_ahp_flag(void)
208{
209 TCGv_i32 ret = tcg_temp_new_i32();
210
211 tcg_gen_ld_i32(ret, cpu_env,
212 offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
213 tcg_gen_extract_i32(ret, ret, 26, 1);
214
215 return ret;
216}
217
218
219static inline void set_pstate_bits(uint32_t bits)
220{
221 TCGv_i32 p = tcg_temp_new_i32();
222
223 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
224
225 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
226 tcg_gen_ori_i32(p, p, bits);
227 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
228 tcg_temp_free_i32(p);
229}
230
231
232static inline void clear_pstate_bits(uint32_t bits)
233{
234 TCGv_i32 p = tcg_temp_new_i32();
235
236 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
237
238 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
239 tcg_gen_andi_i32(p, p, ~bits);
240 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
241 tcg_temp_free_i32(p);
242}
243
244
245static inline void gen_ss_advance(DisasContext *s)
246{
247 if (s->ss_active) {
248 s->pstate_ss = 0;
249 clear_pstate_bits(PSTATE_SS);
250 }
251}
252
253static inline void gen_exception(int excp, uint32_t syndrome,
254 uint32_t target_el)
255{
256 TCGv_i32 tcg_excp = tcg_const_i32(excp);
257 TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
258 TCGv_i32 tcg_el = tcg_const_i32(target_el);
259
260 gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
261 tcg_syn, tcg_el);
262
263 tcg_temp_free_i32(tcg_el);
264 tcg_temp_free_i32(tcg_syn);
265 tcg_temp_free_i32(tcg_excp);
266}
267
268
269static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
270{
271 bool same_el = (s->debug_target_el == s->current_el);
272
273
274
275
276
277 assert(s->debug_target_el >= s->current_el);
278
279 gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
280}
281
282
283
284
285
286
287uint64_t vfp_expand_imm(int size, uint8_t imm8);
288
289
290void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
291 uint32_t opr_sz, uint32_t max_sz);
292void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
293 uint32_t opr_sz, uint32_t max_sz);
294void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
295 uint32_t opr_sz, uint32_t max_sz);
296void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
297 uint32_t opr_sz, uint32_t max_sz);
298void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
299 uint32_t opr_sz, uint32_t max_sz);
300
301void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
302 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
303void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
304 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
305
306void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
307 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
308void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
309 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
310void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
311 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
312
313void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
314void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
315void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
316void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
317void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
318
319void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
320 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
321void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
322 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
323void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
324 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
325void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
326 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
327
328void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
329 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
330void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
331 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
332
333void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
334 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
335void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
336 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
337void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
338 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
339void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
340 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
341
342void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
343 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
344void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
345 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
346
347void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
348 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
349void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
350 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
351
352void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
353 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
354void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
355 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
356
357void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
358 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
359void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
360 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
361
362
363
364
365#define dc_isar_feature(name, ctx) \
366 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
367
368
369typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
370typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
371 uint32_t, uint32_t);
372typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
373 uint32_t, uint32_t, uint32_t);
374typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
375 uint32_t, uint32_t, uint32_t);
376
377
378typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
379typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
380typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
381typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
382typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
383typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
384typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
385typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
386typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
387typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
388typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
389typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
390typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
391typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
392typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
393typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
394typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
395typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
396
397
398
399
400typedef enum ARMFPStatusFlavour {
401 FPST_FPCR,
402 FPST_FPCR_F16,
403 FPST_STD,
404 FPST_STD_F16,
405} ARMFPStatusFlavour;
406
407
408
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421
422
423
424static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
425{
426 TCGv_ptr statusptr = tcg_temp_new_ptr();
427 int offset;
428
429 switch (flavour) {
430 case FPST_FPCR:
431 offset = offsetof(CPUARMState, vfp.fp_status);
432 break;
433 case FPST_FPCR_F16:
434 offset = offsetof(CPUARMState, vfp.fp_status_f16);
435 break;
436 case FPST_STD:
437 offset = offsetof(CPUARMState, vfp.standard_fp_status);
438 break;
439 case FPST_STD_F16:
440 offset = offsetof(CPUARMState, vfp.standard_fp_status_f16);
441 break;
442 default:
443 g_assert_not_reached();
444 }
445 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
446 return statusptr;
447}
448
449#endif
450