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20#include "qemu/osdep.h"
21#include "cpu.h"
22#include "exec/helper-proto.h"
23#include "internals.h"
24#ifdef CONFIG_TCG
25#include "qemu/log.h"
26#include "fpu/softfloat.h"
27#endif
28
29
30
31
32
33#ifdef CONFIG_TCG
34
35
36static inline int vfp_exceptbits_from_host(int host_bits)
37{
38 int target_bits = 0;
39
40 if (host_bits & float_flag_invalid) {
41 target_bits |= 1;
42 }
43 if (host_bits & float_flag_divbyzero) {
44 target_bits |= 2;
45 }
46 if (host_bits & float_flag_overflow) {
47 target_bits |= 4;
48 }
49 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
50 target_bits |= 8;
51 }
52 if (host_bits & float_flag_inexact) {
53 target_bits |= 0x10;
54 }
55 if (host_bits & float_flag_input_denormal) {
56 target_bits |= 0x80;
57 }
58 return target_bits;
59}
60
61
62static inline int vfp_exceptbits_to_host(int target_bits)
63{
64 int host_bits = 0;
65
66 if (target_bits & 1) {
67 host_bits |= float_flag_invalid;
68 }
69 if (target_bits & 2) {
70 host_bits |= float_flag_divbyzero;
71 }
72 if (target_bits & 4) {
73 host_bits |= float_flag_overflow;
74 }
75 if (target_bits & 8) {
76 host_bits |= float_flag_underflow;
77 }
78 if (target_bits & 0x10) {
79 host_bits |= float_flag_inexact;
80 }
81 if (target_bits & 0x80) {
82 host_bits |= float_flag_input_denormal;
83 }
84 return host_bits;
85}
86
87static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
88{
89 uint32_t i;
90
91 i = get_float_exception_flags(&env->vfp.fp_status);
92 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
93
94 i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
95 & ~float_flag_input_denormal);
96 i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
97 & ~float_flag_input_denormal);
98 return vfp_exceptbits_from_host(i);
99}
100
101static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
102{
103 int i;
104 uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
105
106 changed ^= val;
107 if (changed & (3 << 22)) {
108 i = (val >> 22) & 3;
109 switch (i) {
110 case FPROUNDING_TIEEVEN:
111 i = float_round_nearest_even;
112 break;
113 case FPROUNDING_POSINF:
114 i = float_round_up;
115 break;
116 case FPROUNDING_NEGINF:
117 i = float_round_down;
118 break;
119 case FPROUNDING_ZERO:
120 i = float_round_to_zero;
121 break;
122 }
123 set_float_rounding_mode(i, &env->vfp.fp_status);
124 set_float_rounding_mode(i, &env->vfp.fp_status_f16);
125 }
126 if (changed & FPCR_FZ16) {
127 bool ftz_enabled = val & FPCR_FZ16;
128 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
129 set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
130 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
131 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
132 }
133 if (changed & FPCR_FZ) {
134 bool ftz_enabled = val & FPCR_FZ;
135 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
136 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
137 }
138 if (changed & FPCR_DN) {
139 bool dnan_enabled = val & FPCR_DN;
140 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
141 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
142 }
143
144
145
146
147
148
149 i = vfp_exceptbits_to_host(val);
150 set_float_exception_flags(i, &env->vfp.fp_status);
151 set_float_exception_flags(0, &env->vfp.fp_status_f16);
152 set_float_exception_flags(0, &env->vfp.standard_fp_status);
153 set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
154}
155
156#else
157
158static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
159{
160 return 0;
161}
162
163static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
164{
165}
166
167#endif
168
169uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
170{
171 uint32_t i, fpscr;
172
173 fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
174 | (env->vfp.vec_len << 16)
175 | (env->vfp.vec_stride << 20);
176
177
178
179
180
181 fpscr |= env->v7m.ltpsize << 16;
182
183 fpscr |= vfp_get_fpscr_from_host(env);
184
185 i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
186 fpscr |= i ? FPCR_QC : 0;
187
188 return fpscr;
189}
190
191uint32_t vfp_get_fpscr(CPUARMState *env)
192{
193 return HELPER(vfp_get_fpscr)(env);
194}
195
196void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
197{
198
199 if (!cpu_isar_feature(any_fp16, env_archcpu(env))) {
200 val &= ~FPCR_FZ16;
201 }
202
203 vfp_set_fpscr_to_host(env, val);
204
205 if (!arm_feature(env, ARM_FEATURE_M)) {
206
207
208
209
210
211
212
213
214
215
216 env->vfp.vec_len = extract32(val, 16, 3);
217 env->vfp.vec_stride = extract32(val, 20, 2);
218 }
219
220 if (arm_feature(env, ARM_FEATURE_NEON)) {
221
222
223
224
225
226 env->vfp.qc[0] = val & FPCR_QC;
227 env->vfp.qc[1] = 0;
228 env->vfp.qc[2] = 0;
229 env->vfp.qc[3] = 0;
230 }
231
232
233
234
235
236
237
238
239
240
241 env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
242}
243
244void vfp_set_fpscr(CPUARMState *env, uint32_t val)
245{
246 HELPER(vfp_set_fpscr)(env, val);
247}
248
249#ifdef CONFIG_TCG
250
251#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
252
253#define VFP_BINOP(name) \
254dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
255{ \
256 float_status *fpst = fpstp; \
257 return float16_ ## name(a, b, fpst); \
258} \
259float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
260{ \
261 float_status *fpst = fpstp; \
262 return float32_ ## name(a, b, fpst); \
263} \
264float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
265{ \
266 float_status *fpst = fpstp; \
267 return float64_ ## name(a, b, fpst); \
268}
269VFP_BINOP(add)
270VFP_BINOP(sub)
271VFP_BINOP(mul)
272VFP_BINOP(div)
273VFP_BINOP(min)
274VFP_BINOP(max)
275VFP_BINOP(minnum)
276VFP_BINOP(maxnum)
277#undef VFP_BINOP
278
279dh_ctype_f16 VFP_HELPER(neg, h)(dh_ctype_f16 a)
280{
281 return float16_chs(a);
282}
283
284float32 VFP_HELPER(neg, s)(float32 a)
285{
286 return float32_chs(a);
287}
288
289float64 VFP_HELPER(neg, d)(float64 a)
290{
291 return float64_chs(a);
292}
293
294dh_ctype_f16 VFP_HELPER(abs, h)(dh_ctype_f16 a)
295{
296 return float16_abs(a);
297}
298
299float32 VFP_HELPER(abs, s)(float32 a)
300{
301 return float32_abs(a);
302}
303
304float64 VFP_HELPER(abs, d)(float64 a)
305{
306 return float64_abs(a);
307}
308
309dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env)
310{
311 return float16_sqrt(a, &env->vfp.fp_status_f16);
312}
313
314float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
315{
316 return float32_sqrt(a, &env->vfp.fp_status);
317}
318
319float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
320{
321 return float64_sqrt(a, &env->vfp.fp_status);
322}
323
324static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
325{
326 uint32_t flags;
327 switch (cmp) {
328 case float_relation_equal:
329 flags = 0x6;
330 break;
331 case float_relation_less:
332 flags = 0x8;
333 break;
334 case float_relation_greater:
335 flags = 0x2;
336 break;
337 case float_relation_unordered:
338 flags = 0x3;
339 break;
340 default:
341 g_assert_not_reached();
342 }
343 env->vfp.xregs[ARM_VFP_FPSCR] =
344 deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags);
345}
346
347
348#define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \
349void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
350{ \
351 softfloat_to_vfp_compare(env, \
352 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \
353} \
354void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
355{ \
356 softfloat_to_vfp_compare(env, \
357 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
358}
359DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16)
360DO_VFP_cmp(s, float32, float32, fp_status)
361DO_VFP_cmp(d, float64, float64, fp_status)
362#undef DO_VFP_cmp
363
364
365
366#define CONV_ITOF(name, ftype, fsz, sign) \
367ftype HELPER(name)(uint32_t x, void *fpstp) \
368{ \
369 float_status *fpst = fpstp; \
370 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
371}
372
373#define CONV_FTOI(name, ftype, fsz, sign, round) \
374sign##int32_t HELPER(name)(ftype x, void *fpstp) \
375{ \
376 float_status *fpst = fpstp; \
377 if (float##fsz##_is_any_nan(x)) { \
378 float_raise(float_flag_invalid, fpst); \
379 return 0; \
380 } \
381 return float##fsz##_to_##sign##int32##round(x, fpst); \
382}
383
384#define FLOAT_CONVS(name, p, ftype, fsz, sign) \
385 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
386 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
387 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
388
389FLOAT_CONVS(si, h, uint32_t, 16, )
390FLOAT_CONVS(si, s, float32, 32, )
391FLOAT_CONVS(si, d, float64, 64, )
392FLOAT_CONVS(ui, h, uint32_t, 16, u)
393FLOAT_CONVS(ui, s, float32, 32, u)
394FLOAT_CONVS(ui, d, float64, 64, u)
395
396#undef CONV_ITOF
397#undef CONV_FTOI
398#undef FLOAT_CONVS
399
400
401float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
402{
403 return float32_to_float64(x, &env->vfp.fp_status);
404}
405
406float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
407{
408 return float64_to_float32(x, &env->vfp.fp_status);
409}
410
411
412
413
414
415
416
417
418#define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
419ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
420 void *fpstp) \
421{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
422
423#define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
424 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
425 uint32_t shift, \
426 void *fpstp) \
427 { \
428 ftype ret; \
429 float_status *fpst = fpstp; \
430 FloatRoundMode oldmode = fpst->float_rounding_mode; \
431 fpst->float_rounding_mode = float_round_nearest_even; \
432 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
433 fpst->float_rounding_mode = oldmode; \
434 return ret; \
435 }
436
437#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
438uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
439 void *fpst) \
440{ \
441 if (unlikely(float##fsz##_is_any_nan(x))) { \
442 float_raise(float_flag_invalid, fpst); \
443 return 0; \
444 } \
445 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
446}
447
448#define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \
449VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
450VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
451VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
452 float_round_to_zero, _round_to_zero) \
453VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
454 get_float_rounding_mode(fpst), )
455
456#define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \
457VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
458VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
459 get_float_rounding_mode(fpst), )
460
461VFP_CONV_FIX(sh, d, 64, float64, 64, int16)
462VFP_CONV_FIX(sl, d, 64, float64, 64, int32)
463VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64)
464VFP_CONV_FIX(uh, d, 64, float64, 64, uint16)
465VFP_CONV_FIX(ul, d, 64, float64, 64, uint32)
466VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64)
467VFP_CONV_FIX(sh, s, 32, float32, 32, int16)
468VFP_CONV_FIX(sl, s, 32, float32, 32, int32)
469VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64)
470VFP_CONV_FIX(uh, s, 32, float32, 32, uint16)
471VFP_CONV_FIX(ul, s, 32, float32, 32, uint32)
472VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64)
473VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16)
474VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32)
475VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64)
476VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16)
477VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32)
478VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64)
479
480#undef VFP_CONV_FIX
481#undef VFP_CONV_FIX_FLOAT
482#undef VFP_CONV_FLOAT_FIX_ROUND
483#undef VFP_CONV_FIX_A64
484
485
486
487
488uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
489{
490 float_status *fp_status = fpstp;
491
492 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
493 set_float_rounding_mode(rmode, fp_status);
494
495 return prev_rmode;
496}
497
498
499float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
500{
501
502
503
504 float_status *fpst = fpstp;
505 bool save = get_flush_inputs_to_zero(fpst);
506 set_flush_inputs_to_zero(false, fpst);
507 float32 r = float16_to_float32(a, !ahp_mode, fpst);
508 set_flush_inputs_to_zero(save, fpst);
509 return r;
510}
511
512uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
513{
514
515
516
517 float_status *fpst = fpstp;
518 bool save = get_flush_to_zero(fpst);
519 set_flush_to_zero(false, fpst);
520 float16 r = float32_to_float16(a, !ahp_mode, fpst);
521 set_flush_to_zero(save, fpst);
522 return r;
523}
524
525float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
526{
527
528
529
530 float_status *fpst = fpstp;
531 bool save = get_flush_inputs_to_zero(fpst);
532 set_flush_inputs_to_zero(false, fpst);
533 float64 r = float16_to_float64(a, !ahp_mode, fpst);
534 set_flush_inputs_to_zero(save, fpst);
535 return r;
536}
537
538uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
539{
540
541
542
543 float_status *fpst = fpstp;
544 bool save = get_flush_to_zero(fpst);
545 set_flush_to_zero(false, fpst);
546 float16 r = float64_to_float16(a, !ahp_mode, fpst);
547 set_flush_to_zero(save, fpst);
548 return r;
549}
550
551
552
553
554
555#define float64_256 make_float64(0x4070000000000000LL)
556#define float64_512 make_float64(0x4080000000000000LL)
557#define float16_maxnorm make_float16(0x7bff)
558#define float32_maxnorm make_float32(0x7f7fffff)
559#define float64_maxnorm make_float64(0x7fefffffffffffffLL)
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574static int recip_estimate(int input)
575{
576 int a, b, r;
577 assert(256 <= input && input < 512);
578 a = (input * 2) + 1;
579 b = (1 << 19) / a;
580 r = (b + 1) >> 1;
581 assert(256 <= r && r < 512);
582 return r;
583}
584
585
586
587
588
589
590
591
592
593
594static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
595{
596 uint32_t scaled, estimate;
597 uint64_t result_frac;
598 int result_exp;
599
600
601 if (*exp == 0) {
602 if (extract64(frac, 51, 1) == 0) {
603 *exp = -1;
604 frac <<= 2;
605 } else {
606 frac <<= 1;
607 }
608 }
609
610
611 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
612 estimate = recip_estimate(scaled);
613
614 result_exp = exp_off - *exp;
615 result_frac = deposit64(0, 44, 8, estimate);
616 if (result_exp == 0) {
617 result_frac = deposit64(result_frac >> 1, 51, 1, 1);
618 } else if (result_exp == -1) {
619 result_frac = deposit64(result_frac >> 2, 50, 2, 1);
620 result_exp = 0;
621 }
622
623 *exp = result_exp;
624
625 return result_frac;
626}
627
628static bool round_to_inf(float_status *fpst, bool sign_bit)
629{
630 switch (fpst->float_rounding_mode) {
631 case float_round_nearest_even:
632 return true;
633 case float_round_up:
634 return !sign_bit;
635 case float_round_down:
636 return sign_bit;
637 case float_round_to_zero:
638 return false;
639 default:
640 g_assert_not_reached();
641 }
642}
643
644uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
645{
646 float_status *fpst = fpstp;
647 float16 f16 = float16_squash_input_denormal(input, fpst);
648 uint32_t f16_val = float16_val(f16);
649 uint32_t f16_sign = float16_is_neg(f16);
650 int f16_exp = extract32(f16_val, 10, 5);
651 uint32_t f16_frac = extract32(f16_val, 0, 10);
652 uint64_t f64_frac;
653
654 if (float16_is_any_nan(f16)) {
655 float16 nan = f16;
656 if (float16_is_signaling_nan(f16, fpst)) {
657 float_raise(float_flag_invalid, fpst);
658 nan = float16_silence_nan(f16, fpst);
659 }
660 if (fpst->default_nan_mode) {
661 nan = float16_default_nan(fpst);
662 }
663 return nan;
664 } else if (float16_is_infinity(f16)) {
665 return float16_set_sign(float16_zero, float16_is_neg(f16));
666 } else if (float16_is_zero(f16)) {
667 float_raise(float_flag_divbyzero, fpst);
668 return float16_set_sign(float16_infinity, float16_is_neg(f16));
669 } else if (float16_abs(f16) < (1 << 8)) {
670
671 float_raise(float_flag_overflow | float_flag_inexact, fpst);
672 if (round_to_inf(fpst, f16_sign)) {
673 return float16_set_sign(float16_infinity, f16_sign);
674 } else {
675 return float16_set_sign(float16_maxnorm, f16_sign);
676 }
677 } else if (f16_exp >= 29 && fpst->flush_to_zero) {
678 float_raise(float_flag_underflow, fpst);
679 return float16_set_sign(float16_zero, float16_is_neg(f16));
680 }
681
682 f64_frac = call_recip_estimate(&f16_exp, 29,
683 ((uint64_t) f16_frac) << (52 - 10));
684
685
686 f16_val = deposit32(0, 15, 1, f16_sign);
687 f16_val = deposit32(f16_val, 10, 5, f16_exp);
688 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
689 return make_float16(f16_val);
690}
691
692float32 HELPER(recpe_f32)(float32 input, void *fpstp)
693{
694 float_status *fpst = fpstp;
695 float32 f32 = float32_squash_input_denormal(input, fpst);
696 uint32_t f32_val = float32_val(f32);
697 bool f32_sign = float32_is_neg(f32);
698 int f32_exp = extract32(f32_val, 23, 8);
699 uint32_t f32_frac = extract32(f32_val, 0, 23);
700 uint64_t f64_frac;
701
702 if (float32_is_any_nan(f32)) {
703 float32 nan = f32;
704 if (float32_is_signaling_nan(f32, fpst)) {
705 float_raise(float_flag_invalid, fpst);
706 nan = float32_silence_nan(f32, fpst);
707 }
708 if (fpst->default_nan_mode) {
709 nan = float32_default_nan(fpst);
710 }
711 return nan;
712 } else if (float32_is_infinity(f32)) {
713 return float32_set_sign(float32_zero, float32_is_neg(f32));
714 } else if (float32_is_zero(f32)) {
715 float_raise(float_flag_divbyzero, fpst);
716 return float32_set_sign(float32_infinity, float32_is_neg(f32));
717 } else if (float32_abs(f32) < (1ULL << 21)) {
718
719 float_raise(float_flag_overflow | float_flag_inexact, fpst);
720 if (round_to_inf(fpst, f32_sign)) {
721 return float32_set_sign(float32_infinity, f32_sign);
722 } else {
723 return float32_set_sign(float32_maxnorm, f32_sign);
724 }
725 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
726 float_raise(float_flag_underflow, fpst);
727 return float32_set_sign(float32_zero, float32_is_neg(f32));
728 }
729
730 f64_frac = call_recip_estimate(&f32_exp, 253,
731 ((uint64_t) f32_frac) << (52 - 23));
732
733
734 f32_val = deposit32(0, 31, 1, f32_sign);
735 f32_val = deposit32(f32_val, 23, 8, f32_exp);
736 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
737 return make_float32(f32_val);
738}
739
740float64 HELPER(recpe_f64)(float64 input, void *fpstp)
741{
742 float_status *fpst = fpstp;
743 float64 f64 = float64_squash_input_denormal(input, fpst);
744 uint64_t f64_val = float64_val(f64);
745 bool f64_sign = float64_is_neg(f64);
746 int f64_exp = extract64(f64_val, 52, 11);
747 uint64_t f64_frac = extract64(f64_val, 0, 52);
748
749
750 if (float64_is_any_nan(f64)) {
751 float64 nan = f64;
752 if (float64_is_signaling_nan(f64, fpst)) {
753 float_raise(float_flag_invalid, fpst);
754 nan = float64_silence_nan(f64, fpst);
755 }
756 if (fpst->default_nan_mode) {
757 nan = float64_default_nan(fpst);
758 }
759 return nan;
760 } else if (float64_is_infinity(f64)) {
761 return float64_set_sign(float64_zero, float64_is_neg(f64));
762 } else if (float64_is_zero(f64)) {
763 float_raise(float_flag_divbyzero, fpst);
764 return float64_set_sign(float64_infinity, float64_is_neg(f64));
765 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
766
767 float_raise(float_flag_overflow | float_flag_inexact, fpst);
768 if (round_to_inf(fpst, f64_sign)) {
769 return float64_set_sign(float64_infinity, f64_sign);
770 } else {
771 return float64_set_sign(float64_maxnorm, f64_sign);
772 }
773 } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
774 float_raise(float_flag_underflow, fpst);
775 return float64_set_sign(float64_zero, float64_is_neg(f64));
776 }
777
778 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
779
780
781 f64_val = deposit64(0, 63, 1, f64_sign);
782 f64_val = deposit64(f64_val, 52, 11, f64_exp);
783 f64_val = deposit64(f64_val, 0, 52, f64_frac);
784 return make_float64(f64_val);
785}
786
787
788
789
790
791static int do_recip_sqrt_estimate(int a)
792{
793 int b, estimate;
794
795 assert(128 <= a && a < 512);
796 if (a < 256) {
797 a = a * 2 + 1;
798 } else {
799 a = (a >> 1) << 1;
800 a = (a + 1) * 2;
801 }
802 b = 512;
803 while (a * (b + 1) * (b + 1) < (1 << 28)) {
804 b += 1;
805 }
806 estimate = (b + 1) / 2;
807 assert(256 <= estimate && estimate < 512);
808
809 return estimate;
810}
811
812
813static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
814{
815 int estimate;
816 uint32_t scaled;
817
818 if (*exp == 0) {
819 while (extract64(frac, 51, 1) == 0) {
820 frac = frac << 1;
821 *exp -= 1;
822 }
823 frac = extract64(frac, 0, 51) << 1;
824 }
825
826 if (*exp & 1) {
827
828 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
829 } else {
830
831 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
832 }
833 estimate = do_recip_sqrt_estimate(scaled);
834
835 *exp = (exp_off - *exp) / 2;
836 return extract64(estimate, 0, 8) << 44;
837}
838
839uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
840{
841 float_status *s = fpstp;
842 float16 f16 = float16_squash_input_denormal(input, s);
843 uint16_t val = float16_val(f16);
844 bool f16_sign = float16_is_neg(f16);
845 int f16_exp = extract32(val, 10, 5);
846 uint16_t f16_frac = extract32(val, 0, 10);
847 uint64_t f64_frac;
848
849 if (float16_is_any_nan(f16)) {
850 float16 nan = f16;
851 if (float16_is_signaling_nan(f16, s)) {
852 float_raise(float_flag_invalid, s);
853 nan = float16_silence_nan(f16, s);
854 }
855 if (s->default_nan_mode) {
856 nan = float16_default_nan(s);
857 }
858 return nan;
859 } else if (float16_is_zero(f16)) {
860 float_raise(float_flag_divbyzero, s);
861 return float16_set_sign(float16_infinity, f16_sign);
862 } else if (f16_sign) {
863 float_raise(float_flag_invalid, s);
864 return float16_default_nan(s);
865 } else if (float16_is_infinity(f16)) {
866 return float16_zero;
867 }
868
869
870
871
872 f64_frac = ((uint64_t) f16_frac) << (52 - 10);
873
874 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
875
876
877 val = deposit32(0, 15, 1, f16_sign);
878 val = deposit32(val, 10, 5, f16_exp);
879 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
880 return make_float16(val);
881}
882
883float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
884{
885 float_status *s = fpstp;
886 float32 f32 = float32_squash_input_denormal(input, s);
887 uint32_t val = float32_val(f32);
888 uint32_t f32_sign = float32_is_neg(f32);
889 int f32_exp = extract32(val, 23, 8);
890 uint32_t f32_frac = extract32(val, 0, 23);
891 uint64_t f64_frac;
892
893 if (float32_is_any_nan(f32)) {
894 float32 nan = f32;
895 if (float32_is_signaling_nan(f32, s)) {
896 float_raise(float_flag_invalid, s);
897 nan = float32_silence_nan(f32, s);
898 }
899 if (s->default_nan_mode) {
900 nan = float32_default_nan(s);
901 }
902 return nan;
903 } else if (float32_is_zero(f32)) {
904 float_raise(float_flag_divbyzero, s);
905 return float32_set_sign(float32_infinity, float32_is_neg(f32));
906 } else if (float32_is_neg(f32)) {
907 float_raise(float_flag_invalid, s);
908 return float32_default_nan(s);
909 } else if (float32_is_infinity(f32)) {
910 return float32_zero;
911 }
912
913
914
915
916 f64_frac = ((uint64_t) f32_frac) << 29;
917
918 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
919
920
921 val = deposit32(0, 31, 1, f32_sign);
922 val = deposit32(val, 23, 8, f32_exp);
923 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
924 return make_float32(val);
925}
926
927float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
928{
929 float_status *s = fpstp;
930 float64 f64 = float64_squash_input_denormal(input, s);
931 uint64_t val = float64_val(f64);
932 bool f64_sign = float64_is_neg(f64);
933 int f64_exp = extract64(val, 52, 11);
934 uint64_t f64_frac = extract64(val, 0, 52);
935
936 if (float64_is_any_nan(f64)) {
937 float64 nan = f64;
938 if (float64_is_signaling_nan(f64, s)) {
939 float_raise(float_flag_invalid, s);
940 nan = float64_silence_nan(f64, s);
941 }
942 if (s->default_nan_mode) {
943 nan = float64_default_nan(s);
944 }
945 return nan;
946 } else if (float64_is_zero(f64)) {
947 float_raise(float_flag_divbyzero, s);
948 return float64_set_sign(float64_infinity, float64_is_neg(f64));
949 } else if (float64_is_neg(f64)) {
950 float_raise(float_flag_invalid, s);
951 return float64_default_nan(s);
952 } else if (float64_is_infinity(f64)) {
953 return float64_zero;
954 }
955
956 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
957
958
959 val = deposit64(0, 61, 1, f64_sign);
960 val = deposit64(val, 52, 11, f64_exp);
961 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
962 return make_float64(val);
963}
964
965uint32_t HELPER(recpe_u32)(uint32_t a)
966{
967 int input, estimate;
968
969 if ((a & 0x80000000) == 0) {
970 return 0xffffffff;
971 }
972
973 input = extract32(a, 23, 9);
974 estimate = recip_estimate(input);
975
976 return deposit32(0, (32 - 9), 9, estimate);
977}
978
979uint32_t HELPER(rsqrte_u32)(uint32_t a)
980{
981 int estimate;
982
983 if ((a & 0xc0000000) == 0) {
984 return 0xffffffff;
985 }
986
987 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
988
989 return deposit32(0, 23, 9, estimate);
990}
991
992
993dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
994 dh_ctype_f16 c, void *fpstp)
995{
996 float_status *fpst = fpstp;
997 return float16_muladd(a, b, c, 0, fpst);
998}
999
1000float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
1001{
1002 float_status *fpst = fpstp;
1003 return float32_muladd(a, b, c, 0, fpst);
1004}
1005
1006float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
1007{
1008 float_status *fpst = fpstp;
1009 return float64_muladd(a, b, c, 0, fpst);
1010}
1011
1012
1013dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status)
1014{
1015 return float16_round_to_int(x, fp_status);
1016}
1017
1018float32 HELPER(rints_exact)(float32 x, void *fp_status)
1019{
1020 return float32_round_to_int(x, fp_status);
1021}
1022
1023float64 HELPER(rintd_exact)(float64 x, void *fp_status)
1024{
1025 return float64_round_to_int(x, fp_status);
1026}
1027
1028dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
1029{
1030 int old_flags = get_float_exception_flags(fp_status), new_flags;
1031 float16 ret;
1032
1033 ret = float16_round_to_int(x, fp_status);
1034
1035
1036 if (!(old_flags & float_flag_inexact)) {
1037 new_flags = get_float_exception_flags(fp_status);
1038 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1039 }
1040
1041 return ret;
1042}
1043
1044float32 HELPER(rints)(float32 x, void *fp_status)
1045{
1046 int old_flags = get_float_exception_flags(fp_status), new_flags;
1047 float32 ret;
1048
1049 ret = float32_round_to_int(x, fp_status);
1050
1051
1052 if (!(old_flags & float_flag_inexact)) {
1053 new_flags = get_float_exception_flags(fp_status);
1054 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1055 }
1056
1057 return ret;
1058}
1059
1060float64 HELPER(rintd)(float64 x, void *fp_status)
1061{
1062 int old_flags = get_float_exception_flags(fp_status), new_flags;
1063 float64 ret;
1064
1065 ret = float64_round_to_int(x, fp_status);
1066
1067 new_flags = get_float_exception_flags(fp_status);
1068
1069
1070 if (!(old_flags & float_flag_inexact)) {
1071 new_flags = get_float_exception_flags(fp_status);
1072 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1073 }
1074
1075 return ret;
1076}
1077
1078
1079int arm_rmode_to_sf(int rmode)
1080{
1081 switch (rmode) {
1082 case FPROUNDING_TIEAWAY:
1083 rmode = float_round_ties_away;
1084 break;
1085 case FPROUNDING_ODD:
1086
1087 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
1088 rmode);
1089
1090 case FPROUNDING_TIEEVEN:
1091 default:
1092 rmode = float_round_nearest_even;
1093 break;
1094 case FPROUNDING_POSINF:
1095 rmode = float_round_up;
1096 break;
1097 case FPROUNDING_NEGINF:
1098 rmode = float_round_down;
1099 break;
1100 case FPROUNDING_ZERO:
1101 rmode = float_round_to_zero;
1102 break;
1103 }
1104 return rmode;
1105}
1106
1107
1108
1109
1110
1111uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
1112{
1113 float_status *status = vstatus;
1114 uint32_t exp, sign;
1115 uint64_t frac;
1116 uint32_t inexact = 1;
1117
1118 sign = extract64(value, 63, 1);
1119 exp = extract64(value, 52, 11);
1120 frac = extract64(value, 0, 52);
1121
1122 if (exp == 0) {
1123
1124 inexact = sign;
1125 if (frac != 0) {
1126 if (status->flush_inputs_to_zero) {
1127 float_raise(float_flag_input_denormal, status);
1128 } else {
1129 float_raise(float_flag_inexact, status);
1130 inexact = 1;
1131 }
1132 }
1133 frac = 0;
1134 } else if (exp == 0x7ff) {
1135
1136 float_raise(float_flag_invalid, status);
1137 frac = 0;
1138 } else {
1139 int true_exp = exp - 1023;
1140 int shift = true_exp - 52;
1141
1142
1143 frac |= 1ull << 52;
1144
1145
1146 if (shift >= 0) {
1147
1148 if (shift >= 64) {
1149
1150 frac = 0;
1151 } else {
1152 frac <<= shift;
1153 }
1154 } else if (shift > -64) {
1155
1156 inexact = (frac << (64 + shift)) != 0;
1157 frac >>= -shift;
1158 } else {
1159
1160 frac = 0;
1161 }
1162
1163
1164 if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) {
1165
1166 float_raise(float_flag_invalid, status);
1167 inexact = 1;
1168 } else if (inexact) {
1169 float_raise(float_flag_inexact, status);
1170 }
1171
1172
1173 if (sign) {
1174 frac = -frac;
1175 }
1176 }
1177
1178
1179 return deposit64(frac, 32, 32, inexact);
1180}
1181
1182uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
1183{
1184 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
1185 uint32_t result = pair;
1186 uint32_t z = (pair >> 32) == 0;
1187
1188
1189 env->vfp.xregs[ARM_VFP_FPSCR]
1190 = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z);
1191
1192 return result;
1193}
1194
1195
1196static float32 frint_s(float32 f, float_status *fpst, int intsize)
1197{
1198 int old_flags = get_float_exception_flags(fpst);
1199 uint32_t exp = extract32(f, 23, 8);
1200
1201 if (unlikely(exp == 0xff)) {
1202
1203 goto overflow;
1204 }
1205
1206
1207 f = float32_round_to_int(f, fpst);
1208 exp = extract32(f, 23, 8);
1209
1210
1211 if (exp < 126 + intsize) {
1212
1213 return f;
1214 }
1215 if (exp == 126 + intsize) {
1216 uint32_t sign = extract32(f, 31, 1);
1217 uint32_t frac = extract32(f, 0, 23);
1218 if (sign && frac == 0) {
1219
1220 return f;
1221 }
1222 }
1223
1224 overflow:
1225
1226
1227
1228
1229 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1230 return (0x100u + 126u + intsize) << 23;
1231}
1232
1233float32 HELPER(frint32_s)(float32 f, void *fpst)
1234{
1235 return frint_s(f, fpst, 32);
1236}
1237
1238float32 HELPER(frint64_s)(float32 f, void *fpst)
1239{
1240 return frint_s(f, fpst, 64);
1241}
1242
1243
1244static float64 frint_d(float64 f, float_status *fpst, int intsize)
1245{
1246 int old_flags = get_float_exception_flags(fpst);
1247 uint32_t exp = extract64(f, 52, 11);
1248
1249 if (unlikely(exp == 0x7ff)) {
1250
1251 goto overflow;
1252 }
1253
1254
1255 f = float64_round_to_int(f, fpst);
1256 exp = extract64(f, 52, 11);
1257
1258
1259 if (exp < 1022 + intsize) {
1260
1261 return f;
1262 }
1263 if (exp == 1022 + intsize) {
1264 uint64_t sign = extract64(f, 63, 1);
1265 uint64_t frac = extract64(f, 0, 52);
1266 if (sign && frac == 0) {
1267
1268 return f;
1269 }
1270 }
1271
1272 overflow:
1273
1274
1275
1276
1277 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1278 return (uint64_t)(0x800 + 1022 + intsize) << 52;
1279}
1280
1281float64 HELPER(frint32_d)(float64 f, void *fpst)
1282{
1283 return frint_d(f, fpst, 32);
1284}
1285
1286float64 HELPER(frint64_d)(float64 f, void *fpst)
1287{
1288 return frint_d(f, fpst, 64);
1289}
1290
1291void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg)
1292{
1293 uint32_t syndrome;
1294
1295 switch (reg) {
1296 case ARM_VFP_MVFR0:
1297 case ARM_VFP_MVFR1:
1298 case ARM_VFP_MVFR2:
1299 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) {
1300 return;
1301 }
1302 break;
1303 case ARM_VFP_FPSID:
1304 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) {
1305 return;
1306 }
1307 break;
1308 default:
1309 g_assert_not_reached();
1310 }
1311
1312 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT)
1313 | ARM_EL_IL
1314 | (1 << 24) | (0xe << 20) | (7 << 14)
1315 | (reg << 10) | (rt << 5) | 1);
1316
1317 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
1318}
1319
1320#endif
1321