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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "qemu/qemu-print.h"
24#include "exec/exec-all.h"
25#include "cpu.h"
26#include "disas/dis-asm.h"
27
28static void avr_cpu_set_pc(CPUState *cs, vaddr value)
29{
30 AVRCPU *cpu = AVR_CPU(cs);
31
32 cpu->env.pc_w = value / 2;
33}
34
35static bool avr_cpu_has_work(CPUState *cs)
36{
37 AVRCPU *cpu = AVR_CPU(cs);
38 CPUAVRState *env = &cpu->env;
39
40 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
41 && cpu_interrupts_enabled(env);
42}
43
44static void avr_cpu_synchronize_from_tb(CPUState *cs,
45 const TranslationBlock *tb)
46{
47 AVRCPU *cpu = AVR_CPU(cs);
48 CPUAVRState *env = &cpu->env;
49
50 env->pc_w = tb->pc / 2;
51}
52
53static void avr_cpu_reset(DeviceState *ds)
54{
55 CPUState *cs = CPU(ds);
56 AVRCPU *cpu = AVR_CPU(cs);
57 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
58 CPUAVRState *env = &cpu->env;
59
60 mcc->parent_reset(ds);
61
62 env->pc_w = 0;
63 env->sregI = 1;
64 env->sregC = 0;
65 env->sregZ = 0;
66 env->sregN = 0;
67 env->sregV = 0;
68 env->sregS = 0;
69 env->sregH = 0;
70 env->sregT = 0;
71
72 env->rampD = 0;
73 env->rampX = 0;
74 env->rampY = 0;
75 env->rampZ = 0;
76 env->eind = 0;
77 env->sp = 0;
78
79 env->skip = 0;
80
81 memset(env->r, 0, sizeof(env->r));
82}
83
84static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
85{
86 info->mach = bfd_arch_avr;
87 info->print_insn = avr_print_insn;
88}
89
90static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
91{
92 CPUState *cs = CPU(dev);
93 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
94 Error *local_err = NULL;
95
96 cpu_exec_realizefn(cs, &local_err);
97 if (local_err != NULL) {
98 error_propagate(errp, local_err);
99 return;
100 }
101 qemu_init_vcpu(cs);
102 cpu_reset(cs);
103
104 mcc->parent_realize(dev, errp);
105}
106
107static void avr_cpu_set_int(void *opaque, int irq, int level)
108{
109 AVRCPU *cpu = opaque;
110 CPUAVRState *env = &cpu->env;
111 CPUState *cs = CPU(cpu);
112 uint64_t mask = (1ull << irq);
113
114 if (level) {
115 env->intsrc |= mask;
116 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
117 } else {
118 env->intsrc &= ~mask;
119 if (env->intsrc == 0) {
120 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
121 }
122 }
123}
124
125static void avr_cpu_initfn(Object *obj)
126{
127 AVRCPU *cpu = AVR_CPU(obj);
128
129 cpu_set_cpustate_pointers(cpu);
130
131
132 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
133 sizeof(cpu->env.intsrc) * 8);
134}
135
136static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
137{
138 ObjectClass *oc;
139
140 oc = object_class_by_name(cpu_model);
141 if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
142 object_class_is_abstract(oc)) {
143 oc = NULL;
144 }
145 return oc;
146}
147
148static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
149{
150 AVRCPU *cpu = AVR_CPU(cs);
151 CPUAVRState *env = &cpu->env;
152 int i;
153
154 qemu_fprintf(f, "\n");
155 qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2);
156 qemu_fprintf(f, "SP: %04x\n", env->sp);
157 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16);
158 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16);
159 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16);
160 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16);
161 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16);
162 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]);
163 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]);
164 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]);
165 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n",
166 env->sregI ? 'I' : '-',
167 env->sregT ? 'T' : '-',
168 env->sregH ? 'H' : '-',
169 env->sregS ? 'S' : '-',
170 env->sregV ? 'V' : '-',
171 env->sregN ? '-' : 'N',
172 env->sregZ ? 'Z' : '-',
173 env->sregC ? 'I' : '-');
174 qemu_fprintf(f, "SKIP: %02x\n", env->skip);
175
176 qemu_fprintf(f, "\n");
177 for (i = 0; i < ARRAY_SIZE(env->r); i++) {
178 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]);
179
180 if ((i % 8) == 7) {
181 qemu_fprintf(f, "\n");
182 }
183 }
184 qemu_fprintf(f, "\n");
185}
186
187#include "hw/core/tcg-cpu-ops.h"
188
189static struct TCGCPUOps avr_tcg_ops = {
190 .initialize = avr_cpu_tcg_init,
191 .synchronize_from_tb = avr_cpu_synchronize_from_tb,
192 .cpu_exec_interrupt = avr_cpu_exec_interrupt,
193 .tlb_fill = avr_cpu_tlb_fill,
194
195#ifndef CONFIG_USER_ONLY
196 .do_interrupt = avr_cpu_do_interrupt,
197#endif
198};
199
200static void avr_cpu_class_init(ObjectClass *oc, void *data)
201{
202 DeviceClass *dc = DEVICE_CLASS(oc);
203 CPUClass *cc = CPU_CLASS(oc);
204 AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
205
206 device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
207 device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
208
209 cc->class_by_name = avr_cpu_class_by_name;
210
211 cc->has_work = avr_cpu_has_work;
212 cc->dump_state = avr_cpu_dump_state;
213 cc->set_pc = avr_cpu_set_pc;
214 cc->memory_rw_debug = avr_cpu_memory_rw_debug;
215 cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
216 cc->vmsd = &vms_avr_cpu;
217 cc->disas_set_info = avr_cpu_disas_set_info;
218 cc->gdb_read_register = avr_cpu_gdb_read_register;
219 cc->gdb_write_register = avr_cpu_gdb_write_register;
220 cc->gdb_num_core_regs = 35;
221 cc->gdb_core_xml_file = "avr-cpu.xml";
222 cc->tcg_ops = &avr_tcg_ops;
223}
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249static void avr_avr5_initfn(Object *obj)
250{
251 AVRCPU *cpu = AVR_CPU(obj);
252 CPUAVRState *env = &cpu->env;
253
254 set_avr_feature(env, AVR_FEATURE_LPM);
255 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
256 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
257 set_avr_feature(env, AVR_FEATURE_SRAM);
258 set_avr_feature(env, AVR_FEATURE_BREAK);
259
260 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
261 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
262 set_avr_feature(env, AVR_FEATURE_JMP_CALL);
263 set_avr_feature(env, AVR_FEATURE_LPMX);
264 set_avr_feature(env, AVR_FEATURE_MOVW);
265 set_avr_feature(env, AVR_FEATURE_MUL);
266}
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278static void avr_avr51_initfn(Object *obj)
279{
280 AVRCPU *cpu = AVR_CPU(obj);
281 CPUAVRState *env = &cpu->env;
282
283 set_avr_feature(env, AVR_FEATURE_LPM);
284 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
285 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
286 set_avr_feature(env, AVR_FEATURE_SRAM);
287 set_avr_feature(env, AVR_FEATURE_BREAK);
288
289 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
290 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
291 set_avr_feature(env, AVR_FEATURE_RAMPZ);
292 set_avr_feature(env, AVR_FEATURE_ELPMX);
293 set_avr_feature(env, AVR_FEATURE_ELPM);
294 set_avr_feature(env, AVR_FEATURE_JMP_CALL);
295 set_avr_feature(env, AVR_FEATURE_LPMX);
296 set_avr_feature(env, AVR_FEATURE_MOVW);
297 set_avr_feature(env, AVR_FEATURE_MUL);
298}
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307
308static void avr_avr6_initfn(Object *obj)
309{
310 AVRCPU *cpu = AVR_CPU(obj);
311 CPUAVRState *env = &cpu->env;
312
313 set_avr_feature(env, AVR_FEATURE_LPM);
314 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
315 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
316 set_avr_feature(env, AVR_FEATURE_SRAM);
317 set_avr_feature(env, AVR_FEATURE_BREAK);
318
319 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC);
320 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
321 set_avr_feature(env, AVR_FEATURE_RAMPZ);
322 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL);
323 set_avr_feature(env, AVR_FEATURE_ELPMX);
324 set_avr_feature(env, AVR_FEATURE_ELPM);
325 set_avr_feature(env, AVR_FEATURE_JMP_CALL);
326 set_avr_feature(env, AVR_FEATURE_LPMX);
327 set_avr_feature(env, AVR_FEATURE_MOVW);
328 set_avr_feature(env, AVR_FEATURE_MUL);
329}
330
331typedef struct AVRCPUInfo {
332 const char *name;
333 void (*initfn)(Object *obj);
334} AVRCPUInfo;
335
336
337static void avr_cpu_list_entry(gpointer data, gpointer user_data)
338{
339 const char *typename = object_class_get_name(OBJECT_CLASS(data));
340
341 qemu_printf("%s\n", typename);
342}
343
344void avr_cpu_list(void)
345{
346 GSList *list;
347 list = object_class_get_list_sorted(TYPE_AVR_CPU, false);
348 g_slist_foreach(list, avr_cpu_list_entry, NULL);
349 g_slist_free(list);
350}
351
352#define DEFINE_AVR_CPU_TYPE(model, initfn) \
353 { \
354 .parent = TYPE_AVR_CPU, \
355 .instance_init = initfn, \
356 .name = AVR_CPU_TYPE_NAME(model), \
357 }
358
359static const TypeInfo avr_cpu_type_info[] = {
360 {
361 .name = TYPE_AVR_CPU,
362 .parent = TYPE_CPU,
363 .instance_size = sizeof(AVRCPU),
364 .instance_init = avr_cpu_initfn,
365 .class_size = sizeof(AVRCPUClass),
366 .class_init = avr_cpu_class_init,
367 .abstract = true,
368 },
369 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
370 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
371 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
372};
373
374DEFINE_TYPES(avr_cpu_type_info)
375