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21#include "qemu/osdep.h"
22#include "cpu.h"
23#include "hw/core/tcg-cpu-ops.h"
24#include "mmu.h"
25#include "qemu/host-utils.h"
26#include "exec/exec-all.h"
27#include "exec/cpu_ldst.h"
28#include "exec/helper-proto.h"
29
30
31
32
33
34#ifdef CRIS_HELPER_DEBUG
35#define D(x) x
36#define D_LOG(...) qemu_log(__VA_ARGS__)
37#else
38#define D(x)
39#define D_LOG(...) do { } while (0)
40#endif
41
42#if defined(CONFIG_USER_ONLY)
43
44void cris_cpu_do_interrupt(CPUState *cs)
45{
46 CRISCPU *cpu = CRIS_CPU(cs);
47 CPUCRISState *env = &cpu->env;
48
49 cs->exception_index = -1;
50 env->pregs[PR_ERP] = env->pc;
51}
52
53void crisv10_cpu_do_interrupt(CPUState *cs)
54{
55 cris_cpu_do_interrupt(cs);
56}
57
58bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
59 MMUAccessType access_type, int mmu_idx,
60 bool probe, uintptr_t retaddr)
61{
62 CRISCPU *cpu = CRIS_CPU(cs);
63
64 cs->exception_index = 0xaa;
65 cpu->env.pregs[PR_EDA] = address;
66 cpu_loop_exit_restore(cs, retaddr);
67}
68
69#else
70
71
72static void cris_shift_ccs(CPUCRISState *env)
73{
74 uint32_t ccs;
75
76 ccs = env->pregs[PR_CCS];
77 ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
78 env->pregs[PR_CCS] = ccs;
79}
80
81bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
82 MMUAccessType access_type, int mmu_idx,
83 bool probe, uintptr_t retaddr)
84{
85 CRISCPU *cpu = CRIS_CPU(cs);
86 CPUCRISState *env = &cpu->env;
87 struct cris_mmu_result res;
88 int prot, miss;
89 target_ulong phy;
90
91 miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
92 access_type, mmu_idx, 0);
93 if (likely(!miss)) {
94
95
96
97
98 phy = res.phy & ~0x80000000;
99 prot = res.prot;
100 tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
101 prot, mmu_idx, TARGET_PAGE_SIZE);
102 return true;
103 }
104
105 if (probe) {
106 return false;
107 }
108
109 if (cs->exception_index == EXCP_BUSFAULT) {
110 cpu_abort(cs, "CRIS: Illegal recursive bus fault."
111 "addr=%" VADDR_PRIx " access_type=%d\n",
112 address, access_type);
113 }
114
115 env->pregs[PR_EDA] = address;
116 cs->exception_index = EXCP_BUSFAULT;
117 env->fault_vector = res.bf_vec;
118 if (retaddr) {
119 if (cpu_restore_state(cs, retaddr, true)) {
120
121 helper_top_evaluate_flags(env);
122 }
123 }
124 cpu_loop_exit(cs);
125}
126
127void crisv10_cpu_do_interrupt(CPUState *cs)
128{
129 CRISCPU *cpu = CRIS_CPU(cs);
130 CPUCRISState *env = &cpu->env;
131 int ex_vec = -1;
132
133 D_LOG("exception index=%d interrupt_req=%d\n",
134 cs->exception_index,
135 cs->interrupt_request);
136
137 if (env->dslot) {
138
139 cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
140 }
141
142 assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
143 switch (cs->exception_index) {
144 case EXCP_BREAK:
145
146
147 ex_vec = env->trap_vector;
148 env->pregs[PRV10_BRP] = env->pc;
149 break;
150
151 case EXCP_NMI:
152
153 ex_vec = 0;
154 env->pregs[PR_CCS] &= ~M_FLAG_V10;
155 env->pregs[PRV10_BRP] = env->pc;
156 break;
157
158 case EXCP_BUSFAULT:
159 cpu_abort(cs, "Unhandled busfault");
160 break;
161
162 default:
163
164 ex_vec = env->interrupt_vector;
165
166
167 env->pregs[PR_ERP] = env->pc;
168 break;
169 }
170
171 if (env->pregs[PR_CCS] & U_FLAG) {
172
173 env->pregs[PR_USP] = env->regs[R_SP];
174 env->regs[R_SP] = env->ksp;
175 }
176
177
178 env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
179 env->locked_irq = 1;
180 env->pregs[PR_CCS] |= F_FLAG_V10;
181
182 qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
183 __func__, env->pc, ex_vec,
184 env->pregs[PR_CCS],
185 env->pregs[PR_PID],
186 env->pregs[PR_ERP]);
187}
188
189void cris_cpu_do_interrupt(CPUState *cs)
190{
191 CRISCPU *cpu = CRIS_CPU(cs);
192 CPUCRISState *env = &cpu->env;
193 int ex_vec = -1;
194
195 D_LOG("exception index=%d interrupt_req=%d\n",
196 cs->exception_index,
197 cs->interrupt_request);
198
199 switch (cs->exception_index) {
200 case EXCP_BREAK:
201
202
203 ex_vec = env->trap_vector;
204 env->pregs[PR_ERP] = env->pc;
205 break;
206
207 case EXCP_NMI:
208
209 ex_vec = 0;
210 env->pregs[PR_CCS] &= ~M_FLAG_V32;
211 env->pregs[PR_NRP] = env->pc;
212 break;
213
214 case EXCP_BUSFAULT:
215 ex_vec = env->fault_vector;
216 env->pregs[PR_ERP] = env->pc;
217 break;
218
219 default:
220
221 ex_vec = env->interrupt_vector;
222
223
224 env->pregs[PR_ERP] = env->pc;
225 break;
226 }
227
228
229 env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
230
231 if (env->dslot) {
232 D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
233 " ERP=%x pid=%x ccs=%x cc=%d %x\n",
234 ex_vec, env->pc, env->dslot,
235 env->regs[R_SP],
236 env->pregs[PR_ERP], env->pregs[PR_PID],
237 env->pregs[PR_CCS],
238 env->cc_op, env->cc_mask);
239
240
241 env->pregs[PR_ERP] -= env->dslot;
242
243 env->dslot = 0;
244 }
245
246 if (env->pregs[PR_CCS] & U_FLAG) {
247
248 env->pregs[PR_USP] = env->regs[R_SP];
249 env->regs[R_SP] = env->ksp;
250 }
251
252
253 cris_shift_ccs(env);
254
255
256
257
258 env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
259
260
261
262 cs->exception_index = -1;
263
264 D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
265 __func__, env->pc, ex_vec,
266 env->pregs[PR_CCS],
267 env->pregs[PR_PID],
268 env->pregs[PR_ERP]);
269}
270
271hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
272{
273 CRISCPU *cpu = CRIS_CPU(cs);
274 uint32_t phy = addr;
275 struct cris_mmu_result res;
276 int miss;
277
278 miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_DATA_LOAD, 0, 1);
279
280 if (miss) {
281 miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_INST_FETCH, 0, 1);
282 }
283
284 if (!miss) {
285 phy = res.phy;
286 }
287 D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
288 return phy;
289}
290#endif
291
292bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
293{
294 CPUClass *cc = CPU_GET_CLASS(cs);
295 CRISCPU *cpu = CRIS_CPU(cs);
296 CPUCRISState *env = &cpu->env;
297 bool ret = false;
298
299 if (interrupt_request & CPU_INTERRUPT_HARD
300 && (env->pregs[PR_CCS] & I_FLAG)
301 && !env->locked_irq) {
302 cs->exception_index = EXCP_IRQ;
303 cc->tcg_ops->do_interrupt(cs);
304 ret = true;
305 }
306 if (interrupt_request & CPU_INTERRUPT_NMI) {
307 unsigned int m_flag_archval;
308 if (env->pregs[PR_VR] < 32) {
309 m_flag_archval = M_FLAG_V10;
310 } else {
311 m_flag_archval = M_FLAG_V32;
312 }
313 if ((env->pregs[PR_CCS] & m_flag_archval)) {
314 cs->exception_index = EXCP_NMI;
315 cc->tcg_ops->do_interrupt(cs);
316 ret = true;
317 }
318 }
319
320 return ret;
321}
322