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20#ifndef I386_CPU_H
21#define I386_CPU_H
22
23#include "sysemu/tcg.h"
24#include "cpu-qom.h"
25#include "kvm/hyperv-proto.h"
26#include "exec/cpu-defs.h"
27#include "qapi/qapi-types-common.h"
28
29
30#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
31
32#define KVM_HAVE_MCE_INJECTION 1
33
34
35
36#define TARGET_HAS_PRECISE_SMC
37
38#ifdef TARGET_X86_64
39#define I386_ELF_MACHINE EM_X86_64
40#define ELF_MACHINE_UNAME "x86_64"
41#else
42#define I386_ELF_MACHINE EM_386
43#define ELF_MACHINE_UNAME "i686"
44#endif
45
46enum {
47 R_EAX = 0,
48 R_ECX = 1,
49 R_EDX = 2,
50 R_EBX = 3,
51 R_ESP = 4,
52 R_EBP = 5,
53 R_ESI = 6,
54 R_EDI = 7,
55 R_R8 = 8,
56 R_R9 = 9,
57 R_R10 = 10,
58 R_R11 = 11,
59 R_R12 = 12,
60 R_R13 = 13,
61 R_R14 = 14,
62 R_R15 = 15,
63
64 R_AL = 0,
65 R_CL = 1,
66 R_DL = 2,
67 R_BL = 3,
68 R_AH = 4,
69 R_CH = 5,
70 R_DH = 6,
71 R_BH = 7,
72};
73
74typedef enum X86Seg {
75 R_ES = 0,
76 R_CS = 1,
77 R_SS = 2,
78 R_DS = 3,
79 R_FS = 4,
80 R_GS = 5,
81 R_LDTR = 6,
82 R_TR = 7,
83} X86Seg;
84
85
86#define DESC_G_SHIFT 23
87#define DESC_G_MASK (1 << DESC_G_SHIFT)
88#define DESC_B_SHIFT 22
89#define DESC_B_MASK (1 << DESC_B_SHIFT)
90#define DESC_L_SHIFT 21
91#define DESC_L_MASK (1 << DESC_L_SHIFT)
92#define DESC_AVL_SHIFT 20
93#define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
94#define DESC_P_SHIFT 15
95#define DESC_P_MASK (1 << DESC_P_SHIFT)
96#define DESC_DPL_SHIFT 13
97#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
98#define DESC_S_SHIFT 12
99#define DESC_S_MASK (1 << DESC_S_SHIFT)
100#define DESC_TYPE_SHIFT 8
101#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
102#define DESC_A_MASK (1 << 8)
103
104#define DESC_CS_MASK (1 << 11)
105#define DESC_C_MASK (1 << 10)
106#define DESC_R_MASK (1 << 9)
107
108#define DESC_E_MASK (1 << 10)
109#define DESC_W_MASK (1 << 9)
110
111#define DESC_TSS_BUSY_MASK (1 << 9)
112
113
114#define CC_C 0x0001
115#define CC_P 0x0004
116#define CC_A 0x0010
117#define CC_Z 0x0040
118#define CC_S 0x0080
119#define CC_O 0x0800
120
121#define TF_SHIFT 8
122#define IOPL_SHIFT 12
123#define VM_SHIFT 17
124
125#define TF_MASK 0x00000100
126#define IF_MASK 0x00000200
127#define DF_MASK 0x00000400
128#define IOPL_MASK 0x00003000
129#define NT_MASK 0x00004000
130#define RF_MASK 0x00010000
131#define VM_MASK 0x00020000
132#define AC_MASK 0x00040000
133#define VIF_MASK 0x00080000
134#define VIP_MASK 0x00100000
135#define ID_MASK 0x00200000
136
137
138
139
140
141
142#define HF_CPL_SHIFT 0
143
144#define HF_INHIBIT_IRQ_SHIFT 3
145
146#define HF_CS32_SHIFT 4
147#define HF_SS32_SHIFT 5
148
149#define HF_ADDSEG_SHIFT 6
150
151#define HF_PE_SHIFT 7
152#define HF_TF_SHIFT 8
153#define HF_MP_SHIFT 9
154#define HF_EM_SHIFT 10
155#define HF_TS_SHIFT 11
156#define HF_IOPL_SHIFT 12
157#define HF_LMA_SHIFT 14
158#define HF_CS64_SHIFT 15
159#define HF_RF_SHIFT 16
160#define HF_VM_SHIFT 17
161#define HF_AC_SHIFT 18
162#define HF_SMM_SHIFT 19
163#define HF_SVME_SHIFT 20
164#define HF_GUEST_SHIFT 21
165#define HF_OSFXSR_SHIFT 22
166#define HF_SMAP_SHIFT 23
167#define HF_IOBPT_SHIFT 24
168#define HF_MPX_EN_SHIFT 25
169#define HF_MPX_IU_SHIFT 26
170
171#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
172#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
173#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
174#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
175#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
176#define HF_PE_MASK (1 << HF_PE_SHIFT)
177#define HF_TF_MASK (1 << HF_TF_SHIFT)
178#define HF_MP_MASK (1 << HF_MP_SHIFT)
179#define HF_EM_MASK (1 << HF_EM_SHIFT)
180#define HF_TS_MASK (1 << HF_TS_SHIFT)
181#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
182#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
183#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
184#define HF_RF_MASK (1 << HF_RF_SHIFT)
185#define HF_VM_MASK (1 << HF_VM_SHIFT)
186#define HF_AC_MASK (1 << HF_AC_SHIFT)
187#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
188#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
189#define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
190#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
191#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
192#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
193#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
194#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
195
196
197
198#define HF2_GIF_SHIFT 0
199#define HF2_HIF_SHIFT 1
200#define HF2_NMI_SHIFT 2
201#define HF2_VINTR_SHIFT 3
202#define HF2_SMM_INSIDE_NMI_SHIFT 4
203#define HF2_MPX_PR_SHIFT 5
204#define HF2_NPT_SHIFT 6
205#define HF2_IGNNE_SHIFT 7
206
207#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
208#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
209#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
210#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
211#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
212#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
213#define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
214#define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
215
216#define CR0_PE_SHIFT 0
217#define CR0_MP_SHIFT 1
218
219#define CR0_PE_MASK (1U << 0)
220#define CR0_MP_MASK (1U << 1)
221#define CR0_EM_MASK (1U << 2)
222#define CR0_TS_MASK (1U << 3)
223#define CR0_ET_MASK (1U << 4)
224#define CR0_NE_MASK (1U << 5)
225#define CR0_WP_MASK (1U << 16)
226#define CR0_AM_MASK (1U << 18)
227#define CR0_PG_MASK (1U << 31)
228
229#define CR4_VME_MASK (1U << 0)
230#define CR4_PVI_MASK (1U << 1)
231#define CR4_TSD_MASK (1U << 2)
232#define CR4_DE_MASK (1U << 3)
233#define CR4_PSE_MASK (1U << 4)
234#define CR4_PAE_MASK (1U << 5)
235#define CR4_MCE_MASK (1U << 6)
236#define CR4_PGE_MASK (1U << 7)
237#define CR4_PCE_MASK (1U << 8)
238#define CR4_OSFXSR_SHIFT 9
239#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
240#define CR4_OSXMMEXCPT_MASK (1U << 10)
241#define CR4_LA57_MASK (1U << 12)
242#define CR4_VMXE_MASK (1U << 13)
243#define CR4_SMXE_MASK (1U << 14)
244#define CR4_FSGSBASE_MASK (1U << 16)
245#define CR4_PCIDE_MASK (1U << 17)
246#define CR4_OSXSAVE_MASK (1U << 18)
247#define CR4_SMEP_MASK (1U << 20)
248#define CR4_SMAP_MASK (1U << 21)
249#define CR4_PKE_MASK (1U << 22)
250#define CR4_PKS_MASK (1U << 24)
251
252#define DR6_BD (1 << 13)
253#define DR6_BS (1 << 14)
254#define DR6_BT (1 << 15)
255#define DR6_FIXED_1 0xffff0ff0
256
257#define DR7_GD (1 << 13)
258#define DR7_TYPE_SHIFT 16
259#define DR7_LEN_SHIFT 18
260#define DR7_FIXED_1 0x00000400
261#define DR7_GLOBAL_BP_MASK 0xaa
262#define DR7_LOCAL_BP_MASK 0x55
263#define DR7_MAX_BP 4
264#define DR7_TYPE_BP_INST 0x0
265#define DR7_TYPE_DATA_WR 0x1
266#define DR7_TYPE_IO_RW 0x2
267#define DR7_TYPE_DATA_RW 0x3
268
269#define PG_PRESENT_BIT 0
270#define PG_RW_BIT 1
271#define PG_USER_BIT 2
272#define PG_PWT_BIT 3
273#define PG_PCD_BIT 4
274#define PG_ACCESSED_BIT 5
275#define PG_DIRTY_BIT 6
276#define PG_PSE_BIT 7
277#define PG_GLOBAL_BIT 8
278#define PG_PSE_PAT_BIT 12
279#define PG_PKRU_BIT 59
280#define PG_NX_BIT 63
281
282#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
283#define PG_RW_MASK (1 << PG_RW_BIT)
284#define PG_USER_MASK (1 << PG_USER_BIT)
285#define PG_PWT_MASK (1 << PG_PWT_BIT)
286#define PG_PCD_MASK (1 << PG_PCD_BIT)
287#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
288#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
289#define PG_PSE_MASK (1 << PG_PSE_BIT)
290#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
291#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
292#define PG_ADDRESS_MASK 0x000ffffffffff000LL
293#define PG_HI_USER_MASK 0x7ff0000000000000LL
294#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
295#define PG_NX_MASK (1ULL << PG_NX_BIT)
296
297#define PG_ERROR_W_BIT 1
298
299#define PG_ERROR_P_MASK 0x01
300#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
301#define PG_ERROR_U_MASK 0x04
302#define PG_ERROR_RSVD_MASK 0x08
303#define PG_ERROR_I_D_MASK 0x10
304#define PG_ERROR_PK_MASK 0x20
305
306#define MCG_CTL_P (1ULL<<8)
307#define MCG_SER_P (1ULL<<24)
308#define MCG_LMCE_P (1ULL<<27)
309
310#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
311#define MCE_BANKS_DEF 10
312
313#define MCG_CAP_BANKS_MASK 0xff
314
315#define MCG_STATUS_RIPV (1ULL<<0)
316#define MCG_STATUS_EIPV (1ULL<<1)
317#define MCG_STATUS_MCIP (1ULL<<2)
318#define MCG_STATUS_LMCE (1ULL<<3)
319
320#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
321
322#define MCI_STATUS_VAL (1ULL<<63)
323#define MCI_STATUS_OVER (1ULL<<62)
324#define MCI_STATUS_UC (1ULL<<61)
325#define MCI_STATUS_EN (1ULL<<60)
326#define MCI_STATUS_MISCV (1ULL<<59)
327#define MCI_STATUS_ADDRV (1ULL<<58)
328#define MCI_STATUS_PCC (1ULL<<57)
329#define MCI_STATUS_S (1ULL<<56)
330#define MCI_STATUS_AR (1ULL<<55)
331
332
333#define MCM_ADDR_SEGOFF 0
334#define MCM_ADDR_LINEAR 1
335#define MCM_ADDR_PHYS 2
336#define MCM_ADDR_MEM 3
337#define MCM_ADDR_GENERIC 7
338
339#define MSR_IA32_TSC 0x10
340#define MSR_IA32_APICBASE 0x1b
341#define MSR_IA32_APICBASE_BSP (1<<8)
342#define MSR_IA32_APICBASE_ENABLE (1<<11)
343#define MSR_IA32_APICBASE_EXTD (1 << 10)
344#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
345#define MSR_IA32_FEATURE_CONTROL 0x0000003a
346#define MSR_TSC_ADJUST 0x0000003b
347#define MSR_IA32_SPEC_CTRL 0x48
348#define MSR_VIRT_SSBD 0xc001011f
349#define MSR_IA32_PRED_CMD 0x49
350#define MSR_IA32_UCODE_REV 0x8b
351#define MSR_IA32_CORE_CAPABILITY 0xcf
352
353#define MSR_IA32_ARCH_CAPABILITIES 0x10a
354#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
355
356#define MSR_IA32_PERF_CAPABILITIES 0x345
357
358#define MSR_IA32_TSX_CTRL 0x122
359#define MSR_IA32_TSCDEADLINE 0x6e0
360#define MSR_IA32_PKRS 0x6e1
361
362#define FEATURE_CONTROL_LOCKED (1<<0)
363#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
364#define FEATURE_CONTROL_LMCE (1<<20)
365
366#define MSR_P6_PERFCTR0 0xc1
367
368#define MSR_IA32_SMBASE 0x9e
369#define MSR_SMI_COUNT 0x34
370#define MSR_CORE_THREAD_COUNT 0x35
371#define MSR_MTRRcap 0xfe
372#define MSR_MTRRcap_VCNT 8
373#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
374#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
375
376#define MSR_IA32_SYSENTER_CS 0x174
377#define MSR_IA32_SYSENTER_ESP 0x175
378#define MSR_IA32_SYSENTER_EIP 0x176
379
380#define MSR_MCG_CAP 0x179
381#define MSR_MCG_STATUS 0x17a
382#define MSR_MCG_CTL 0x17b
383#define MSR_MCG_EXT_CTL 0x4d0
384
385#define MSR_P6_EVNTSEL0 0x186
386
387#define MSR_IA32_PERF_STATUS 0x198
388
389#define MSR_IA32_MISC_ENABLE 0x1a0
390
391#define MSR_IA32_MISC_ENABLE_DEFAULT 1
392#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
393
394#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
395#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
396
397#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
398
399#define MSR_MTRRfix64K_00000 0x250
400#define MSR_MTRRfix16K_80000 0x258
401#define MSR_MTRRfix16K_A0000 0x259
402#define MSR_MTRRfix4K_C0000 0x268
403#define MSR_MTRRfix4K_C8000 0x269
404#define MSR_MTRRfix4K_D0000 0x26a
405#define MSR_MTRRfix4K_D8000 0x26b
406#define MSR_MTRRfix4K_E0000 0x26c
407#define MSR_MTRRfix4K_E8000 0x26d
408#define MSR_MTRRfix4K_F0000 0x26e
409#define MSR_MTRRfix4K_F8000 0x26f
410
411#define MSR_PAT 0x277
412
413#define MSR_MTRRdefType 0x2ff
414
415#define MSR_CORE_PERF_FIXED_CTR0 0x309
416#define MSR_CORE_PERF_FIXED_CTR1 0x30a
417#define MSR_CORE_PERF_FIXED_CTR2 0x30b
418#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
419#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
420#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
421#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
422
423#define MSR_MC0_CTL 0x400
424#define MSR_MC0_STATUS 0x401
425#define MSR_MC0_ADDR 0x402
426#define MSR_MC0_MISC 0x403
427
428#define MSR_IA32_RTIT_OUTPUT_BASE 0x560
429#define MSR_IA32_RTIT_OUTPUT_MASK 0x561
430#define MSR_IA32_RTIT_CTL 0x570
431#define MSR_IA32_RTIT_STATUS 0x571
432#define MSR_IA32_RTIT_CR3_MATCH 0x572
433#define MSR_IA32_RTIT_ADDR0_A 0x580
434#define MSR_IA32_RTIT_ADDR0_B 0x581
435#define MSR_IA32_RTIT_ADDR1_A 0x582
436#define MSR_IA32_RTIT_ADDR1_B 0x583
437#define MSR_IA32_RTIT_ADDR2_A 0x584
438#define MSR_IA32_RTIT_ADDR2_B 0x585
439#define MSR_IA32_RTIT_ADDR3_A 0x586
440#define MSR_IA32_RTIT_ADDR3_B 0x587
441#define MAX_RTIT_ADDRS 8
442
443#define MSR_EFER 0xc0000080
444
445#define MSR_EFER_SCE (1 << 0)
446#define MSR_EFER_LME (1 << 8)
447#define MSR_EFER_LMA (1 << 10)
448#define MSR_EFER_NXE (1 << 11)
449#define MSR_EFER_SVME (1 << 12)
450#define MSR_EFER_FFXSR (1 << 14)
451
452#define MSR_STAR 0xc0000081
453#define MSR_LSTAR 0xc0000082
454#define MSR_CSTAR 0xc0000083
455#define MSR_FMASK 0xc0000084
456#define MSR_FSBASE 0xc0000100
457#define MSR_GSBASE 0xc0000101
458#define MSR_KERNELGSBASE 0xc0000102
459#define MSR_TSC_AUX 0xc0000103
460
461#define MSR_VM_HSAVE_PA 0xc0010117
462
463#define MSR_IA32_BNDCFGS 0x00000d90
464#define MSR_IA32_XSS 0x00000da0
465#define MSR_IA32_UMWAIT_CONTROL 0xe1
466
467#define MSR_IA32_VMX_BASIC 0x00000480
468#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
469#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
470#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
471#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
472#define MSR_IA32_VMX_MISC 0x00000485
473#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
474#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
475#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
476#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
477#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
478#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
479#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
480#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
481#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
482#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
483#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
484#define MSR_IA32_VMX_VMFUNC 0x00000491
485
486#define XSTATE_FP_BIT 0
487#define XSTATE_SSE_BIT 1
488#define XSTATE_YMM_BIT 2
489#define XSTATE_BNDREGS_BIT 3
490#define XSTATE_BNDCSR_BIT 4
491#define XSTATE_OPMASK_BIT 5
492#define XSTATE_ZMM_Hi256_BIT 6
493#define XSTATE_Hi16_ZMM_BIT 7
494#define XSTATE_PKRU_BIT 9
495
496#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
497#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
498#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
499#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
500#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
501#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
502#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
503#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
504#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
505
506
507typedef enum FeatureWord {
508 FEAT_1_EDX,
509 FEAT_1_ECX,
510 FEAT_7_0_EBX,
511 FEAT_7_0_ECX,
512 FEAT_7_0_EDX,
513 FEAT_7_1_EAX,
514 FEAT_8000_0001_EDX,
515 FEAT_8000_0001_ECX,
516 FEAT_8000_0007_EDX,
517 FEAT_8000_0008_EBX,
518 FEAT_C000_0001_EDX,
519 FEAT_KVM,
520 FEAT_KVM_HINTS,
521 FEAT_HYPERV_EAX,
522 FEAT_HYPERV_EBX,
523 FEAT_HYPERV_EDX,
524 FEAT_HV_RECOMM_EAX,
525 FEAT_HV_NESTED_EAX,
526 FEAT_SVM,
527 FEAT_XSAVE,
528 FEAT_6_EAX,
529 FEAT_XSAVE_COMP_LO,
530 FEAT_XSAVE_COMP_HI,
531 FEAT_ARCH_CAPABILITIES,
532 FEAT_CORE_CAPABILITY,
533 FEAT_PERF_CAPABILITIES,
534 FEAT_VMX_PROCBASED_CTLS,
535 FEAT_VMX_SECONDARY_CTLS,
536 FEAT_VMX_PINBASED_CTLS,
537 FEAT_VMX_EXIT_CTLS,
538 FEAT_VMX_ENTRY_CTLS,
539 FEAT_VMX_MISC,
540 FEAT_VMX_EPT_VPID_CAPS,
541 FEAT_VMX_BASIC,
542 FEAT_VMX_VMFUNC,
543 FEAT_14_0_ECX,
544 FEATURE_WORDS,
545} FeatureWord;
546
547typedef uint64_t FeatureWordArray[FEATURE_WORDS];
548
549
550#define CPUID_FP87 (1U << 0)
551#define CPUID_VME (1U << 1)
552#define CPUID_DE (1U << 2)
553#define CPUID_PSE (1U << 3)
554#define CPUID_TSC (1U << 4)
555#define CPUID_MSR (1U << 5)
556#define CPUID_PAE (1U << 6)
557#define CPUID_MCE (1U << 7)
558#define CPUID_CX8 (1U << 8)
559#define CPUID_APIC (1U << 9)
560#define CPUID_SEP (1U << 11)
561#define CPUID_MTRR (1U << 12)
562#define CPUID_PGE (1U << 13)
563#define CPUID_MCA (1U << 14)
564#define CPUID_CMOV (1U << 15)
565#define CPUID_PAT (1U << 16)
566#define CPUID_PSE36 (1U << 17)
567#define CPUID_PN (1U << 18)
568#define CPUID_CLFLUSH (1U << 19)
569#define CPUID_DTS (1U << 21)
570#define CPUID_ACPI (1U << 22)
571#define CPUID_MMX (1U << 23)
572#define CPUID_FXSR (1U << 24)
573#define CPUID_SSE (1U << 25)
574#define CPUID_SSE2 (1U << 26)
575#define CPUID_SS (1U << 27)
576#define CPUID_HT (1U << 28)
577#define CPUID_TM (1U << 29)
578#define CPUID_IA64 (1U << 30)
579#define CPUID_PBE (1U << 31)
580
581#define CPUID_EXT_SSE3 (1U << 0)
582#define CPUID_EXT_PCLMULQDQ (1U << 1)
583#define CPUID_EXT_DTES64 (1U << 2)
584#define CPUID_EXT_MONITOR (1U << 3)
585#define CPUID_EXT_DSCPL (1U << 4)
586#define CPUID_EXT_VMX (1U << 5)
587#define CPUID_EXT_SMX (1U << 6)
588#define CPUID_EXT_EST (1U << 7)
589#define CPUID_EXT_TM2 (1U << 8)
590#define CPUID_EXT_SSSE3 (1U << 9)
591#define CPUID_EXT_CID (1U << 10)
592#define CPUID_EXT_FMA (1U << 12)
593#define CPUID_EXT_CX16 (1U << 13)
594#define CPUID_EXT_XTPR (1U << 14)
595#define CPUID_EXT_PDCM (1U << 15)
596#define CPUID_EXT_PCID (1U << 17)
597#define CPUID_EXT_DCA (1U << 18)
598#define CPUID_EXT_SSE41 (1U << 19)
599#define CPUID_EXT_SSE42 (1U << 20)
600#define CPUID_EXT_X2APIC (1U << 21)
601#define CPUID_EXT_MOVBE (1U << 22)
602#define CPUID_EXT_POPCNT (1U << 23)
603#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
604#define CPUID_EXT_AES (1U << 25)
605#define CPUID_EXT_XSAVE (1U << 26)
606#define CPUID_EXT_OSXSAVE (1U << 27)
607#define CPUID_EXT_AVX (1U << 28)
608#define CPUID_EXT_F16C (1U << 29)
609#define CPUID_EXT_RDRAND (1U << 30)
610#define CPUID_EXT_HYPERVISOR (1U << 31)
611
612#define CPUID_EXT2_FPU (1U << 0)
613#define CPUID_EXT2_VME (1U << 1)
614#define CPUID_EXT2_DE (1U << 2)
615#define CPUID_EXT2_PSE (1U << 3)
616#define CPUID_EXT2_TSC (1U << 4)
617#define CPUID_EXT2_MSR (1U << 5)
618#define CPUID_EXT2_PAE (1U << 6)
619#define CPUID_EXT2_MCE (1U << 7)
620#define CPUID_EXT2_CX8 (1U << 8)
621#define CPUID_EXT2_APIC (1U << 9)
622#define CPUID_EXT2_SYSCALL (1U << 11)
623#define CPUID_EXT2_MTRR (1U << 12)
624#define CPUID_EXT2_PGE (1U << 13)
625#define CPUID_EXT2_MCA (1U << 14)
626#define CPUID_EXT2_CMOV (1U << 15)
627#define CPUID_EXT2_PAT (1U << 16)
628#define CPUID_EXT2_PSE36 (1U << 17)
629#define CPUID_EXT2_MP (1U << 19)
630#define CPUID_EXT2_NX (1U << 20)
631#define CPUID_EXT2_MMXEXT (1U << 22)
632#define CPUID_EXT2_MMX (1U << 23)
633#define CPUID_EXT2_FXSR (1U << 24)
634#define CPUID_EXT2_FFXSR (1U << 25)
635#define CPUID_EXT2_PDPE1GB (1U << 26)
636#define CPUID_EXT2_RDTSCP (1U << 27)
637#define CPUID_EXT2_LM (1U << 29)
638#define CPUID_EXT2_3DNOWEXT (1U << 30)
639#define CPUID_EXT2_3DNOW (1U << 31)
640
641
642#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
643 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
644 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
645 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
646 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
647 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
648 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
649 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
650 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
651
652#define CPUID_EXT3_LAHF_LM (1U << 0)
653#define CPUID_EXT3_CMP_LEG (1U << 1)
654#define CPUID_EXT3_SVM (1U << 2)
655#define CPUID_EXT3_EXTAPIC (1U << 3)
656#define CPUID_EXT3_CR8LEG (1U << 4)
657#define CPUID_EXT3_ABM (1U << 5)
658#define CPUID_EXT3_SSE4A (1U << 6)
659#define CPUID_EXT3_MISALIGNSSE (1U << 7)
660#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
661#define CPUID_EXT3_OSVW (1U << 9)
662#define CPUID_EXT3_IBS (1U << 10)
663#define CPUID_EXT3_XOP (1U << 11)
664#define CPUID_EXT3_SKINIT (1U << 12)
665#define CPUID_EXT3_WDT (1U << 13)
666#define CPUID_EXT3_LWP (1U << 15)
667#define CPUID_EXT3_FMA4 (1U << 16)
668#define CPUID_EXT3_TCE (1U << 17)
669#define CPUID_EXT3_NODEID (1U << 19)
670#define CPUID_EXT3_TBM (1U << 21)
671#define CPUID_EXT3_TOPOEXT (1U << 22)
672#define CPUID_EXT3_PERFCORE (1U << 23)
673#define CPUID_EXT3_PERFNB (1U << 24)
674
675#define CPUID_SVM_NPT (1U << 0)
676#define CPUID_SVM_LBRV (1U << 1)
677#define CPUID_SVM_SVMLOCK (1U << 2)
678#define CPUID_SVM_NRIPSAVE (1U << 3)
679#define CPUID_SVM_TSCSCALE (1U << 4)
680#define CPUID_SVM_VMCBCLEAN (1U << 5)
681#define CPUID_SVM_FLUSHASID (1U << 6)
682#define CPUID_SVM_DECODEASSIST (1U << 7)
683#define CPUID_SVM_PAUSEFILTER (1U << 10)
684#define CPUID_SVM_PFTHRESHOLD (1U << 12)
685#define CPUID_SVM_AVIC (1U << 13)
686#define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
687#define CPUID_SVM_VGIF (1U << 16)
688#define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
689
690
691#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
692
693#define CPUID_7_0_EBX_BMI1 (1U << 3)
694
695#define CPUID_7_0_EBX_HLE (1U << 4)
696
697#define CPUID_7_0_EBX_AVX2 (1U << 5)
698
699#define CPUID_7_0_EBX_SMEP (1U << 7)
700
701#define CPUID_7_0_EBX_BMI2 (1U << 8)
702
703#define CPUID_7_0_EBX_ERMS (1U << 9)
704
705#define CPUID_7_0_EBX_INVPCID (1U << 10)
706
707#define CPUID_7_0_EBX_RTM (1U << 11)
708
709#define CPUID_7_0_EBX_MPX (1U << 14)
710
711#define CPUID_7_0_EBX_AVX512F (1U << 16)
712
713#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
714
715#define CPUID_7_0_EBX_RDSEED (1U << 18)
716
717#define CPUID_7_0_EBX_ADX (1U << 19)
718
719#define CPUID_7_0_EBX_SMAP (1U << 20)
720
721#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
722
723#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
724
725#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
726
727#define CPUID_7_0_EBX_CLWB (1U << 24)
728
729#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
730
731#define CPUID_7_0_EBX_AVX512PF (1U << 26)
732
733#define CPUID_7_0_EBX_AVX512ER (1U << 27)
734
735#define CPUID_7_0_EBX_AVX512CD (1U << 28)
736
737#define CPUID_7_0_EBX_SHA_NI (1U << 29)
738
739#define CPUID_7_0_EBX_AVX512BW (1U << 30)
740
741#define CPUID_7_0_EBX_AVX512VL (1U << 31)
742
743
744#define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
745
746#define CPUID_7_0_ECX_UMIP (1U << 2)
747
748#define CPUID_7_0_ECX_PKU (1U << 3)
749
750#define CPUID_7_0_ECX_OSPKE (1U << 4)
751
752#define CPUID_7_0_ECX_WAITPKG (1U << 5)
753
754#define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
755
756#define CPUID_7_0_ECX_GFNI (1U << 8)
757
758#define CPUID_7_0_ECX_VAES (1U << 9)
759
760#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
761
762#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
763
764#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
765
766#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
767
768#define CPUID_7_0_ECX_LA57 (1U << 16)
769
770#define CPUID_7_0_ECX_RDPID (1U << 22)
771
772#define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
773
774#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
775
776#define CPUID_7_0_ECX_MOVDIRI (1U << 27)
777
778#define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
779
780#define CPUID_7_0_ECX_PKS (1U << 31)
781
782
783#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
784
785#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
786
787#define CPUID_7_0_EDX_FSRM (1U << 4)
788
789#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
790
791#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
792
793#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
794
795#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
796
797#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
798
799#define CPUID_7_0_EDX_STIBP (1U << 27)
800
801#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
802
803#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
804
805#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
806
807
808#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
809
810
811#define CPUID_14_0_ECX_LIP (1U << 31)
812
813
814#define CPUID_8000_0008_EBX_CLZERO (1U << 0)
815
816#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
817
818#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
819
820#define CPUID_8000_0008_EBX_IBPB (1U << 12)
821
822#define CPUID_8000_0008_EBX_IBRS (1U << 14)
823
824#define CPUID_8000_0008_EBX_STIBP (1U << 15)
825
826#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
827
828#define CPUID_XSAVE_XSAVEOPT (1U << 0)
829#define CPUID_XSAVE_XSAVEC (1U << 1)
830#define CPUID_XSAVE_XGETBV1 (1U << 2)
831#define CPUID_XSAVE_XSAVES (1U << 3)
832
833#define CPUID_6_EAX_ARAT (1U << 2)
834
835
836#define CPUID_APM_INVTSC (1U << 8)
837
838#define CPUID_VENDOR_SZ 12
839
840#define CPUID_VENDOR_INTEL_1 0x756e6547
841#define CPUID_VENDOR_INTEL_2 0x49656e69
842#define CPUID_VENDOR_INTEL_3 0x6c65746e
843#define CPUID_VENDOR_INTEL "GenuineIntel"
844
845#define CPUID_VENDOR_AMD_1 0x68747541
846#define CPUID_VENDOR_AMD_2 0x69746e65
847#define CPUID_VENDOR_AMD_3 0x444d4163
848#define CPUID_VENDOR_AMD "AuthenticAMD"
849
850#define CPUID_VENDOR_VIA "CentaurHauls"
851
852#define CPUID_VENDOR_HYGON "HygonGenuine"
853
854#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
855 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
856 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
857#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
858 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
859 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
860
861#define CPUID_MWAIT_IBE (1U << 1)
862#define CPUID_MWAIT_EMX (1U << 0)
863
864
865#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
866#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
867#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
868#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
869
870
871#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
872#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
873#define MSR_ARCH_CAP_RSBA (1U << 2)
874#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
875#define MSR_ARCH_CAP_SSB_NO (1U << 4)
876#define MSR_ARCH_CAP_MDS_NO (1U << 5)
877#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
878#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
879#define MSR_ARCH_CAP_TAA_NO (1U << 8)
880
881#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
882
883
884#define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
885#define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
886#define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
887#define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
888#define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
889#define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
890
891#define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
892#define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
893#define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
894#define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
895#define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
896#define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
897#define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
898#define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
899
900#define MSR_VMX_EPT_EXECONLY (1ULL << 0)
901#define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
902#define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
903#define MSR_VMX_EPT_UC (1ULL << 8)
904#define MSR_VMX_EPT_WB (1ULL << 14)
905#define MSR_VMX_EPT_2MB (1ULL << 16)
906#define MSR_VMX_EPT_1GB (1ULL << 17)
907#define MSR_VMX_EPT_INVEPT (1ULL << 20)
908#define MSR_VMX_EPT_AD_BITS (1ULL << 21)
909#define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
910#define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
911#define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
912#define MSR_VMX_EPT_INVVPID (1ULL << 32)
913#define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
914#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
915#define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
916#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
917
918#define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
919
920
921
922#define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
923#define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
924#define VMX_CPU_BASED_HLT_EXITING 0x00000080
925#define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
926#define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
927#define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
928#define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
929#define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
930#define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
931#define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
932#define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
933#define VMX_CPU_BASED_TPR_SHADOW 0x00200000
934#define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
935#define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
936#define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
937#define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
938#define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
939#define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
940#define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
941#define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
942#define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
943
944#define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
945#define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
946#define VMX_SECONDARY_EXEC_DESC 0x00000004
947#define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
948#define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
949#define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
950#define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
951#define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
952#define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
953#define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
954#define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
955#define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
956#define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
957#define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
958#define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
959#define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
960#define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
961#define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
962#define VMX_SECONDARY_EXEC_XSAVES 0x00100000
963
964#define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
965#define VMX_PIN_BASED_NMI_EXITING 0x00000008
966#define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
967#define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
968#define VMX_PIN_BASED_POSTED_INTR 0x00000080
969
970#define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
971#define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
972#define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
973#define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
974#define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
975#define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
976#define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
977#define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
978#define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
979#define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
980#define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
981#define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
982#define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
983
984#define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
985#define VMX_VM_ENTRY_IA32E_MODE 0x00000200
986#define VMX_VM_ENTRY_SMM 0x00000400
987#define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
988#define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
989#define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
990#define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
991#define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
992#define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
993#define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
994#define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
995
996
997#define HYPERV_FEAT_RELAXED 0
998#define HYPERV_FEAT_VAPIC 1
999#define HYPERV_FEAT_TIME 2
1000#define HYPERV_FEAT_CRASH 3
1001#define HYPERV_FEAT_RESET 4
1002#define HYPERV_FEAT_VPINDEX 5
1003#define HYPERV_FEAT_RUNTIME 6
1004#define HYPERV_FEAT_SYNIC 7
1005#define HYPERV_FEAT_STIMER 8
1006#define HYPERV_FEAT_FREQUENCIES 9
1007#define HYPERV_FEAT_REENLIGHTENMENT 10
1008#define HYPERV_FEAT_TLBFLUSH 11
1009#define HYPERV_FEAT_EVMCS 12
1010#define HYPERV_FEAT_IPI 13
1011#define HYPERV_FEAT_STIMER_DIRECT 14
1012
1013#ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1014#define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1015#endif
1016
1017#define EXCP00_DIVZ 0
1018#define EXCP01_DB 1
1019#define EXCP02_NMI 2
1020#define EXCP03_INT3 3
1021#define EXCP04_INTO 4
1022#define EXCP05_BOUND 5
1023#define EXCP06_ILLOP 6
1024#define EXCP07_PREX 7
1025#define EXCP08_DBLE 8
1026#define EXCP09_XERR 9
1027#define EXCP0A_TSS 10
1028#define EXCP0B_NOSEG 11
1029#define EXCP0C_STACK 12
1030#define EXCP0D_GPF 13
1031#define EXCP0E_PAGE 14
1032#define EXCP10_COPR 16
1033#define EXCP11_ALGN 17
1034#define EXCP12_MCHK 18
1035
1036#define EXCP_VMEXIT 0x100
1037#define EXCP_SYSCALL 0x101
1038#define EXCP_VSYSCALL 0x102
1039
1040
1041#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1042#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1043#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1044#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1045#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1046#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1047#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1048
1049
1050#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1051
1052
1053
1054
1055
1056
1057
1058
1059typedef enum {
1060 CC_OP_DYNAMIC,
1061 CC_OP_EFLAGS,
1062
1063 CC_OP_MULB,
1064 CC_OP_MULW,
1065 CC_OP_MULL,
1066 CC_OP_MULQ,
1067
1068 CC_OP_ADDB,
1069 CC_OP_ADDW,
1070 CC_OP_ADDL,
1071 CC_OP_ADDQ,
1072
1073 CC_OP_ADCB,
1074 CC_OP_ADCW,
1075 CC_OP_ADCL,
1076 CC_OP_ADCQ,
1077
1078 CC_OP_SUBB,
1079 CC_OP_SUBW,
1080 CC_OP_SUBL,
1081 CC_OP_SUBQ,
1082
1083 CC_OP_SBBB,
1084 CC_OP_SBBW,
1085 CC_OP_SBBL,
1086 CC_OP_SBBQ,
1087
1088 CC_OP_LOGICB,
1089 CC_OP_LOGICW,
1090 CC_OP_LOGICL,
1091 CC_OP_LOGICQ,
1092
1093 CC_OP_INCB,
1094 CC_OP_INCW,
1095 CC_OP_INCL,
1096 CC_OP_INCQ,
1097
1098 CC_OP_DECB,
1099 CC_OP_DECW,
1100 CC_OP_DECL,
1101 CC_OP_DECQ,
1102
1103 CC_OP_SHLB,
1104 CC_OP_SHLW,
1105 CC_OP_SHLL,
1106 CC_OP_SHLQ,
1107
1108 CC_OP_SARB,
1109 CC_OP_SARW,
1110 CC_OP_SARL,
1111 CC_OP_SARQ,
1112
1113 CC_OP_BMILGB,
1114 CC_OP_BMILGW,
1115 CC_OP_BMILGL,
1116 CC_OP_BMILGQ,
1117
1118 CC_OP_ADCX,
1119 CC_OP_ADOX,
1120 CC_OP_ADCOX,
1121
1122 CC_OP_CLR,
1123 CC_OP_POPCNT,
1124
1125 CC_OP_NB,
1126} CCOp;
1127
1128typedef struct SegmentCache {
1129 uint32_t selector;
1130 target_ulong base;
1131 uint32_t limit;
1132 uint32_t flags;
1133} SegmentCache;
1134
1135#define MMREG_UNION(n, bits) \
1136 union n { \
1137 uint8_t _b_##n[(bits)/8]; \
1138 uint16_t _w_##n[(bits)/16]; \
1139 uint32_t _l_##n[(bits)/32]; \
1140 uint64_t _q_##n[(bits)/64]; \
1141 float32 _s_##n[(bits)/32]; \
1142 float64 _d_##n[(bits)/64]; \
1143 }
1144
1145typedef union {
1146 uint8_t _b[16];
1147 uint16_t _w[8];
1148 uint32_t _l[4];
1149 uint64_t _q[2];
1150} XMMReg;
1151
1152typedef union {
1153 uint8_t _b[32];
1154 uint16_t _w[16];
1155 uint32_t _l[8];
1156 uint64_t _q[4];
1157} YMMReg;
1158
1159typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
1160typedef MMREG_UNION(MMXReg, 64) MMXReg;
1161
1162typedef struct BNDReg {
1163 uint64_t lb;
1164 uint64_t ub;
1165} BNDReg;
1166
1167typedef struct BNDCSReg {
1168 uint64_t cfgu;
1169 uint64_t sts;
1170} BNDCSReg;
1171
1172#define BNDCFG_ENABLE 1ULL
1173#define BNDCFG_BNDPRESERVE 2ULL
1174#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1175
1176#ifdef HOST_WORDS_BIGENDIAN
1177#define ZMM_B(n) _b_ZMMReg[63 - (n)]
1178#define ZMM_W(n) _w_ZMMReg[31 - (n)]
1179#define ZMM_L(n) _l_ZMMReg[15 - (n)]
1180#define ZMM_S(n) _s_ZMMReg[15 - (n)]
1181#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1182#define ZMM_D(n) _d_ZMMReg[7 - (n)]
1183
1184#define MMX_B(n) _b_MMXReg[7 - (n)]
1185#define MMX_W(n) _w_MMXReg[3 - (n)]
1186#define MMX_L(n) _l_MMXReg[1 - (n)]
1187#define MMX_S(n) _s_MMXReg[1 - (n)]
1188#else
1189#define ZMM_B(n) _b_ZMMReg[n]
1190#define ZMM_W(n) _w_ZMMReg[n]
1191#define ZMM_L(n) _l_ZMMReg[n]
1192#define ZMM_S(n) _s_ZMMReg[n]
1193#define ZMM_Q(n) _q_ZMMReg[n]
1194#define ZMM_D(n) _d_ZMMReg[n]
1195
1196#define MMX_B(n) _b_MMXReg[n]
1197#define MMX_W(n) _w_MMXReg[n]
1198#define MMX_L(n) _l_MMXReg[n]
1199#define MMX_S(n) _s_MMXReg[n]
1200#endif
1201#define MMX_Q(n) _q_MMXReg[n]
1202
1203typedef union {
1204 floatx80 d __attribute__((aligned(16)));
1205 MMXReg mmx;
1206} FPReg;
1207
1208typedef struct {
1209 uint64_t base;
1210 uint64_t mask;
1211} MTRRVar;
1212
1213#define CPU_NB_REGS64 16
1214#define CPU_NB_REGS32 8
1215
1216#ifdef TARGET_X86_64
1217#define CPU_NB_REGS CPU_NB_REGS64
1218#else
1219#define CPU_NB_REGS CPU_NB_REGS32
1220#endif
1221
1222#define MAX_FIXED_COUNTERS 3
1223#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1224
1225#define TARGET_INSN_START_EXTRA_WORDS 1
1226
1227#define NB_OPMASK_REGS 8
1228
1229
1230
1231
1232#define UNASSIGNED_APIC_ID 0xFFFFFFFF
1233
1234typedef union X86LegacyXSaveArea {
1235 struct {
1236 uint16_t fcw;
1237 uint16_t fsw;
1238 uint8_t ftw;
1239 uint8_t reserved;
1240 uint16_t fpop;
1241 uint64_t fpip;
1242 uint64_t fpdp;
1243 uint32_t mxcsr;
1244 uint32_t mxcsr_mask;
1245 FPReg fpregs[8];
1246 uint8_t xmm_regs[16][16];
1247 };
1248 uint8_t data[512];
1249} X86LegacyXSaveArea;
1250
1251typedef struct X86XSaveHeader {
1252 uint64_t xstate_bv;
1253 uint64_t xcomp_bv;
1254 uint64_t reserve0;
1255 uint8_t reserved[40];
1256} X86XSaveHeader;
1257
1258
1259typedef struct XSaveAVX {
1260 uint8_t ymmh[16][16];
1261} XSaveAVX;
1262
1263
1264typedef struct XSaveBNDREG {
1265 BNDReg bnd_regs[4];
1266} XSaveBNDREG;
1267
1268
1269typedef union XSaveBNDCSR {
1270 BNDCSReg bndcsr;
1271 uint8_t data[64];
1272} XSaveBNDCSR;
1273
1274
1275typedef struct XSaveOpmask {
1276 uint64_t opmask_regs[NB_OPMASK_REGS];
1277} XSaveOpmask;
1278
1279
1280typedef struct XSaveZMM_Hi256 {
1281 uint8_t zmm_hi256[16][32];
1282} XSaveZMM_Hi256;
1283
1284
1285typedef struct XSaveHi16_ZMM {
1286 uint8_t hi16_zmm[16][64];
1287} XSaveHi16_ZMM;
1288
1289
1290typedef struct XSavePKRU {
1291 uint32_t pkru;
1292 uint32_t padding;
1293} XSavePKRU;
1294
1295typedef struct X86XSaveArea {
1296 X86LegacyXSaveArea legacy;
1297 X86XSaveHeader header;
1298
1299
1300
1301
1302 XSaveAVX avx_state;
1303 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1304
1305 XSaveBNDREG bndreg_state;
1306 XSaveBNDCSR bndcsr_state;
1307
1308 XSaveOpmask opmask_state;
1309 XSaveZMM_Hi256 zmm_hi256_state;
1310 XSaveHi16_ZMM hi16_zmm_state;
1311
1312 XSavePKRU pkru_state;
1313} X86XSaveArea;
1314
1315QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1316QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1317QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1318QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1319QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1320QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1321QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1322QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1323QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1324QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1325QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1326QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1327QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1328QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1329
1330typedef enum TPRAccess {
1331 TPR_ACCESS_READ,
1332 TPR_ACCESS_WRITE,
1333} TPRAccess;
1334
1335
1336
1337enum CacheType {
1338 DATA_CACHE,
1339 INSTRUCTION_CACHE,
1340 UNIFIED_CACHE
1341};
1342
1343typedef struct CPUCacheInfo {
1344 enum CacheType type;
1345 uint8_t level;
1346
1347 uint32_t size;
1348
1349 uint16_t line_size;
1350
1351
1352
1353
1354 uint8_t associativity;
1355
1356 uint8_t partitions;
1357
1358 uint32_t sets;
1359
1360
1361
1362
1363
1364 uint8_t lines_per_tag;
1365
1366
1367 bool self_init;
1368
1369
1370
1371
1372
1373 bool no_invd_sharing;
1374
1375
1376
1377
1378 bool inclusive;
1379
1380
1381
1382
1383 bool complex_indexing;
1384} CPUCacheInfo;
1385
1386
1387typedef struct CPUCaches {
1388 CPUCacheInfo *l1d_cache;
1389 CPUCacheInfo *l1i_cache;
1390 CPUCacheInfo *l2_cache;
1391 CPUCacheInfo *l3_cache;
1392} CPUCaches;
1393
1394typedef struct HVFX86LazyFlags {
1395 target_ulong result;
1396 target_ulong auxbits;
1397} HVFX86LazyFlags;
1398
1399typedef struct CPUX86State {
1400
1401 target_ulong regs[CPU_NB_REGS];
1402 target_ulong eip;
1403 target_ulong eflags;
1404
1405
1406
1407
1408 target_ulong cc_dst;
1409 target_ulong cc_src;
1410 target_ulong cc_src2;
1411 uint32_t cc_op;
1412 int32_t df;
1413 uint32_t hflags;
1414
1415 uint32_t hflags2;
1416
1417
1418 SegmentCache segs[6];
1419 SegmentCache ldt;
1420 SegmentCache tr;
1421 SegmentCache gdt;
1422 SegmentCache idt;
1423
1424 target_ulong cr[5];
1425 int32_t a20_mask;
1426
1427 BNDReg bnd_regs[4];
1428 BNDCSReg bndcs_regs;
1429 uint64_t msr_bndcfgs;
1430 uint64_t efer;
1431
1432
1433 struct {} start_init_save;
1434
1435
1436 unsigned int fpstt;
1437 uint16_t fpus;
1438 uint16_t fpuc;
1439 uint8_t fptags[8];
1440 FPReg fpregs[8];
1441
1442 uint16_t fpop;
1443 uint64_t fpip;
1444 uint64_t fpdp;
1445
1446
1447 float_status fp_status;
1448 floatx80 ft0;
1449
1450 float_status mmx_status;
1451 float_status sse_status;
1452 uint32_t mxcsr;
1453 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1454 ZMMReg xmm_t0;
1455 MMXReg mmx_t0;
1456
1457 XMMReg ymmh_regs[CPU_NB_REGS];
1458
1459 uint64_t opmask_regs[NB_OPMASK_REGS];
1460 YMMReg zmmh_regs[CPU_NB_REGS];
1461 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1462
1463
1464 uint32_t sysenter_cs;
1465 target_ulong sysenter_esp;
1466 target_ulong sysenter_eip;
1467 uint64_t star;
1468
1469 uint64_t vm_hsave;
1470
1471#ifdef TARGET_X86_64
1472 target_ulong lstar;
1473 target_ulong cstar;
1474 target_ulong fmask;
1475 target_ulong kernelgsbase;
1476#endif
1477
1478 uint64_t tsc;
1479 uint64_t tsc_adjust;
1480 uint64_t tsc_deadline;
1481 uint64_t tsc_aux;
1482
1483 uint64_t xcr0;
1484
1485 uint64_t mcg_status;
1486 uint64_t msr_ia32_misc_enable;
1487 uint64_t msr_ia32_feature_control;
1488
1489 uint64_t msr_fixed_ctr_ctrl;
1490 uint64_t msr_global_ctrl;
1491 uint64_t msr_global_status;
1492 uint64_t msr_global_ovf_ctrl;
1493 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1494 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1495 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1496
1497 uint64_t pat;
1498 uint32_t smbase;
1499 uint64_t msr_smi_count;
1500
1501 uint32_t pkru;
1502 uint32_t pkrs;
1503 uint32_t tsx_ctrl;
1504
1505 uint64_t spec_ctrl;
1506 uint64_t virt_ssbd;
1507
1508
1509 struct {} end_init_save;
1510
1511 uint64_t system_time_msr;
1512 uint64_t wall_clock_msr;
1513 uint64_t steal_time_msr;
1514 uint64_t async_pf_en_msr;
1515 uint64_t async_pf_int_msr;
1516 uint64_t pv_eoi_en_msr;
1517 uint64_t poll_control_msr;
1518
1519
1520 uint64_t msr_hv_hypercall;
1521 uint64_t msr_hv_guest_os_id;
1522 uint64_t msr_hv_tsc;
1523
1524
1525 uint64_t msr_hv_vapic;
1526 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1527 uint64_t msr_hv_runtime;
1528 uint64_t msr_hv_synic_control;
1529 uint64_t msr_hv_synic_evt_page;
1530 uint64_t msr_hv_synic_msg_page;
1531 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1532 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1533 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1534 uint64_t msr_hv_reenlightenment_control;
1535 uint64_t msr_hv_tsc_emulation_control;
1536 uint64_t msr_hv_tsc_emulation_status;
1537
1538 uint64_t msr_rtit_ctrl;
1539 uint64_t msr_rtit_status;
1540 uint64_t msr_rtit_output_base;
1541 uint64_t msr_rtit_output_mask;
1542 uint64_t msr_rtit_cr3_match;
1543 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1544
1545
1546 int error_code;
1547 int exception_is_int;
1548 target_ulong exception_next_eip;
1549 target_ulong dr[8];
1550 union {
1551 struct CPUBreakpoint *cpu_breakpoint[4];
1552 struct CPUWatchpoint *cpu_watchpoint[4];
1553 };
1554 int old_exception;
1555
1556 uint64_t vm_vmcb;
1557 uint64_t tsc_offset;
1558 uint64_t intercept;
1559 uint16_t intercept_cr_read;
1560 uint16_t intercept_cr_write;
1561 uint16_t intercept_dr_read;
1562 uint16_t intercept_dr_write;
1563 uint32_t intercept_exceptions;
1564 uint64_t nested_cr3;
1565 uint32_t nested_pg_mode;
1566 uint8_t v_tpr;
1567
1568
1569 uint8_t nmi_injected;
1570 uint8_t nmi_pending;
1571
1572 uintptr_t retaddr;
1573
1574
1575 struct {} end_reset_fields;
1576
1577
1578
1579
1580
1581 uint32_t cpuid_level_func7;
1582
1583 uint32_t cpuid_min_level_func7;
1584
1585 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1586
1587 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1588
1589 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1590 uint32_t cpuid_vendor1;
1591 uint32_t cpuid_vendor2;
1592 uint32_t cpuid_vendor3;
1593 uint32_t cpuid_version;
1594 FeatureWordArray features;
1595
1596 FeatureWordArray user_features;
1597 uint32_t cpuid_model[12];
1598
1599
1600
1601
1602 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1603
1604
1605 uint64_t mtrr_fixed[11];
1606 uint64_t mtrr_deftype;
1607 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1608
1609
1610 uint32_t mp_state;
1611 int32_t exception_nr;
1612 int32_t interrupt_injected;
1613 uint8_t soft_interrupt;
1614 uint8_t exception_pending;
1615 uint8_t exception_injected;
1616 uint8_t has_error_code;
1617 uint8_t exception_has_payload;
1618 uint64_t exception_payload;
1619 uint32_t ins_len;
1620 uint32_t sipi_vector;
1621 bool tsc_valid;
1622 int64_t tsc_khz;
1623 int64_t user_tsc_khz;
1624 uint64_t apic_bus_freq;
1625#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1626 void *xsave_buf;
1627#endif
1628#if defined(CONFIG_KVM)
1629 struct kvm_nested_state *nested_state;
1630#endif
1631#if defined(CONFIG_HVF)
1632 HVFX86LazyFlags hvf_lflags;
1633 void *hvf_mmio_buf;
1634#endif
1635
1636 uint64_t mcg_cap;
1637 uint64_t mcg_ctl;
1638 uint64_t mcg_ext_ctl;
1639 uint64_t mce_banks[MCE_BANKS_DEF*4];
1640 uint64_t xstate_bv;
1641
1642
1643 uint16_t fpus_vmstate;
1644 uint16_t fptag_vmstate;
1645 uint16_t fpregs_format_vmstate;
1646
1647 uint64_t xss;
1648 uint32_t umwait;
1649
1650 TPRAccess tpr_access_type;
1651
1652 unsigned nr_dies;
1653} CPUX86State;
1654
1655struct kvm_msrs;
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666struct X86CPU {
1667
1668 CPUState parent_obj;
1669
1670
1671 CPUNegativeOffsetState neg;
1672 CPUX86State env;
1673 VMChangeStateEntry *vmsentry;
1674
1675 uint64_t ucode_rev;
1676
1677 uint32_t hyperv_spinlock_attempts;
1678 char *hyperv_vendor;
1679 bool hyperv_synic_kvm_only;
1680 uint64_t hyperv_features;
1681 bool hyperv_passthrough;
1682 OnOffAuto hyperv_no_nonarch_cs;
1683 uint32_t hyperv_vendor_id[3];
1684 uint32_t hyperv_interface_id[4];
1685 uint32_t hyperv_version_id[4];
1686 uint32_t hyperv_limits[3];
1687
1688 bool check_cpuid;
1689 bool enforce_cpuid;
1690
1691
1692
1693
1694
1695 bool force_features;
1696 bool expose_kvm;
1697 bool expose_tcg;
1698 bool migratable;
1699 bool migrate_smi_count;
1700 bool max_features;
1701 uint32_t apic_id;
1702
1703
1704
1705 bool vmware_cpuid_freq;
1706
1707
1708 bool cache_info_passthrough;
1709
1710
1711
1712 struct {
1713 uint32_t eax;
1714 uint32_t ebx;
1715 uint32_t ecx;
1716 uint32_t edx;
1717 } mwait;
1718
1719
1720 FeatureWordArray filtered_features;
1721
1722
1723
1724
1725
1726
1727 bool enable_pmu;
1728
1729
1730
1731
1732
1733 bool enable_lmce;
1734
1735
1736
1737
1738
1739 bool enable_l3_cache;
1740
1741
1742
1743
1744 bool legacy_cache;
1745
1746
1747 bool enable_cpuid_0xb;
1748
1749
1750 bool full_cpuid_auto_level;
1751
1752
1753 bool intel_pt_auto_level;
1754
1755
1756 bool fill_mtrr_mask;
1757
1758
1759 bool host_phys_bits;
1760
1761
1762 uint8_t host_phys_bits_limit;
1763
1764
1765 bool kvm_no_smi_migration;
1766
1767
1768 uint32_t phys_bits;
1769
1770
1771
1772 struct DeviceState *apic_state;
1773 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1774 Notifier machine_done;
1775
1776 struct kvm_msrs *kvm_msr_buf;
1777
1778 int32_t node_id;
1779 int32_t socket_id;
1780 int32_t die_id;
1781 int32_t core_id;
1782 int32_t thread_id;
1783
1784 int32_t hv_max_vps;
1785};
1786
1787
1788#ifndef CONFIG_USER_ONLY
1789extern VMStateDescription vmstate_x86_cpu;
1790#endif
1791
1792int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
1793
1794int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1795 int cpuid, void *opaque);
1796int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1797 int cpuid, void *opaque);
1798int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1799 void *opaque);
1800int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1801 void *opaque);
1802
1803void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1804 Error **errp);
1805
1806void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
1807
1808hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1809 MemTxAttrs *attrs);
1810
1811int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1812int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1813
1814void x86_cpu_list(void);
1815int cpu_x86_support_mca_broadcast(CPUX86State *env);
1816
1817int cpu_get_pic_interrupt(CPUX86State *s);
1818
1819void x86_register_ferr_irq(qemu_irq irq);
1820void cpu_set_ignne(void);
1821
1822void cpu_sync_bndcs_hflags(CPUX86State *env);
1823
1824
1825
1826static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1827 X86Seg seg_reg, unsigned int selector,
1828 target_ulong base,
1829 unsigned int limit,
1830 unsigned int flags)
1831{
1832 SegmentCache *sc;
1833 unsigned int new_hflags;
1834
1835 sc = &env->segs[seg_reg];
1836 sc->selector = selector;
1837 sc->base = base;
1838 sc->limit = limit;
1839 sc->flags = flags;
1840
1841
1842 {
1843 if (seg_reg == R_CS) {
1844#ifdef TARGET_X86_64
1845 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1846
1847 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1848 env->hflags &= ~(HF_ADDSEG_MASK);
1849 } else
1850#endif
1851 {
1852
1853 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1854 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1855 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1856 new_hflags;
1857 }
1858 }
1859 if (seg_reg == R_SS) {
1860 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1861#if HF_CPL_MASK != 3
1862#error HF_CPL_MASK is hardcoded
1863#endif
1864 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1865
1866 cpu_sync_bndcs_hflags(env);
1867 }
1868 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1869 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1870 if (env->hflags & HF_CS64_MASK) {
1871
1872 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1873 (env->eflags & VM_MASK) ||
1874 !(env->hflags & HF_CS32_MASK)) {
1875
1876
1877
1878
1879
1880 new_hflags |= HF_ADDSEG_MASK;
1881 } else {
1882 new_hflags |= ((env->segs[R_DS].base |
1883 env->segs[R_ES].base |
1884 env->segs[R_SS].base) != 0) <<
1885 HF_ADDSEG_SHIFT;
1886 }
1887 env->hflags = (env->hflags &
1888 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1889 }
1890}
1891
1892static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1893 uint8_t sipi_vector)
1894{
1895 CPUState *cs = CPU(cpu);
1896 CPUX86State *env = &cpu->env;
1897
1898 env->eip = 0;
1899 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1900 sipi_vector << 12,
1901 env->segs[R_CS].limit,
1902 env->segs[R_CS].flags);
1903 cs->halted = 0;
1904}
1905
1906int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1907 target_ulong *base, unsigned int *limit,
1908 unsigned int *flags);
1909
1910
1911
1912
1913
1914
1915
1916void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
1917void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1918void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1919void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1920void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1921
1922
1923
1924
1925int cpu_x86_signal_handler(int host_signum, void *pinfo,
1926 void *puc);
1927
1928
1929void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1930 uint32_t *eax, uint32_t *ebx,
1931 uint32_t *ecx, uint32_t *edx);
1932void cpu_clear_apic_feature(CPUX86State *env);
1933void host_cpuid(uint32_t function, uint32_t count,
1934 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1935void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1936
1937
1938void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1939
1940#ifndef CONFIG_USER_ONLY
1941static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1942{
1943 return !!attrs.secure;
1944}
1945
1946static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1947{
1948 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1949}
1950
1951uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1952uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1953uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1954uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1955void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1956void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1957void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1958void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1959void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1960#endif
1961
1962
1963void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1964void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1965void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1966void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1967
1968
1969uint64_t cpu_get_tsc(CPUX86State *env);
1970
1971#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1972#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1973#define CPU_RESOLVING_TYPE TYPE_X86_CPU
1974
1975#ifdef TARGET_X86_64
1976#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1977#else
1978#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1979#endif
1980
1981#define cpu_signal_handler cpu_x86_signal_handler
1982#define cpu_list x86_cpu_list
1983
1984
1985#define MMU_KSMAP_IDX 0
1986#define MMU_USER_IDX 1
1987#define MMU_KNOSMAP_IDX 2
1988static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1989{
1990 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1991 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1992 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1993}
1994
1995static inline int cpu_mmu_index_kernel(CPUX86State *env)
1996{
1997 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1998 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1999 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
2000}
2001
2002#define CC_DST (env->cc_dst)
2003#define CC_SRC (env->cc_src)
2004#define CC_SRC2 (env->cc_src2)
2005#define CC_OP (env->cc_op)
2006
2007typedef CPUX86State CPUArchState;
2008typedef X86CPU ArchCPU;
2009
2010#include "exec/cpu-all.h"
2011#include "svm.h"
2012
2013#if !defined(CONFIG_USER_ONLY)
2014#include "hw/i386/apic.h"
2015#endif
2016
2017static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
2018 target_ulong *cs_base, uint32_t *flags)
2019{
2020 *cs_base = env->segs[R_CS].base;
2021 *pc = *cs_base + env->eip;
2022 *flags = env->hflags |
2023 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2024}
2025
2026void do_cpu_init(X86CPU *cpu);
2027void do_cpu_sipi(X86CPU *cpu);
2028
2029#define MCE_INJECT_BROADCAST 1
2030#define MCE_INJECT_UNCOND_AO 2
2031
2032void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2033 uint64_t status, uint64_t mcg_status, uint64_t addr,
2034 uint64_t misc, int flags);
2035
2036uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
2037
2038static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2039{
2040 uint32_t eflags = env->eflags;
2041 if (tcg_enabled()) {
2042 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
2043 }
2044 return eflags;
2045}
2046
2047
2048
2049
2050static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
2051{
2052 env->efer = val;
2053 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
2054 if (env->efer & MSR_EFER_LMA) {
2055 env->hflags |= HF_LMA_MASK;
2056 }
2057 if (env->efer & MSR_EFER_SVME) {
2058 env->hflags |= HF_SVME_MASK;
2059 }
2060}
2061
2062static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2063{
2064 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2065}
2066
2067static inline int32_t x86_get_a20_mask(CPUX86State *env)
2068{
2069 if (env->hflags & HF_SMM_MASK) {
2070 return -1;
2071 } else {
2072 return env->a20_mask;
2073 }
2074}
2075
2076static inline bool cpu_has_vmx(CPUX86State *env)
2077{
2078 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2079}
2080
2081static inline bool cpu_has_svm(CPUX86State *env)
2082{
2083 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2084}
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2103{
2104 return cpu_has_vmx(env) &&
2105 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2106}
2107
2108
2109void update_fp_status(CPUX86State *env);
2110void update_mxcsr_status(CPUX86State *env);
2111void update_mxcsr_from_sse_status(CPUX86State *env);
2112
2113static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2114{
2115 env->mxcsr = mxcsr;
2116 if (tcg_enabled()) {
2117 update_mxcsr_status(env);
2118 }
2119}
2120
2121static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2122{
2123 env->fpuc = fpuc;
2124 if (tcg_enabled()) {
2125 update_fp_status(env);
2126 }
2127}
2128
2129
2130void helper_lock_init(void);
2131
2132
2133void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2134 uint64_t param, uintptr_t retaddr);
2135
2136void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2137void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2138 TPRAccess access);
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149void x86_cpu_change_kvm_default(const char *prop, const char *value);
2150
2151
2152
2153
2154#define CPU_VERSION_LATEST -1
2155
2156
2157
2158
2159
2160#define CPU_VERSION_AUTO -2
2161
2162
2163#define CPU_VERSION_LEGACY 0
2164
2165typedef int X86CPUVersion;
2166
2167
2168
2169
2170
2171void x86_cpu_set_default_version(X86CPUVersion version);
2172
2173#define APIC_DEFAULT_ADDRESS 0xfee00000
2174#define APIC_SPACE_SIZE 0x100000
2175
2176
2177void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2178
2179
2180bool cpu_is_bsp(X86CPU *cpu);
2181
2182void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
2183void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
2184void x86_update_hflags(CPUX86State* env);
2185
2186static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2187{
2188 return !!(cpu->hyperv_features & BIT(feat));
2189}
2190
2191#if defined(TARGET_X86_64) && \
2192 defined(CONFIG_USER_ONLY) && \
2193 defined(CONFIG_LINUX)
2194# define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2195#endif
2196
2197#endif
2198