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20#ifndef QEMU_PPC_CPU_QOM_H
21#define QEMU_PPC_CPU_QOM_H
22
23#include "hw/core/cpu.h"
24#include "qom/object.h"
25
26#ifdef TARGET_PPC64
27#define TYPE_POWERPC_CPU "powerpc64-cpu"
28#else
29#define TYPE_POWERPC_CPU "powerpc-cpu"
30#endif
31
32OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
33 POWERPC_CPU)
34
35typedef struct CPUPPCState CPUPPCState;
36typedef struct ppc_tb_t ppc_tb_t;
37typedef struct ppc_dcr_t ppc_dcr_t;
38
39
40
41typedef enum powerpc_mmu_t powerpc_mmu_t;
42enum powerpc_mmu_t {
43 POWERPC_MMU_UNKNOWN = 0x00000000,
44
45 POWERPC_MMU_32B = 0x00000001,
46
47 POWERPC_MMU_SOFT_6xx = 0x00000002,
48
49 POWERPC_MMU_SOFT_74xx = 0x00000003,
50
51 POWERPC_MMU_SOFT_4xx = 0x00000004,
52
53 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
54
55 POWERPC_MMU_REAL = 0x00000006,
56
57 POWERPC_MMU_MPC8xx = 0x00000007,
58
59 POWERPC_MMU_BOOKE = 0x00000008,
60
61 POWERPC_MMU_BOOKE206 = 0x00000009,
62
63 POWERPC_MMU_601 = 0x0000000A,
64#define POWERPC_MMU_64 0x00010000
65
66 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
67
68 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
69
70 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
71
72 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
73
74 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
75};
76
77static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
78{
79 return mmu_model & POWERPC_MMU_64;
80}
81
82
83
84typedef enum powerpc_excp_t powerpc_excp_t;
85enum powerpc_excp_t {
86 POWERPC_EXCP_UNKNOWN = 0,
87
88 POWERPC_EXCP_STD,
89
90 POWERPC_EXCP_40x,
91
92 POWERPC_EXCP_601,
93
94 POWERPC_EXCP_602,
95
96 POWERPC_EXCP_603,
97
98 POWERPC_EXCP_603E,
99
100 POWERPC_EXCP_G2,
101
102 POWERPC_EXCP_604,
103
104 POWERPC_EXCP_7x0,
105
106 POWERPC_EXCP_7x5,
107
108 POWERPC_EXCP_74xx,
109
110 POWERPC_EXCP_BOOKE,
111
112 POWERPC_EXCP_970,
113
114 POWERPC_EXCP_POWER7,
115
116 POWERPC_EXCP_POWER8,
117
118 POWERPC_EXCP_POWER9,
119};
120
121
122
123typedef enum {
124 PPC_PM_DOZE,
125 PPC_PM_NAP,
126 PPC_PM_SLEEP,
127 PPC_PM_RVWINKLE,
128 PPC_PM_STOP,
129} powerpc_pm_insn_t;
130
131
132
133typedef enum powerpc_input_t powerpc_input_t;
134enum powerpc_input_t {
135 PPC_FLAGS_INPUT_UNKNOWN = 0,
136
137 PPC_FLAGS_INPUT_6xx,
138
139 PPC_FLAGS_INPUT_BookE,
140
141 PPC_FLAGS_INPUT_405,
142
143 PPC_FLAGS_INPUT_970,
144
145 PPC_FLAGS_INPUT_POWER7,
146
147 PPC_FLAGS_INPUT_POWER9,
148
149 PPC_FLAGS_INPUT_401,
150
151 PPC_FLAGS_INPUT_RCPU,
152};
153
154typedef struct PPCHash64Options PPCHash64Options;
155
156
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159
160
161
162
163struct PowerPCCPUClass {
164
165 CPUClass parent_class;
166
167
168 DeviceRealize parent_realize;
169 DeviceUnrealize parent_unrealize;
170 DeviceReset parent_reset;
171 void (*parent_parse_features)(const char *type, char *str, Error **errp);
172
173 uint32_t pvr;
174 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
175 uint64_t pcr_mask;
176 uint64_t pcr_supported;
177 uint32_t svr;
178 uint64_t insns_flags;
179 uint64_t insns_flags2;
180 uint64_t msr_mask;
181 uint64_t lpcr_mask;
182 uint64_t lpcr_pm;
183 powerpc_mmu_t mmu_model;
184 powerpc_excp_t excp_model;
185 powerpc_input_t bus_model;
186 uint32_t flags;
187 int bfd_mach;
188 uint32_t l1_dcache_size, l1_icache_size;
189#ifndef CONFIG_USER_ONLY
190 unsigned int gdb_num_sprs;
191 const char *gdb_spr_xml;
192#endif
193 const PPCHash64Options *hash64_opts;
194 struct ppc_radix_page_info *radix_page_info;
195 uint32_t lrg_decr_bits;
196 int n_host_threads;
197 void (*init_proc)(CPUPPCState *env);
198 int (*check_pow)(CPUPPCState *env);
199 int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
200 bool (*interrupts_big_endian)(PowerPCCPU *cpu);
201};
202
203#ifndef CONFIG_USER_ONLY
204typedef struct PPCTimebase {
205 uint64_t guest_timebase;
206 int64_t time_of_the_day_ns;
207 bool runstate_paused;
208} PPCTimebase;
209
210extern const VMStateDescription vmstate_ppc_timebase;
211
212#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \
213 .name = (stringify(_field)), \
214 .version_id = (_version), \
215 .size = sizeof(PPCTimebase), \
216 .vmsd = &vmstate_ppc_timebase, \
217 .flags = VMS_STRUCT, \
218 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \
219}
220
221void cpu_ppc_clock_vm_state_change(void *opaque, bool running,
222 RunState state);
223#endif
224
225#endif
226