LXR qemu/target/ppc/cpu.h

   1/*
   2 *  PowerPC emulation cpu definitions for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef PPC_CPU_H
  21#define PPC_CPU_H
  22
  23#include "qemu/int128.h"
  24#include "exec/cpu-defs.h"
  25#include "cpu-qom.h"
  26#include "qom/object.h"
  27
  28#define TCG_GUEST_DEFAULT_MO 0
  29
  30#define TARGET_PAGE_BITS_64K 16
  31#define TARGET_PAGE_BITS_16M 24
  32
  33#if defined(TARGET_PPC64)
  34#define PPC_ELF_MACHINE     EM_PPC64
  35#else
  36#define PPC_ELF_MACHINE     EM_PPC
  37#endif
  38
  39#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
  40#define PPC_BIT32(bit)          (0x80000000 >> (bit))
  41#define PPC_BIT8(bit)           (0x80 >> (bit))
  42#define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
  43#define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
  44                                 PPC_BIT32(bs))
  45#define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
  46
  47/*****************************************************************************/
  48/* Exception vectors definitions                                             */
  49enum {
  50    POWERPC_EXCP_NONE    = -1,
  51    /* The 64 first entries are used by the PowerPC embedded specification   */
  52    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
  53    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
  54    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
  55    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
  56    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
  57    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
  58    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
  59    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
  60    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
  61    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
  62    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
  63    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
  64    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
  65    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
  66    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
  67    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
  68    /* Vectors 16 to 31 are reserved                                         */
  69    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
  70    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
  71    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
  72    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
  73    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
  74    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
  75    POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
  76    POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
  77    POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
  78    /* Vectors 42 to 63 are reserved                                         */
  79    /* Exceptions defined in the PowerPC server specification                */
  80    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
  81    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
  82    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
  83    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
  84    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
  85    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
  86    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
  87    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
  88    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
  89    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
  90    /* 40x specific exceptions                                               */
  91    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
  92    /* 601 specific exceptions                                               */
  93    POWERPC_EXCP_IO       = 75, /* IO error exception                        */
  94    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
  95    /* 602 specific exceptions                                               */
  96    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
  97    /* 602/603 specific exceptions                                           */
  98    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
  99    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 100    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 101    /* Exceptions available on most PowerPC                                  */
 102    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 103    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 104    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 105    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 106    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 107    /* 7xx/74xx specific exceptions                                          */
 108    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 109    /* 74xx specific exceptions                                              */
 110    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 111    /* 970FX specific exceptions                                             */
 112    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 113    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 114    /* Freescale embedded cores specific exceptions                          */
 115    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 116    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 117    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 118    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 119    /* VSX Unavailable (Power ISA 2.06 and later)                            */
 120    POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 121    POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
 122    /* Additional ISA 2.06 and later server exceptions                       */
 123    POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
 124    POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
 125    POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
 126    /* Server doorbell variants */
 127    POWERPC_EXCP_SDOOR    = 99,
 128    POWERPC_EXCP_SDOOR_HV = 100,
 129    /* ISA 3.00 additions */
 130    POWERPC_EXCP_HVIRT    = 101,
 131    POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception                     */
 132    /* EOL                                                                   */
 133    POWERPC_EXCP_NB       = 103,
 134    /* QEMU exceptions: used internally during code translation              */
 135    POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 136    POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 137    /* QEMU exceptions: special cases we want to stop translation            */
 138    POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 139    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 140};
 141
 142/* Exceptions error codes                                                    */
 143enum {
 144    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 145    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 146    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 147    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 148    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 149    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 150    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 151    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 152    /* FP exceptions                                                         */
 153    POWERPC_EXCP_FP            = 0x10,
 154    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 155    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 156    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 157    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 158    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 159    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 160    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 161    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 162    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 163    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 164    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 165    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 166    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 167    /* Invalid instruction                                                   */
 168    POWERPC_EXCP_INVAL         = 0x20,
 169    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 170    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 171    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 172    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 173    /* Privileged instruction                                                */
 174    POWERPC_EXCP_PRIV          = 0x30,
 175    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 176    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 177    /* Trap                                                                  */
 178    POWERPC_EXCP_TRAP          = 0x40,
 179};
 180
 181#define PPC_INPUT(env) ((env)->bus_model)
 182
 183/*****************************************************************************/
 184typedef struct opc_handler_t opc_handler_t;
 185
 186/*****************************************************************************/
 187/* Types used to describe some PowerPC registers etc. */
 188typedef struct DisasContext DisasContext;
 189typedef struct ppc_spr_t ppc_spr_t;
 190typedef union ppc_tlb_t ppc_tlb_t;
 191typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
 192
 193/* SPR access micro-ops generations callbacks */
 194struct ppc_spr_t {
 195    void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 196    void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 197#if !defined(CONFIG_USER_ONLY)
 198    void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 199    void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 200    void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 201    void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 202    unsigned int gdb_id;
 203#endif
 204    const char *name;
 205    target_ulong default_value;
 206#ifdef CONFIG_KVM
 207    /*
 208     * We (ab)use the fact that all the SPRs will have ids for the
 209     * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 210     * don't sync this
 211     */
 212    uint64_t one_reg_id;
 213#endif
 214};
 215
 216/* VSX/Altivec registers (128 bits) */
 217typedef union _ppc_vsr_t {
 218    uint8_t u8[16];
 219    uint16_t u16[8];
 220    uint32_t u32[4];
 221    uint64_t u64[2];
 222    int8_t s8[16];
 223    int16_t s16[8];
 224    int32_t s32[4];
 225    int64_t s64[2];
 226    float32 f32[4];
 227    float64 f64[2];
 228    float128 f128;
 229#ifdef CONFIG_INT128
 230    __uint128_t u128;
 231#endif
 232    Int128  s128;
 233} ppc_vsr_t;
 234
 235typedef ppc_vsr_t ppc_avr_t;
 236typedef ppc_vsr_t ppc_fprp_t;
 237
 238#if !defined(CONFIG_USER_ONLY)
 239/* Software TLB cache */
 240typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 241struct ppc6xx_tlb_t {
 242    target_ulong pte0;
 243    target_ulong pte1;
 244    target_ulong EPN;
 245};
 246
 247typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 248struct ppcemb_tlb_t {
 249    uint64_t RPN;
 250    target_ulong EPN;
 251    target_ulong PID;
 252    target_ulong size;
 253    uint32_t prot;
 254    uint32_t attr; /* Storage attributes */
 255};
 256
 257typedef struct ppcmas_tlb_t {
 258     uint32_t mas8;
 259     uint32_t mas1;
 260     uint64_t mas2;
 261     uint64_t mas7_3;
 262} ppcmas_tlb_t;
 263
 264union ppc_tlb_t {
 265    ppc6xx_tlb_t *tlb6;
 266    ppcemb_tlb_t *tlbe;
 267    ppcmas_tlb_t *tlbm;
 268};
 269
 270/* possible TLB variants */
 271#define TLB_NONE               0
 272#define TLB_6XX                1
 273#define TLB_EMB                2
 274#define TLB_MAS                3
 275#endif
 276
 277typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
 278
 279typedef struct ppc_slb_t ppc_slb_t;
 280struct ppc_slb_t {
 281    uint64_t esid;
 282    uint64_t vsid;
 283    const PPCHash64SegmentPageSizes *sps;
 284};
 285
 286#define MAX_SLB_ENTRIES         64
 287#define SEGMENT_SHIFT_256M      28
 288#define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 289
 290#define SEGMENT_SHIFT_1T        40
 291#define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 292
 293typedef struct ppc_v3_pate_t {
 294    uint64_t dw0;
 295    uint64_t dw1;
 296} ppc_v3_pate_t;
 297
 298/*****************************************************************************/
 299/* Machine state register bits definition                                    */
 300#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 301#define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 302#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 303#define MSR_HV   60 /* hypervisor state                               hflags */
 304#define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
 305#define MSR_TS1  33
 306#define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
 307#define MSR_CM   31 /* Computation mode for BookE                     hflags */
 308#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 309#define MSR_GS   28 /* guest state for BookE                                 */
 310#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 311#define MSR_VR   25 /* altivec available                            x hflags */
 312#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 313#define MSR_AP   23 /* Access privilege state on 602                  hflags */
 314#define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
 315#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 316#define MSR_KEY  19 /* key bit on 603e                                       */
 317#define MSR_POW  18 /* Power management                                      */
 318#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 319#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 320#define MSR_ILE  16 /* Interrupt little-endian mode                          */
 321#define MSR_EE   15 /* External interrupt enable                             */
 322#define MSR_PR   14 /* Problem state                                  hflags */
 323#define MSR_FP   13 /* Floating point available                       hflags */
 324#define MSR_ME   12 /* Machine check interrupt enable                        */
 325#define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 326#define MSR_SE   10 /* Single-step trace enable                     x hflags */
 327#define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 328#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 329#define MSR_BE   9  /* Branch trace enable                          x hflags */
 330#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 331#define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 332#define MSR_AL   7  /* AL bit on POWER                                       */
 333#define MSR_EP   6  /* Exception prefix on 601                               */
 334#define MSR_IR   5  /* Instruction relocate                                  */
 335#define MSR_DR   4  /* Data relocate                                         */
 336#define MSR_IS   5  /* Instruction address space (BookE)                     */
 337#define MSR_DS   4  /* Data address space (BookE)                            */
 338#define MSR_PE   3  /* Protection enable on 403                              */
 339#define MSR_PX   2  /* Protection exclusive on 403                  x        */
 340#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 341#define MSR_RI   1  /* Recoverable interrupt                        1        */
 342#define MSR_LE   0  /* Little-endian mode                           1 hflags */
 343
 344/* LPCR bits */
 345#define LPCR_VPM0         PPC_BIT(0)
 346#define LPCR_VPM1         PPC_BIT(1)
 347#define LPCR_ISL          PPC_BIT(2)
 348#define LPCR_KBV          PPC_BIT(3)
 349#define LPCR_DPFD_SHIFT   (63 - 11)
 350#define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
 351#define LPCR_VRMASD_SHIFT (63 - 16)
 352#define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
 353/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
 354#define LPCR_PECE_U_SHIFT (63 - 19)
 355#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
 356#define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
 357#define LPCR_RMLS_SHIFT   (63 - 37)
 358#define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
 359#define LPCR_ILE          PPC_BIT(38)
 360#define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
 361#define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
 362#define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
 363#define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
 364#define LPCR_HR           PPC_BIT(43) /* Host Radix */
 365#define LPCR_ONL          PPC_BIT(45)
 366#define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
 367#define LPCR_P7_PECE0     PPC_BIT(49)
 368#define LPCR_P7_PECE1     PPC_BIT(50)
 369#define LPCR_P7_PECE2     PPC_BIT(51)
 370#define LPCR_P8_PECE0     PPC_BIT(47)
 371#define LPCR_P8_PECE1     PPC_BIT(48)
 372#define LPCR_P8_PECE2     PPC_BIT(49)
 373#define LPCR_P8_PECE3     PPC_BIT(50)
 374#define LPCR_P8_PECE4     PPC_BIT(51)
 375/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
 376#define LPCR_PECE_L_SHIFT (63 - 51)
 377#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
 378#define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
 379#define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
 380#define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
 381#define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
 382#define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
 383#define LPCR_MER          PPC_BIT(52)
 384#define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
 385#define LPCR_TC           PPC_BIT(54)
 386#define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
 387#define LPCR_LPES0        PPC_BIT(60)
 388#define LPCR_LPES1        PPC_BIT(61)
 389#define LPCR_RMI          PPC_BIT(62)
 390#define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
 391#define LPCR_HDICE        PPC_BIT(63)
 392
 393/* PSSCR bits */
 394#define PSSCR_ESL         PPC_BIT(42) /* Enable State Loss */
 395#define PSSCR_EC          PPC_BIT(43) /* Exit Criterion */
 396
 397/* HFSCR bits */
 398#define HFSCR_MSGP     PPC_BIT(53) /* Privileged Message Send Facilities */
 399#define HFSCR_IC_MSGP  0xA
 400
 401#define msr_sf   ((env->msr >> MSR_SF)   & 1)
 402#define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 403#if defined(TARGET_PPC64)
 404#define msr_hv   ((env->msr >> MSR_HV)   & 1)
 405#else
 406#define msr_hv   (0)
 407#endif
 408#define msr_cm   ((env->msr >> MSR_CM)   & 1)
 409#define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 410#define msr_gs   ((env->msr >> MSR_GS)   & 1)
 411#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 412#define msr_vr   ((env->msr >> MSR_VR)   & 1)
 413#define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 414#define msr_ap   ((env->msr >> MSR_AP)   & 1)
 415#define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
 416#define msr_sa   ((env->msr >> MSR_SA)   & 1)
 417#define msr_key  ((env->msr >> MSR_KEY)  & 1)
 418#define msr_pow  ((env->msr >> MSR_POW)  & 1)
 419#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 420#define msr_ce   ((env->msr >> MSR_CE)   & 1)
 421#define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 422#define msr_ee   ((env->msr >> MSR_EE)   & 1)
 423#define msr_pr   ((env->msr >> MSR_PR)   & 1)
 424#define msr_fp   ((env->msr >> MSR_FP)   & 1)
 425#define msr_me   ((env->msr >> MSR_ME)   & 1)
 426#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 427#define msr_se   ((env->msr >> MSR_SE)   & 1)
 428#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 429#define msr_uble ((env->msr >> MSR_UBLE) & 1)
 430#define msr_be   ((env->msr >> MSR_BE)   & 1)
 431#define msr_de   ((env->msr >> MSR_DE)   & 1)
 432#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 433#define msr_al   ((env->msr >> MSR_AL)   & 1)
 434#define msr_ep   ((env->msr >> MSR_EP)   & 1)
 435#define msr_ir   ((env->msr >> MSR_IR)   & 1)
 436#define msr_dr   ((env->msr >> MSR_DR)   & 1)
 437#define msr_is   ((env->msr >> MSR_IS)   & 1)
 438#define msr_ds   ((env->msr >> MSR_DS)   & 1)
 439#define msr_pe   ((env->msr >> MSR_PE)   & 1)
 440#define msr_px   ((env->msr >> MSR_PX)   & 1)
 441#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 442#define msr_ri   ((env->msr >> MSR_RI)   & 1)
 443#define msr_le   ((env->msr >> MSR_LE)   & 1)
 444#define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 445#define msr_tm   ((env->msr >> MSR_TM)   & 1)
 446
 447#define DBCR0_ICMP (1 << 27)
 448#define DBCR0_BRT (1 << 26)
 449#define DBSR_ICMP (1 << 27)
 450#define DBSR_BRT (1 << 26)
 451
 452/* Hypervisor bit is more specific */
 453#if defined(TARGET_PPC64)
 454#define MSR_HVB (1ULL << MSR_HV)
 455#else
 456#define MSR_HVB (0ULL)
 457#endif
 458
 459/* DSISR */
 460#define DSISR_NOPTE              0x40000000
 461/* Not permitted by access authority of encoded access authority */
 462#define DSISR_PROTFAULT          0x08000000
 463#define DSISR_ISSTORE            0x02000000
 464/* Not permitted by virtual page class key protection */
 465#define DSISR_AMR                0x00200000
 466/* Unsupported Radix Tree Configuration */
 467#define DSISR_R_BADCONFIG        0x00080000
 468#define DSISR_ATOMIC_RC          0x00040000
 469/* Unable to translate address of (guest) pde or process/page table entry */
 470#define DSISR_PRTABLE_FAULT      0x00020000
 471
 472/* SRR1 error code fields */
 473
 474#define SRR1_NOPTE               DSISR_NOPTE
 475/* Not permitted due to no-execute or guard bit set */
 476#define SRR1_NOEXEC_GUARD        0x10000000
 477#define SRR1_PROTFAULT           DSISR_PROTFAULT
 478#define SRR1_IAMR                DSISR_AMR
 479
 480/* SRR1[42:45] wakeup fields for System Reset Interrupt */
 481
 482#define SRR1_WAKEMASK           0x003c0000 /* reason for wakeup */
 483
 484#define SRR1_WAKEHMI            0x00280000 /* Hypervisor maintenance */
 485#define SRR1_WAKEHVI            0x00240000 /* Hypervisor Virt. Interrupt (P9) */
 486#define SRR1_WAKEEE             0x00200000 /* External interrupt */
 487#define SRR1_WAKEDEC            0x00180000 /* Decrementer interrupt */
 488#define SRR1_WAKEDBELL          0x00140000 /* Privileged doorbell */
 489#define SRR1_WAKERESET          0x00100000 /* System reset */
 490#define SRR1_WAKEHDBELL         0x000c0000 /* Hypervisor doorbell */
 491#define SRR1_WAKESCOM           0x00080000 /* SCOM not in power-saving mode */
 492
 493/* SRR1[46:47] power-saving exit mode */
 494
 495#define SRR1_WAKESTATE          0x00030000 /* Powersave exit mask */
 496
 497#define SRR1_WS_HVLOSS          0x00030000 /* HV resources not maintained */
 498#define SRR1_WS_GPRLOSS         0x00020000 /* GPRs not maintained */
 499#define SRR1_WS_NOLOSS          0x00010000 /* All resources maintained */
 500
 501/* Facility Status and Control (FSCR) bits */
 502#define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
 503#define FSCR_TAR        (63 - 55) /* Target Address Register */
 504#define FSCR_SCV        (63 - 51) /* System call vectored */
 505/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
 506#define FSCR_IC_MASK    (0xFFULL)
 507#define FSCR_IC_POS     (63 - 7)
 508#define FSCR_IC_DSCR_SPR3   2
 509#define FSCR_IC_PMU         3
 510#define FSCR_IC_BHRB        4
 511#define FSCR_IC_TM          5
 512#define FSCR_IC_EBB         7
 513#define FSCR_IC_TAR         8
 514#define FSCR_IC_SCV        12
 515
 516/* Exception state register bits definition                                  */
 517#define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
 518#define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
 519#define ESR_PTR   PPC_BIT(38) /* Trap                                   */
 520#define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
 521#define ESR_ST    PPC_BIT(40) /* Store Operation                        */
 522#define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
 523#define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
 524#define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
 525#define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
 526#define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
 527#define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
 528#define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
 529#define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
 530#define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
 531#define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
 532#define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
 533
 534/* Transaction EXception And Summary Register bits                           */
 535#define TEXASR_FAILURE_PERSISTENT                (63 - 7)
 536#define TEXASR_DISALLOWED                        (63 - 8)
 537#define TEXASR_NESTING_OVERFLOW                  (63 - 9)
 538#define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
 539#define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
 540#define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
 541#define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
 542#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
 543#define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
 544#define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
 545#define TEXASR_ABORT                             (63 - 31)
 546#define TEXASR_SUSPENDED                         (63 - 32)
 547#define TEXASR_PRIVILEGE_HV                      (63 - 34)
 548#define TEXASR_PRIVILEGE_PR                      (63 - 35)
 549#define TEXASR_FAILURE_SUMMARY                   (63 - 36)
 550#define TEXASR_TFIAR_EXACT                       (63 - 37)
 551#define TEXASR_ROT                               (63 - 38)
 552#define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
 553
 554enum {
 555    POWERPC_FLAG_NONE     = 0x00000000,
 556    /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 557    POWERPC_FLAG_SPE      = 0x00000001,
 558    POWERPC_FLAG_VRE      = 0x00000002,
 559    /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 560    POWERPC_FLAG_TGPR     = 0x00000004,
 561    POWERPC_FLAG_CE       = 0x00000008,
 562    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 563    POWERPC_FLAG_SE       = 0x00000010,
 564    POWERPC_FLAG_DWE      = 0x00000020,
 565    POWERPC_FLAG_UBLE     = 0x00000040,
 566    /* Flag for MSR bit 9 signification (BE/DE)                              */
 567    POWERPC_FLAG_BE       = 0x00000080,
 568    POWERPC_FLAG_DE       = 0x00000100,
 569    /* Flag for MSR bit 2 signification (PX/PMM)                             */
 570    POWERPC_FLAG_PX       = 0x00000200,
 571    POWERPC_FLAG_PMM      = 0x00000400,
 572    /* Flag for special features                                             */
 573    /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 574    POWERPC_FLAG_RTC_CLK  = 0x00010000,
 575    POWERPC_FLAG_BUS_CLK  = 0x00020000,
 576    /* Has CFAR                                                              */
 577    POWERPC_FLAG_CFAR     = 0x00040000,
 578    /* Has VSX                                                               */
 579    POWERPC_FLAG_VSX      = 0x00080000,
 580    /* Has Transaction Memory (ISA 2.07)                                     */
 581    POWERPC_FLAG_TM       = 0x00100000,
 582    /* Has SCV (ISA 3.00)                                                    */
 583    POWERPC_FLAG_SCV      = 0x00200000,
 584};
 585
 586/*****************************************************************************/
 587/* Floating point status and control register                                */
 588#define FPSCR_DRN2   34 /* Decimal Floating-Point rounding control           */
 589#define FPSCR_DRN1   33 /* Decimal Floating-Point rounding control           */
 590#define FPSCR_DRN0   32 /* Decimal Floating-Point rounding control           */
 591#define FPSCR_FX     31 /* Floating-point exception summary                  */
 592#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 593#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 594#define FPSCR_OX     28 /* Floating-point overflow exception                 */
 595#define FPSCR_UX     27 /* Floating-point underflow exception                */
 596#define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 597#define FPSCR_XX     25 /* Floating-point inexact exception                  */
 598#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 599#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 600#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 601#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 602#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 603#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 604#define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 605#define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 606#define FPSCR_C      16 /* Floating-point result class descriptor            */
 607#define FPSCR_FL     15 /* Floating-point less than or negative              */
 608#define FPSCR_FG     14 /* Floating-point greater than or negative           */
 609#define FPSCR_FE     13 /* Floating-point equal or zero                      */
 610#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 611#define FPSCR_FPCC   12 /* Floating-point condition code                     */
 612#define FPSCR_FPRF   12 /* Floating-point result flags                       */
 613#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 614#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 615#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 616#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 617#define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 618#define FPSCR_UE     5  /* Floating-point underflow exception enable          */
 619#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 620#define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 621#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 622#define FPSCR_RN1    1
 623#define FPSCR_RN0    0  /* Floating-point rounding control                   */
 624#define fpscr_drn    (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
 625#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 626#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 627#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 628#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 629#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 630#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 631#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 632#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 633#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 634#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 635#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 636#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 637#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 638#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 639#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 640#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 641#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 642#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 643#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 644#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 645#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 646#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 647#define fpscr_rn     (((env->fpscr) >> FPSCR_RN0)    & 0x3)
 648/* Invalid operation exception summary */
 649#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 650                                  (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 651                                  (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 652                                  (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 653                                  (1 << FPSCR_VXCVI)))
 654/* exception summary */
 655#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 656/* enabled exception summary */
 657#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 658                   0x1F)
 659
 660#define FP_DRN2         (1ull << FPSCR_DRN2)
 661#define FP_DRN1         (1ull << FPSCR_DRN1)
 662#define FP_DRN0         (1ull << FPSCR_DRN0)
 663#define FP_DRN          (FP_DRN2 | FP_DRN1 | FP_DRN0)
 664#define FP_FX           (1ull << FPSCR_FX)
 665#define FP_FEX          (1ull << FPSCR_FEX)
 666#define FP_VX           (1ull << FPSCR_VX)
 667#define FP_OX           (1ull << FPSCR_OX)
 668#define FP_UX           (1ull << FPSCR_UX)
 669#define FP_ZX           (1ull << FPSCR_ZX)
 670#define FP_XX           (1ull << FPSCR_XX)
 671#define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
 672#define FP_VXISI        (1ull << FPSCR_VXISI)
 673#define FP_VXIDI        (1ull << FPSCR_VXIDI)
 674#define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
 675#define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
 676#define FP_VXVC         (1ull << FPSCR_VXVC)
 677#define FP_FR           (1ull << FPSCR_FR)
 678#define FP_FI           (1ull << FPSCR_FI)
 679#define FP_C            (1ull << FPSCR_C)
 680#define FP_FL           (1ull << FPSCR_FL)
 681#define FP_FG           (1ull << FPSCR_FG)
 682#define FP_FE           (1ull << FPSCR_FE)
 683#define FP_FU           (1ull << FPSCR_FU)
 684#define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
 685#define FP_FPRF         (FP_C | FP_FPCC)
 686#define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
 687#define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
 688#define FP_VXCVI        (1ull << FPSCR_VXCVI)
 689#define FP_VE           (1ull << FPSCR_VE)
 690#define FP_OE           (1ull << FPSCR_OE)
 691#define FP_UE           (1ull << FPSCR_UE)
 692#define FP_ZE           (1ull << FPSCR_ZE)
 693#define FP_XE           (1ull << FPSCR_XE)
 694#define FP_NI           (1ull << FPSCR_NI)
 695#define FP_RN1          (1ull << FPSCR_RN1)
 696#define FP_RN0          (1ull << FPSCR_RN0)
 697#define FP_RN           (FP_RN1 | FP_RN0)
 698
 699#define FP_ENABLES      (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
 700#define FP_STATUS       (FP_FR | FP_FI | FP_FPRF)
 701
 702/* the exception bits which can be cleared by mcrfs - includes FX */
 703#define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
 704                          FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
 705                          FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
 706                          FP_VXSQRT | FP_VXCVI)
 707
 708/*****************************************************************************/
 709/* Vector status and control register */
 710#define VSCR_NJ         16 /* Vector non-java */
 711#define VSCR_SAT        0 /* Vector saturation */
 712
 713/*****************************************************************************/
 714/* BookE e500 MMU registers */
 715
 716#define MAS0_NV_SHIFT      0
 717#define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 718
 719#define MAS0_WQ_SHIFT      12
 720#define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 721/* Write TLB entry regardless of reservation */
 722#define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 723/* Write TLB entry only already in use */
 724#define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 725/* Clear TLB entry */
 726#define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 727
 728#define MAS0_HES_SHIFT     14
 729#define MAS0_HES           (1 << MAS0_HES_SHIFT)
 730
 731#define MAS0_ESEL_SHIFT    16
 732#define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 733
 734#define MAS0_TLBSEL_SHIFT  28
 735#define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 736#define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 737#define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 738#define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 739#define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 740
 741#define MAS0_ATSEL_SHIFT   31
 742#define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 743#define MAS0_ATSEL_TLB     0
 744#define MAS0_ATSEL_LRAT    MAS0_ATSEL
 745
 746#define MAS1_TSIZE_SHIFT   7
 747#define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 748
 749#define MAS1_TS_SHIFT      12
 750#define MAS1_TS            (1 << MAS1_TS_SHIFT)
 751
 752#define MAS1_IND_SHIFT     13
 753#define MAS1_IND           (1 << MAS1_IND_SHIFT)
 754
 755#define MAS1_TID_SHIFT     16
 756#define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 757
 758#define MAS1_IPROT_SHIFT   30
 759#define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 760
 761#define MAS1_VALID_SHIFT   31
 762#define MAS1_VALID         0x80000000
 763
 764#define MAS2_EPN_SHIFT     12
 765#define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 766
 767#define MAS2_ACM_SHIFT     6
 768#define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 769
 770#define MAS2_VLE_SHIFT     5
 771#define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 772
 773#define MAS2_W_SHIFT       4
 774#define MAS2_W             (1 << MAS2_W_SHIFT)
 775
 776#define MAS2_I_SHIFT       3
 777#define MAS2_I             (1 << MAS2_I_SHIFT)
 778
 779#define MAS2_M_SHIFT       2
 780#define MAS2_M             (1 << MAS2_M_SHIFT)
 781
 782#define MAS2_G_SHIFT       1
 783#define MAS2_G             (1 << MAS2_G_SHIFT)
 784
 785#define MAS2_E_SHIFT       0
 786#define MAS2_E             (1 << MAS2_E_SHIFT)
 787
 788#define MAS3_RPN_SHIFT     12
 789#define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 790
 791#define MAS3_U0                 0x00000200
 792#define MAS3_U1                 0x00000100
 793#define MAS3_U2                 0x00000080
 794#define MAS3_U3                 0x00000040
 795#define MAS3_UX                 0x00000020
 796#define MAS3_SX                 0x00000010
 797#define MAS3_UW                 0x00000008
 798#define MAS3_SW                 0x00000004
 799#define MAS3_UR                 0x00000002
 800#define MAS3_SR                 0x00000001
 801#define MAS3_SPSIZE_SHIFT       1
 802#define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 803
 804#define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 805#define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 806#define MAS4_TIDSELD_MASK       0x00030000
 807#define MAS4_TIDSELD_PID0       0x00000000
 808#define MAS4_TIDSELD_PID1       0x00010000
 809#define MAS4_TIDSELD_PID2       0x00020000
 810#define MAS4_TIDSELD_PIDZ       0x00030000
 811#define MAS4_INDD               0x00008000      /* Default IND */
 812#define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 813#define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 814#define MAS4_ACMD               0x00000040
 815#define MAS4_VLED               0x00000020
 816#define MAS4_WD                 0x00000010
 817#define MAS4_ID                 0x00000008
 818#define MAS4_MD                 0x00000004
 819#define MAS4_GD                 0x00000002
 820#define MAS4_ED                 0x00000001
 821#define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 822#define MAS4_WIMGED_SHIFT       0
 823
 824#define MAS5_SGS                0x80000000
 825#define MAS5_SLPID_MASK         0x00000fff
 826
 827#define MAS6_SPID0              0x3fff0000
 828#define MAS6_SPID1              0x00007ffe
 829#define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 830#define MAS6_SAS                0x00000001
 831#define MAS6_SPID               MAS6_SPID0
 832#define MAS6_SIND               0x00000002      /* Indirect page */
 833#define MAS6_SIND_SHIFT         1
 834#define MAS6_SPID_MASK          0x3fff0000
 835#define MAS6_SPID_SHIFT         16
 836#define MAS6_ISIZE_MASK         0x00000f80
 837#define MAS6_ISIZE_SHIFT        7
 838
 839#define MAS7_RPN                0xffffffff
 840
 841#define MAS8_TGS                0x80000000
 842#define MAS8_VF                 0x40000000
 843#define MAS8_TLBPID             0x00000fff
 844
 845/* Bit definitions for MMUCFG */
 846#define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 847#define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 848#define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 849#define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 850#define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 851#define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 852#define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 853#define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 854#define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 855
 856/* Bit definitions for MMUCSR0 */
 857#define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 858#define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 859#define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 860#define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 861#define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 862                         MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 863#define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 864#define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 865#define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 866#define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 867
 868/* TLBnCFG encoding */
 869#define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 870#define TLBnCFG_HES             0x00002000      /* HW select supported */
 871#define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 872#define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 873#define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 874#define TLBnCFG_IND             0x00020000      /* IND entries supported */
 875#define TLBnCFG_PT              0x00040000      /* Can load from page table */
 876#define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 877#define TLBnCFG_MINSIZE_SHIFT   20
 878#define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 879#define TLBnCFG_MAXSIZE_SHIFT   16
 880#define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 881#define TLBnCFG_ASSOC_SHIFT     24
 882
 883/* TLBnPS encoding */
 884#define TLBnPS_4K               0x00000004
 885#define TLBnPS_8K               0x00000008
 886#define TLBnPS_16K              0x00000010
 887#define TLBnPS_32K              0x00000020
 888#define TLBnPS_64K              0x00000040
 889#define TLBnPS_128K             0x00000080
 890#define TLBnPS_256K             0x00000100
 891#define TLBnPS_512K             0x00000200
 892#define TLBnPS_1M               0x00000400
 893#define TLBnPS_2M               0x00000800
 894#define TLBnPS_4M               0x00001000
 895#define TLBnPS_8M               0x00002000
 896#define TLBnPS_16M              0x00004000
 897#define TLBnPS_32M              0x00008000
 898#define TLBnPS_64M              0x00010000
 899#define TLBnPS_128M             0x00020000
 900#define TLBnPS_256M             0x00040000
 901#define TLBnPS_512M             0x00080000
 902#define TLBnPS_1G               0x00100000
 903#define TLBnPS_2G               0x00200000
 904#define TLBnPS_4G               0x00400000
 905#define TLBnPS_8G               0x00800000
 906#define TLBnPS_16G              0x01000000
 907#define TLBnPS_32G              0x02000000
 908#define TLBnPS_64G              0x04000000
 909#define TLBnPS_128G             0x08000000
 910#define TLBnPS_256G             0x10000000
 911
 912/* tlbilx action encoding */
 913#define TLBILX_T_ALL                    0
 914#define TLBILX_T_TID                    1
 915#define TLBILX_T_FULLMATCH              3
 916#define TLBILX_T_CLASS0                 4
 917#define TLBILX_T_CLASS1                 5
 918#define TLBILX_T_CLASS2                 6
 919#define TLBILX_T_CLASS3                 7
 920
 921/* BookE 2.06 helper defines */
 922
 923#define BOOKE206_FLUSH_TLB0    (1 << 0)
 924#define BOOKE206_FLUSH_TLB1    (1 << 1)
 925#define BOOKE206_FLUSH_TLB2    (1 << 2)
 926#define BOOKE206_FLUSH_TLB3    (1 << 3)
 927
 928/* number of possible TLBs */
 929#define BOOKE206_MAX_TLBN      4
 930
 931#define EPID_EPID_SHIFT 0x0
 932#define EPID_EPID 0xFF
 933#define EPID_ELPID_SHIFT 0x10
 934#define EPID_ELPID 0x3F0000
 935#define EPID_EGS 0x20000000
 936#define EPID_EGS_SHIFT 29
 937#define EPID_EAS 0x40000000
 938#define EPID_EAS_SHIFT 30
 939#define EPID_EPR 0x80000000
 940#define EPID_EPR_SHIFT 31
 941/* We don't support EGS and ELPID */
 942#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
 943
 944/*****************************************************************************/
 945/* Server and Embedded Processor Control */
 946
 947#define DBELL_TYPE_SHIFT               27
 948#define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 949#define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 950#define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 951#define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 952#define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 953#define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 954
 955#define DBELL_TYPE_DBELL_SERVER        (0x05 << DBELL_TYPE_SHIFT)
 956
 957#define DBELL_BRDCAST                  PPC_BIT(37)
 958#define DBELL_LPIDTAG_SHIFT            14
 959#define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 960#define DBELL_PIRTAG_MASK              0x3fff
 961
 962#define DBELL_PROCIDTAG_MASK           PPC_BITMASK(44, 63)
 963
 964#define PPC_PAGE_SIZES_MAX_SZ   8
 965
 966struct ppc_radix_page_info {
 967    uint32_t count;
 968    uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
 969};
 970
 971/*****************************************************************************/
 972/* The whole PowerPC CPU context */
 973
 974/*
 975 * PowerPC needs eight modes for different hypervisor/supervisor/guest
 976 * + real/paged mode combinations. The other two modes are for
 977 * external PID load/store.
 978 */
 979#define PPC_TLB_EPID_LOAD 8
 980#define PPC_TLB_EPID_STORE 9
 981
 982#define PPC_CPU_OPCODES_LEN          0x40
 983#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
 984
 985struct CPUPPCState {
 986    /* Most commonly used resources during translated code execution first */
 987    target_ulong gpr[32];  /* general purpose registers */
 988    target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
 989    target_ulong lr;
 990    target_ulong ctr;
 991    uint32_t crf[8];       /* condition register */
 992#if defined(TARGET_PPC64)
 993    target_ulong cfar;
 994#endif
 995    target_ulong xer;      /* XER (with SO, OV, CA split out) */
 996    target_ulong so;
 997    target_ulong ov;
 998    target_ulong ca;
 999    target_ulong ov32;
1000    target_ulong ca32;

1001
1002    target_ulong reserve_addr; /* Reservation address */
1003    target_ulong reserve_val;  /* Reservation value */
1004    target_ulong reserve_val2;
1005
1006    /* These are used in supervisor mode only */
1007    target_ulong msr;      /* machine state register */
1008    target_ulong tgpr[4];  /* temporary general purpose registers, */
1009                           /* used to speed-up TLB assist handlers */
1010
1011    target_ulong nip;      /* next instruction pointer */
1012    uint64_t retxh;        /* high part of 128-bit helper return */
1013
1014    /* when a memory exception occurs, the access type is stored here */
1015    int access_type;
1016
1017#if !defined(CONFIG_USER_ONLY)
1018    /* MMU context, only relevant for full system emulation */
1019#if defined(TARGET_PPC64)
1020    ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1021#endif
1022    target_ulong sr[32];   /* segment registers */
1023    uint32_t nb_BATs;      /* number of BATs */
1024    target_ulong DBAT[2][8];
1025    target_ulong IBAT[2][8];
1026    /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1027    int32_t nb_tlb;  /* Total number of TLB */
1028    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1029    int nb_ways;     /* Number of ways in the TLB set */
1030    int last_way;    /* Last used way used to allocate TLB in a LRU way */
1031    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1032    int nb_pids;     /* Number of available PID registers */
1033    int tlb_type;    /* Type of TLB we're dealing with */
1034    ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed */
1035    target_ulong pb[4]; /* 403 dedicated access protection registers */
1036    bool tlb_dirty;  /* Set to non-zero when modifying TLB */
1037    bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1038    uint32_t tlb_need_flush; /* Delayed flush needed */
1039#define TLB_NEED_LOCAL_FLUSH   0x1
1040#define TLB_NEED_GLOBAL_FLUSH  0x2
1041#endif
1042
1043    /* Other registers */
1044    target_ulong spr[1024]; /* special purpose registers */
1045    ppc_spr_t spr_cb[1024];
1046    /* Vector status and control register, minus VSCR_SAT */
1047    uint32_t vscr;
1048    /* VSX registers (including FP and AVR) */
1049    ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1050    /* Non-zero if and only if VSCR_SAT should be set */
1051    ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1052    /* SPE registers */
1053    uint64_t spe_acc;
1054    uint32_t spe_fscr;
1055    /* SPE and Altivec share status as they'll never be used simultaneously */
1056    float_status vec_status;
1057    float_status fp_status; /* Floating point execution context */
1058    target_ulong fpscr;     /* Floating point status and control register */
1059
1060    /* Internal devices resources */
1061    ppc_tb_t *tb_env;      /* Time base and decrementer */
1062    ppc_dcr_t *dcr_env;    /* Device control registers */
1063
1064    int dcache_line_size;
1065    int icache_line_size;
1066
1067    /* These resources are used during exception processing */
1068    /* CPU model definition */
1069    target_ulong msr_mask;
1070    powerpc_mmu_t mmu_model;
1071    powerpc_excp_t excp_model;
1072    powerpc_input_t bus_model;
1073    int bfd_mach;
1074    uint32_t flags;
1075    uint64_t insns_flags;
1076    uint64_t insns_flags2;
1077
1078    int error_code;
1079    uint32_t pending_interrupts;
1080#if !defined(CONFIG_USER_ONLY)
1081    /*
1082     * This is the IRQ controller, which is implementation dependent and only
1083     * relevant when emulating a complete machine. Note that this isn't used
1084     * by recent Book3s compatible CPUs (POWER7 and newer).
1085     */
1086    uint32_t irq_input_state;
1087    void **irq_inputs;
1088
1089    target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1090    target_ulong excp_prefix;
1091    target_ulong ivor_mask;
1092    target_ulong ivpr_mask;
1093    target_ulong hreset_vector;
1094    hwaddr mpic_iack;
1095    bool mpic_proxy;  /* true if the external proxy facility mode is enabled */
1096    bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1097                      /* instructions and SPRs are diallowed if MSR:HV is 0 */
1098    /*
1099     * On P7/P8/P9, set when in PM state so we need to handle resume in a
1100     * special way (such as routing some resume causes to 0x100, i.e. sreset).
1101     */
1102    bool resume_as_sreset;
1103#endif
1104
1105    /* These resources are used only in QEMU core */
1106    target_ulong hflags;      /* hflags is MSR & HFLAGS_MASK */
1107    target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1108    int immu_idx;     /* precomputed MMU index to speed up insn accesses */
1109    int dmmu_idx;     /* precomputed MMU index to speed up data accesses */
1110
1111    /* Power management */
1112    int (*check_pow)(CPUPPCState *env);
1113
1114#if !defined(CONFIG_USER_ONLY)
1115    void *load_info;  /* holds boot loading state */
1116#endif
1117
1118    /* booke timers */
1119
1120    /*
1121     * Specifies bit locations of the Time Base used to signal a fixed timer
1122     * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1123     *
1124     * 0 selects the least significant bit, 63 selects the most significant bit
1125     */
1126    uint8_t fit_period[4];
1127    uint8_t wdt_period[4];
1128
1129    /* Transactional memory state */
1130    target_ulong tm_gpr[32];
1131    ppc_avr_t tm_vsr[64];
1132    uint64_t tm_cr;
1133    uint64_t tm_lr;
1134    uint64_t tm_ctr;
1135    uint64_t tm_fpscr;
1136    uint64_t tm_amr;
1137    uint64_t tm_ppr;
1138    uint64_t tm_vrsave;
1139    uint32_t tm_vscr;
1140    uint64_t tm_dscr;
1141    uint64_t tm_tar;
1142};
1143
1144#define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1145do {                                            \
1146    env->fit_period[0] = (a_);                  \
1147    env->fit_period[1] = (b_);                  \
1148    env->fit_period[2] = (c_);                  \
1149    env->fit_period[3] = (d_);                  \
1150 } while (0)
1151
1152#define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1153do {                                            \
1154    env->wdt_period[0] = (a_);                  \
1155    env->wdt_period[1] = (b_);                  \
1156    env->wdt_period[2] = (c_);                  \
1157    env->wdt_period[3] = (d_);                  \
1158 } while (0)
1159
1160typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1161typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1162
1163/**
1164 * PowerPCCPU:
1165 * @env: #CPUPPCState
1166 * @vcpu_id: vCPU identifier given to KVM
1167 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1168 *
1169 * A PowerPC CPU.
1170 */
1171struct PowerPCCPU {
1172    /*< private >*/
1173    CPUState parent_obj;
1174    /*< public >*/
1175
1176    CPUNegativeOffsetState neg;
1177    CPUPPCState env;
1178
1179    int vcpu_id;
1180    uint32_t compat_pvr;
1181    PPCVirtualHypervisor *vhyp;
1182    void *machine_data;
1183    int32_t node_id; /* NUMA node this CPU belongs to */
1184    PPCHash64Options *hash64_opts;
1185
1186    /* Those resources are used only during code translation */
1187    /* opcode handlers */
1188    opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1189
1190    /* Fields related to migration compatibility hacks */
1191    bool pre_2_8_migration;
1192    target_ulong mig_msr_mask;
1193    uint64_t mig_insns_flags;
1194    uint64_t mig_insns_flags2;
1195    uint32_t mig_nb_BATs;
1196    bool pre_2_10_migration;
1197    bool pre_3_0_migration;
1198    int32_t mig_slb_nr;
1199};
1200
1201
1202PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1203PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1204PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1205
1206#ifndef CONFIG_USER_ONLY
1207struct PPCVirtualHypervisorClass {
1208    InterfaceClass parent;
1209    void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1210    hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1211    const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1212                                         hwaddr ptex, int n);
1213    void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1214                        const ppc_hash_pte64_t *hptes,
1215                        hwaddr ptex, int n);
1216    void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1217    void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1218    void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
1219    target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1220    void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1221    void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1222};
1223
1224#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1225DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1226                     PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1227#endif /* CONFIG_USER_ONLY */
1228
1229void ppc_cpu_do_interrupt(CPUState *cpu);
1230bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1231void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1232void ppc_cpu_dump_statistics(CPUState *cpu, int flags);
1233hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1234int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1235int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1236int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1237int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1238#ifndef CONFIG_USER_ONLY
1239void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1240const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1241#endif
1242int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1243                               int cpuid, void *opaque);
1244int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1245                               int cpuid, void *opaque);
1246#ifndef CONFIG_USER_ONLY
1247void ppc_cpu_do_system_reset(CPUState *cs);
1248void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1249extern const VMStateDescription vmstate_ppc_cpu;
1250#endif
1251
1252/*****************************************************************************/
1253void ppc_translate_init(void);
1254/*
1255 * you can call this signal handler from your SIGBUS and SIGSEGV
1256 * signal handlers to inform the virtual CPU of exceptions. non zero
1257 * is returned if the signal was handled by the virtual CPU.
1258 */
1259int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);
1260bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1261                      MMUAccessType access_type, int mmu_idx,
1262                      bool probe, uintptr_t retaddr);
1263
1264#if !defined(CONFIG_USER_ONLY)
1265void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1266void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
1267#endif /* !defined(CONFIG_USER_ONLY) */
1268void ppc_store_msr(CPUPPCState *env, target_ulong value);
1269
1270void ppc_cpu_list(void);
1271
1272/* Time-base and decrementer management */
1273#ifndef NO_CPU_IO_DEFS
1274uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1275uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1276void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1277void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1278uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1279uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1280void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1281void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1282uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1283void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1284bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1285target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1286void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1287target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1288void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1289void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1290uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1291void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1292uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
1293uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
1294#if !defined(CONFIG_USER_ONLY)
1295void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
1296void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
1297target_ulong load_40x_pit(CPUPPCState *env);
1298void store_40x_pit(CPUPPCState *env, target_ulong val);
1299void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1300void store_40x_sler(CPUPPCState *env, uint32_t val);
1301void store_booke_tcr(CPUPPCState *env, target_ulong val);
1302void store_booke_tsr(CPUPPCState *env, target_ulong val);
1303void ppc_tlb_invalidate_all(CPUPPCState *env);
1304void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1305void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1306#endif
1307#endif
1308
1309void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1310void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1311                                 const char *caller, uint32_t cause);
1312
1313static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1314{
1315    uint64_t gprv;
1316
1317    gprv = env->gpr[gprn];
1318    if (env->flags & POWERPC_FLAG_SPE) {
1319        /*
1320         * If the CPU implements the SPE extension, we have to get the
1321         * high bits of the GPR from the gprh storage area
1322         */
1323        gprv &= 0xFFFFFFFFULL;
1324        gprv |= (uint64_t)env->gprh[gprn] << 32;
1325    }
1326
1327    return gprv;
1328}
1329
1330/* Device control registers */
1331int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1332int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1333
1334#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1335#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1336#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1337
1338#define cpu_signal_handler cpu_ppc_signal_handler
1339#define cpu_list ppc_cpu_list
1340
1341/* MMU modes definitions */
1342#define MMU_USER_IDX 0
1343static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
1344{
1345    return ifetch ? env->immu_idx : env->dmmu_idx;
1346}
1347
1348/* Compatibility modes */
1349#if defined(TARGET_PPC64)
1350bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1351                      uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1352bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1353                           uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1354
1355int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1356
1357#if !defined(CONFIG_USER_ONLY)
1358int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1359#endif
1360int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1361void ppc_compat_add_property(Object *obj, const char *name,
1362                             uint32_t *compat_pvr, const char *basedesc);
1363#endif /* defined(TARGET_PPC64) */
1364
1365typedef CPUPPCState CPUArchState;
1366typedef PowerPCCPU ArchCPU;
1367
1368#include "exec/cpu-all.h"
1369
1370/*****************************************************************************/
1371/* CRF definitions */
1372#define CRF_LT_BIT    3
1373#define CRF_GT_BIT    2
1374#define CRF_EQ_BIT    1
1375#define CRF_SO_BIT    0
1376#define CRF_LT        (1 << CRF_LT_BIT)
1377#define CRF_GT        (1 << CRF_GT_BIT)
1378#define CRF_EQ        (1 << CRF_EQ_BIT)
1379#define CRF_SO        (1 << CRF_SO_BIT)
1380/* For SPE extensions */
1381#define CRF_CH        (1 << CRF_LT_BIT)
1382#define CRF_CL        (1 << CRF_GT_BIT)
1383#define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1384#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1385
1386/* XER definitions */
1387#define XER_SO  31
1388#define XER_OV  30
1389#define XER_CA  29
1390#define XER_OV32  19
1391#define XER_CA32  18
1392#define XER_CMP  8
1393#define XER_BC   0
1394#define xer_so  (env->so)
1395#define xer_ov  (env->ov)
1396#define xer_ca  (env->ca)
1397#define xer_ov32  (env->ov)
1398#define xer_ca32  (env->ca)
1399#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1400#define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1401
1402/* SPR definitions */
1403#define SPR_MQ                (0x000)
1404#define SPR_XER               (0x001)
1405#define SPR_601_VRTCU         (0x004)
1406#define SPR_601_VRTCL         (0x005)
1407#define SPR_601_UDECR         (0x006)
1408#define SPR_LR                (0x008)
1409#define SPR_CTR               (0x009)
1410#define SPR_UAMR              (0x00D)
1411#define SPR_DSCR              (0x011)
1412#define SPR_DSISR             (0x012)
1413#define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1414#define SPR_601_RTCU          (0x014)
1415#define SPR_601_RTCL          (0x015)
1416#define SPR_DECR              (0x016)
1417#define SPR_SDR1              (0x019)
1418#define SPR_SRR0              (0x01A)
1419#define SPR_SRR1              (0x01B)
1420#define SPR_CFAR              (0x01C)
1421#define SPR_AMR               (0x01D)
1422#define SPR_ACOP              (0x01F)
1423#define SPR_BOOKE_PID         (0x030)
1424#define SPR_BOOKS_PID         (0x030)
1425#define SPR_BOOKE_DECAR       (0x036)
1426#define SPR_BOOKE_CSRR0       (0x03A)
1427#define SPR_BOOKE_CSRR1       (0x03B)
1428#define SPR_BOOKE_DEAR        (0x03D)
1429#define SPR_IAMR              (0x03D)
1430#define SPR_BOOKE_ESR         (0x03E)
1431#define SPR_BOOKE_IVPR        (0x03F)
1432#define SPR_MPC_EIE           (0x050)
1433#define SPR_MPC_EID           (0x051)
1434#define SPR_MPC_NRI           (0x052)
1435#define SPR_TFHAR             (0x080)
1436#define SPR_TFIAR             (0x081)
1437#define SPR_TEXASR            (0x082)
1438#define SPR_TEXASRU           (0x083)
1439#define SPR_UCTRL             (0x088)
1440#define SPR_TIDR              (0x090)
1441#define SPR_MPC_CMPA          (0x090)
1442#define SPR_MPC_CMPB          (0x091)
1443#define SPR_MPC_CMPC          (0x092)
1444#define SPR_MPC_CMPD          (0x093)
1445#define SPR_MPC_ECR           (0x094)
1446#define SPR_MPC_DER           (0x095)
1447#define SPR_MPC_COUNTA        (0x096)
1448#define SPR_MPC_COUNTB        (0x097)
1449#define SPR_CTRL              (0x098)
1450#define SPR_MPC_CMPE          (0x098)
1451#define SPR_MPC_CMPF          (0x099)
1452#define SPR_FSCR              (0x099)
1453#define SPR_MPC_CMPG          (0x09A)
1454#define SPR_MPC_CMPH          (0x09B)
1455#define SPR_MPC_LCTRL1        (0x09C)
1456#define SPR_MPC_LCTRL2        (0x09D)
1457#define SPR_UAMOR             (0x09D)
1458#define SPR_MPC_ICTRL         (0x09E)
1459#define SPR_MPC_BAR           (0x09F)
1460#define SPR_PSPB              (0x09F)
1461#define SPR_DPDES             (0x0B0)
1462#define SPR_DAWR              (0x0B4)
1463#define SPR_RPR               (0x0BA)
1464#define SPR_CIABR             (0x0BB)
1465#define SPR_DAWRX             (0x0BC)
1466#define SPR_HFSCR             (0x0BE)
1467#define SPR_VRSAVE            (0x100)
1468#define SPR_USPRG0            (0x100)
1469#define SPR_USPRG1            (0x101)
1470#define SPR_USPRG2            (0x102)
1471#define SPR_USPRG3            (0x103)
1472#define SPR_USPRG4            (0x104)
1473#define SPR_USPRG5            (0x105)
1474#define SPR_USPRG6            (0x106)
1475#define SPR_USPRG7            (0x107)
1476#define SPR_VTBL              (0x10C)
1477#define SPR_VTBU              (0x10D)
1478#define SPR_SPRG0             (0x110)
1479#define SPR_SPRG1             (0x111)
1480#define SPR_SPRG2             (0x112)
1481#define SPR_SPRG3             (0x113)
1482#define SPR_SPRG4             (0x114)
1483#define SPR_SCOMC             (0x114)
1484#define SPR_SPRG5             (0x115)
1485#define SPR_SCOMD             (0x115)
1486#define SPR_SPRG6             (0x116)
1487#define SPR_SPRG7             (0x117)
1488#define SPR_ASR               (0x118)
1489#define SPR_EAR               (0x11A)
1490#define SPR_TBL               (0x11C)
1491#define SPR_TBU               (0x11D)
1492#define SPR_TBU40             (0x11E)
1493#define SPR_SVR               (0x11E)
1494#define SPR_BOOKE_PIR         (0x11E)
1495#define SPR_PVR               (0x11F)
1496#define SPR_HSPRG0            (0x130)
1497#define SPR_BOOKE_DBSR        (0x130)
1498#define SPR_HSPRG1            (0x131)
1499#define SPR_HDSISR            (0x132)
1500#define SPR_HDAR              (0x133)
1501#define SPR_BOOKE_EPCR        (0x133)
1502#define SPR_SPURR             (0x134)
1503#define SPR_BOOKE_DBCR0       (0x134)
1504#define SPR_IBCR              (0x135)
1505#define SPR_PURR              (0x135)
1506#define SPR_BOOKE_DBCR1       (0x135)
1507#define SPR_DBCR              (0x136)
1508#define SPR_HDEC              (0x136)
1509#define SPR_BOOKE_DBCR2       (0x136)
1510#define SPR_HIOR              (0x137)
1511#define SPR_MBAR              (0x137)
1512#define SPR_RMOR              (0x138)
1513#define SPR_BOOKE_IAC1        (0x138)
1514#define SPR_HRMOR             (0x139)
1515#define SPR_BOOKE_IAC2        (0x139)
1516#define SPR_HSRR0             (0x13A)
1517#define SPR_BOOKE_IAC3        (0x13A)
1518#define SPR_HSRR1             (0x13B)
1519#define SPR_BOOKE_IAC4        (0x13B)
1520#define SPR_BOOKE_DAC1        (0x13C)
1521#define SPR_MMCRH             (0x13C)
1522#define SPR_DABR2             (0x13D)
1523#define SPR_BOOKE_DAC2        (0x13D)
1524#define SPR_TFMR              (0x13D)
1525#define SPR_BOOKE_DVC1        (0x13E)
1526#define SPR_LPCR              (0x13E)
1527#define SPR_BOOKE_DVC2        (0x13F)
1528#define SPR_LPIDR             (0x13F)
1529#define SPR_BOOKE_TSR         (0x150)
1530#define SPR_HMER              (0x150)
1531#define SPR_HMEER             (0x151)
1532#define SPR_PCR               (0x152)
1533#define SPR_BOOKE_LPIDR       (0x152)
1534#define SPR_BOOKE_TCR         (0x154)
1535#define SPR_BOOKE_TLB0PS      (0x158)
1536#define SPR_BOOKE_TLB1PS      (0x159)
1537#define SPR_BOOKE_TLB2PS      (0x15A)
1538#define SPR_BOOKE_TLB3PS      (0x15B)
1539#define SPR_AMOR              (0x15D)
1540#define SPR_BOOKE_MAS7_MAS3   (0x174)
1541#define SPR_BOOKE_IVOR0       (0x190)
1542#define SPR_BOOKE_IVOR1       (0x191)
1543#define SPR_BOOKE_IVOR2       (0x192)
1544#define SPR_BOOKE_IVOR3       (0x193)
1545#define SPR_BOOKE_IVOR4       (0x194)
1546#define SPR_BOOKE_IVOR5       (0x195)
1547#define SPR_BOOKE_IVOR6       (0x196)
1548#define SPR_BOOKE_IVOR7       (0x197)
1549#define SPR_BOOKE_IVOR8       (0x198)
1550#define SPR_BOOKE_IVOR9       (0x199)
1551#define SPR_BOOKE_IVOR10      (0x19A)
1552#define SPR_BOOKE_IVOR11      (0x19B)
1553#define SPR_BOOKE_IVOR12      (0x19C)
1554#define SPR_BOOKE_IVOR13      (0x19D)
1555#define SPR_BOOKE_IVOR14      (0x19E)
1556#define SPR_BOOKE_IVOR15      (0x19F)
1557#define SPR_BOOKE_IVOR38      (0x1B0)
1558#define SPR_BOOKE_IVOR39      (0x1B1)
1559#define SPR_BOOKE_IVOR40      (0x1B2)
1560#define SPR_BOOKE_IVOR41      (0x1B3)
1561#define SPR_BOOKE_IVOR42      (0x1B4)
1562#define SPR_BOOKE_GIVOR2      (0x1B8)
1563#define SPR_BOOKE_GIVOR3      (0x1B9)
1564#define SPR_BOOKE_GIVOR4      (0x1BA)
1565#define SPR_BOOKE_GIVOR8      (0x1BB)
1566#define SPR_BOOKE_GIVOR13     (0x1BC)
1567#define SPR_BOOKE_GIVOR14     (0x1BD)
1568#define SPR_TIR               (0x1BE)
1569#define SPR_PTCR              (0x1D0)
1570#define SPR_BOOKE_SPEFSCR     (0x200)
1571#define SPR_Exxx_BBEAR        (0x201)
1572#define SPR_Exxx_BBTAR        (0x202)
1573#define SPR_Exxx_L1CFG0       (0x203)
1574#define SPR_Exxx_L1CFG1       (0x204)
1575#define SPR_Exxx_NPIDR        (0x205)
1576#define SPR_ATBL              (0x20E)
1577#define SPR_ATBU              (0x20F)
1578#define SPR_IBAT0U            (0x210)
1579#define SPR_BOOKE_IVOR32      (0x210)
1580#define SPR_RCPU_MI_GRA       (0x210)
1581#define SPR_IBAT0L            (0x211)
1582#define SPR_BOOKE_IVOR33      (0x211)
1583#define SPR_IBAT1U            (0x212)
1584#define SPR_BOOKE_IVOR34      (0x212)
1585#define SPR_IBAT1L            (0x213)
1586#define SPR_BOOKE_IVOR35      (0x213)
1587#define SPR_IBAT2U            (0x214)
1588#define SPR_BOOKE_IVOR36      (0x214)
1589#define SPR_IBAT2L            (0x215)
1590#define SPR_BOOKE_IVOR37      (0x215)
1591#define SPR_IBAT3U            (0x216)
1592#define SPR_IBAT3L            (0x217)
1593#define SPR_DBAT0U            (0x218)
1594#define SPR_RCPU_L2U_GRA      (0x218)
1595#define SPR_DBAT0L            (0x219)
1596#define SPR_DBAT1U            (0x21A)
1597#define SPR_DBAT1L            (0x21B)
1598#define SPR_DBAT2U            (0x21C)
1599#define SPR_DBAT2L            (0x21D)
1600#define SPR_DBAT3U            (0x21E)
1601#define SPR_DBAT3L            (0x21F)
1602#define SPR_IBAT4U            (0x230)
1603#define SPR_RPCU_BBCMCR       (0x230)
1604#define SPR_MPC_IC_CST        (0x230)
1605#define SPR_Exxx_CTXCR        (0x230)
1606#define SPR_IBAT4L            (0x231)
1607#define SPR_MPC_IC_ADR        (0x231)
1608#define SPR_Exxx_DBCR3        (0x231)
1609#define SPR_IBAT5U            (0x232)
1610#define SPR_MPC_IC_DAT        (0x232)
1611#define SPR_Exxx_DBCNT        (0x232)
1612#define SPR_IBAT5L            (0x233)
1613#define SPR_IBAT6U            (0x234)
1614#define SPR_IBAT6L            (0x235)
1615#define SPR_IBAT7U            (0x236)
1616#define SPR_IBAT7L            (0x237)
1617#define SPR_DBAT4U            (0x238)
1618#define SPR_RCPU_L2U_MCR      (0x238)
1619#define SPR_MPC_DC_CST        (0x238)
1620#define SPR_Exxx_ALTCTXCR     (0x238)
1621#define SPR_DBAT4L            (0x239)
1622#define SPR_MPC_DC_ADR        (0x239)
1623#define SPR_DBAT5U            (0x23A)
1624#define SPR_BOOKE_MCSRR0      (0x23A)
1625#define SPR_MPC_DC_DAT        (0x23A)
1626#define SPR_DBAT5L            (0x23B)
1627#define SPR_BOOKE_MCSRR1      (0x23B)
1628#define SPR_DBAT6U            (0x23C)
1629#define SPR_BOOKE_MCSR        (0x23C)
1630#define SPR_DBAT6L            (0x23D)
1631#define SPR_Exxx_MCAR         (0x23D)
1632#define SPR_DBAT7U            (0x23E)
1633#define SPR_BOOKE_DSRR0       (0x23E)
1634#define SPR_DBAT7L            (0x23F)
1635#define SPR_BOOKE_DSRR1       (0x23F)
1636#define SPR_BOOKE_SPRG8       (0x25C)
1637#define SPR_BOOKE_SPRG9       (0x25D)
1638#define SPR_BOOKE_MAS0        (0x270)
1639#define SPR_BOOKE_MAS1        (0x271)
1640#define SPR_BOOKE_MAS2        (0x272)
1641#define SPR_BOOKE_MAS3        (0x273)
1642#define SPR_BOOKE_MAS4        (0x274)
1643#define SPR_BOOKE_MAS5        (0x275)
1644#define SPR_BOOKE_MAS6        (0x276)
1645#define SPR_BOOKE_PID1        (0x279)
1646#define SPR_BOOKE_PID2        (0x27A)
1647#define SPR_MPC_DPDR          (0x280)
1648#define SPR_MPC_IMMR          (0x288)
1649#define SPR_BOOKE_TLB0CFG     (0x2B0)
1650#define SPR_BOOKE_TLB1CFG     (0x2B1)
1651#define SPR_BOOKE_TLB2CFG     (0x2B2)
1652#define SPR_BOOKE_TLB3CFG     (0x2B3)
1653#define SPR_BOOKE_EPR         (0x2BE)
1654#define SPR_PERF0             (0x300)
1655#define SPR_RCPU_MI_RBA0      (0x300)
1656#define SPR_MPC_MI_CTR        (0x300)
1657#define SPR_POWER_USIER       (0x300)
1658#define SPR_PERF1             (0x301)
1659#define SPR_RCPU_MI_RBA1      (0x301)
1660#define SPR_POWER_UMMCR2      (0x301)
1661#define SPR_PERF2             (0x302)
1662#define SPR_RCPU_MI_RBA2      (0x302)
1663#define SPR_MPC_MI_AP         (0x302)
1664#define SPR_POWER_UMMCRA      (0x302)
1665#define SPR_PERF3             (0x303)
1666#define SPR_RCPU_MI_RBA3      (0x303)
1667#define SPR_MPC_MI_EPN        (0x303)
1668#define SPR_POWER_UPMC1       (0x303)
1669#define SPR_PERF4             (0x304)
1670#define SPR_POWER_UPMC2       (0x304)
1671#define SPR_PERF5             (0x305)
1672#define SPR_MPC_MI_TWC        (0x305)
1673#define SPR_POWER_UPMC3       (0x305)
1674#define SPR_PERF6             (0x306)
1675#define SPR_MPC_MI_RPN        (0x306)
1676#define SPR_POWER_UPMC4       (0x306)
1677#define SPR_PERF7             (0x307)
1678#define SPR_POWER_UPMC5       (0x307)
1679#define SPR_PERF8             (0x308)
1680#define SPR_RCPU_L2U_RBA0     (0x308)
1681#define SPR_MPC_MD_CTR        (0x308)
1682#define SPR_POWER_UPMC6       (0x308)
1683#define SPR_PERF9             (0x309)
1684#define SPR_RCPU_L2U_RBA1     (0x309)
1685#define SPR_MPC_MD_CASID      (0x309)
1686#define SPR_970_UPMC7         (0X309)
1687#define SPR_PERFA             (0x30A)
1688#define SPR_RCPU_L2U_RBA2     (0x30A)
1689#define SPR_MPC_MD_AP         (0x30A)
1690#define SPR_970_UPMC8         (0X30A)
1691#define SPR_PERFB             (0x30B)
1692#define SPR_RCPU_L2U_RBA3     (0x30B)
1693#define SPR_MPC_MD_EPN        (0x30B)
1694#define SPR_POWER_UMMCR0      (0X30B)
1695#define SPR_PERFC             (0x30C)
1696#define SPR_MPC_MD_TWB        (0x30C)
1697#define SPR_POWER_USIAR       (0X30C)
1698#define SPR_PERFD             (0x30D)
1699#define SPR_MPC_MD_TWC        (0x30D)
1700#define SPR_POWER_USDAR       (0X30D)
1701#define SPR_PERFE             (0x30E)
1702#define SPR_MPC_MD_RPN        (0x30E)
1703#define SPR_POWER_UMMCR1      (0X30E)
1704#define SPR_PERFF             (0x30F)
1705#define SPR_MPC_MD_TW         (0x30F)
1706#define SPR_UPERF0            (0x310)
1707#define SPR_POWER_SIER        (0x310)
1708#define SPR_UPERF1            (0x311)
1709#define SPR_POWER_MMCR2       (0x311)
1710#define SPR_UPERF2            (0x312)
1711#define SPR_POWER_MMCRA       (0X312)
1712#define SPR_UPERF3            (0x313)
1713#define SPR_POWER_PMC1        (0X313)
1714#define SPR_UPERF4            (0x314)
1715#define SPR_POWER_PMC2        (0X314)
1716#define SPR_UPERF5            (0x315)
1717#define SPR_POWER_PMC3        (0X315)
1718#define SPR_UPERF6            (0x316)
1719#define SPR_POWER_PMC4        (0X316)
1720#define SPR_UPERF7            (0x317)
1721#define SPR_POWER_PMC5        (0X317)
1722#define SPR_UPERF8            (0x318)
1723#define SPR_POWER_PMC6        (0X318)
1724#define SPR_UPERF9            (0x319)
1725#define SPR_970_PMC7          (0X319)
1726#define SPR_UPERFA            (0x31A)
1727#define SPR_970_PMC8          (0X31A)
1728#define SPR_UPERFB            (0x31B)
1729#define SPR_POWER_MMCR0       (0X31B)
1730#define SPR_UPERFC            (0x31C)
1731#define SPR_POWER_SIAR        (0X31C)
1732#define SPR_UPERFD            (0x31D)
1733#define SPR_POWER_SDAR        (0X31D)
1734#define SPR_UPERFE            (0x31E)
1735#define SPR_POWER_MMCR1       (0X31E)
1736#define SPR_UPERFF            (0x31F)
1737#define SPR_RCPU_MI_RA0       (0x320)
1738#define SPR_MPC_MI_DBCAM      (0x320)
1739#define SPR_BESCRS            (0x320)
1740#define SPR_RCPU_MI_RA1       (0x321)
1741#define SPR_MPC_MI_DBRAM0     (0x321)
1742#define SPR_BESCRSU           (0x321)
1743#define SPR_RCPU_MI_RA2       (0x322)
1744#define SPR_MPC_MI_DBRAM1     (0x322)
1745#define SPR_BESCRR            (0x322)
1746#define SPR_RCPU_MI_RA3       (0x323)
1747#define SPR_BESCRRU           (0x323)
1748#define SPR_EBBHR             (0x324)
1749#define SPR_EBBRR             (0x325)
1750#define SPR_BESCR             (0x326)
1751#define SPR_RCPU_L2U_RA0      (0x328)
1752#define SPR_MPC_MD_DBCAM      (0x328)
1753#define SPR_RCPU_L2U_RA1      (0x329)
1754#define SPR_MPC_MD_DBRAM0     (0x329)
1755#define SPR_RCPU_L2U_RA2      (0x32A)
1756#define SPR_MPC_MD_DBRAM1     (0x32A)
1757#define SPR_RCPU_L2U_RA3      (0x32B)
1758#define SPR_TAR               (0x32F)
1759#define SPR_ASDR              (0x330)
1760#define SPR_IC                (0x350)
1761#define SPR_VTB               (0x351)
1762#define SPR_MMCRC             (0x353)
1763#define SPR_PSSCR             (0x357)
1764#define SPR_440_INV0          (0x370)
1765#define SPR_440_INV1          (0x371)
1766#define SPR_440_INV2          (0x372)
1767#define SPR_440_INV3          (0x373)
1768#define SPR_440_ITV0          (0x374)
1769#define SPR_440_ITV1          (0x375)
1770#define SPR_440_ITV2          (0x376)
1771#define SPR_440_ITV3          (0x377)
1772#define SPR_440_CCR1          (0x378)
1773#define SPR_TACR              (0x378)
1774#define SPR_TCSCR             (0x379)
1775#define SPR_CSIGR             (0x37a)
1776#define SPR_DCRIPR            (0x37B)
1777#define SPR_POWER_SPMC1       (0x37C)
1778#define SPR_POWER_SPMC2       (0x37D)
1779#define SPR_POWER_MMCRS       (0x37E)
1780#define SPR_WORT              (0x37F)
1781#define SPR_PPR               (0x380)
1782#define SPR_750_GQR0          (0x390)
1783#define SPR_440_DNV0          (0x390)
1784#define SPR_750_GQR1          (0x391)
1785#define SPR_440_DNV1          (0x391)
1786#define SPR_750_GQR2          (0x392)
1787#define SPR_440_DNV2          (0x392)
1788#define SPR_750_GQR3          (0x393)
1789#define SPR_440_DNV3          (0x393)
1790#define SPR_750_GQR4          (0x394)
1791#define SPR_440_DTV0          (0x394)
1792#define SPR_750_GQR5          (0x395)
1793#define SPR_440_DTV1          (0x395)
1794#define SPR_750_GQR6          (0x396)
1795#define SPR_440_DTV2          (0x396)
1796#define SPR_750_GQR7          (0x397)
1797#define SPR_440_DTV3          (0x397)
1798#define SPR_750_THRM4         (0x398)
1799#define SPR_750CL_HID2        (0x398)
1800#define SPR_440_DVLIM         (0x398)
1801#define SPR_750_WPAR          (0x399)
1802#define SPR_440_IVLIM         (0x399)
1803#define SPR_TSCR              (0x399)
1804#define SPR_750_DMAU          (0x39A)
1805#define SPR_750_DMAL          (0x39B)
1806#define SPR_440_RSTCFG        (0x39B)
1807#define SPR_BOOKE_DCDBTRL     (0x39C)
1808#define SPR_BOOKE_DCDBTRH     (0x39D)
1809#define SPR_BOOKE_ICDBTRL     (0x39E)
1810#define SPR_BOOKE_ICDBTRH     (0x39F)
1811#define SPR_74XX_UMMCR2       (0x3A0)
1812#define SPR_7XX_UPMC5         (0x3A1)
1813#define SPR_7XX_UPMC6         (0x3A2)
1814#define SPR_UBAMR             (0x3A7)
1815#define SPR_7XX_UMMCR0        (0x3A8)
1816#define SPR_7XX_UPMC1         (0x3A9)
1817#define SPR_7XX_UPMC2         (0x3AA)
1818#define SPR_7XX_USIAR         (0x3AB)
1819#define SPR_7XX_UMMCR1        (0x3AC)
1820#define SPR_7XX_UPMC3         (0x3AD)
1821#define SPR_7XX_UPMC4         (0x3AE)
1822#define SPR_USDA              (0x3AF)
1823#define SPR_40x_ZPR           (0x3B0)
1824#define SPR_BOOKE_MAS7        (0x3B0)
1825#define SPR_74XX_MMCR2        (0x3B0)
1826#define SPR_7XX_PMC5          (0x3B1)
1827#define SPR_40x_PID           (0x3B1)
1828#define SPR_7XX_PMC6          (0x3B2)
1829#define SPR_440_MMUCR         (0x3B2)
1830#define SPR_4xx_CCR0          (0x3B3)
1831#define SPR_BOOKE_EPLC        (0x3B3)
1832#define SPR_405_IAC3          (0x3B4)
1833#define SPR_BOOKE_EPSC        (0x3B4)
1834#define SPR_405_IAC4          (0x3B5)
1835#define SPR_405_DVC1          (0x3B6)
1836#define SPR_405_DVC2          (0x3B7)
1837#define SPR_BAMR              (0x3B7)
1838#define SPR_7XX_MMCR0         (0x3B8)
1839#define SPR_7XX_PMC1          (0x3B9)
1840#define SPR_40x_SGR           (0x3B9)
1841#define SPR_7XX_PMC2          (0x3BA)
1842#define SPR_40x_DCWR          (0x3BA)
1843#define SPR_7XX_SIAR          (0x3BB)
1844#define SPR_405_SLER          (0x3BB)
1845#define SPR_7XX_MMCR1         (0x3BC)
1846#define SPR_405_SU0R          (0x3BC)
1847#define SPR_401_SKR           (0x3BC)
1848#define SPR_7XX_PMC3          (0x3BD)
1849#define SPR_405_DBCR1         (0x3BD)
1850#define SPR_7XX_PMC4          (0x3BE)
1851#define SPR_SDA               (0x3BF)
1852#define SPR_403_VTBL          (0x3CC)
1853#define SPR_403_VTBU          (0x3CD)
1854#define SPR_DMISS             (0x3D0)
1855#define SPR_DCMP              (0x3D1)
1856#define SPR_HASH1             (0x3D2)
1857#define SPR_HASH2             (0x3D3)
1858#define SPR_BOOKE_ICDBDR      (0x3D3)
1859#define SPR_TLBMISS           (0x3D4)
1860#define SPR_IMISS             (0x3D4)
1861#define SPR_40x_ESR           (0x3D4)
1862#define SPR_PTEHI             (0x3D5)
1863#define SPR_ICMP              (0x3D5)
1864#define SPR_40x_DEAR          (0x3D5)
1865#define SPR_PTELO             (0x3D6)
1866#define SPR_RPA               (0x3D6)
1867#define SPR_40x_EVPR          (0x3D6)
1868#define SPR_L3PM              (0x3D7)
1869#define SPR_403_CDBCR         (0x3D7)
1870#define SPR_L3ITCR0           (0x3D8)
1871#define SPR_TCR               (0x3D8)
1872#define SPR_40x_TSR           (0x3D8)
1873#define SPR_IBR               (0x3DA)
1874#define SPR_40x_TCR           (0x3DA)
1875#define SPR_ESASRR            (0x3DB)
1876#define SPR_40x_PIT           (0x3DB)
1877#define SPR_403_TBL           (0x3DC)
1878#define SPR_403_TBU           (0x3DD)
1879#define SPR_SEBR              (0x3DE)
1880#define SPR_40x_SRR2          (0x3DE)
1881#define SPR_SER               (0x3DF)
1882#define SPR_40x_SRR3          (0x3DF)
1883#define SPR_L3OHCR            (0x3E8)
1884#define SPR_L3ITCR1           (0x3E9)
1885#define SPR_L3ITCR2           (0x3EA)
1886#define SPR_L3ITCR3           (0x3EB)
1887#define SPR_HID0              (0x3F0)
1888#define SPR_40x_DBSR          (0x3F0)
1889#define SPR_HID1              (0x3F1)
1890#define SPR_IABR              (0x3F2)
1891#define SPR_40x_DBCR0         (0x3F2)
1892#define SPR_601_HID2          (0x3F2)
1893#define SPR_Exxx_L1CSR0       (0x3F2)
1894#define SPR_ICTRL             (0x3F3)
1895#define SPR_HID2              (0x3F3)
1896#define SPR_750CL_HID4        (0x3F3)
1897#define SPR_Exxx_L1CSR1       (0x3F3)
1898#define SPR_440_DBDR          (0x3F3)
1899#define SPR_LDSTDB            (0x3F4)
1900#define SPR_750_TDCL          (0x3F4)
1901#define SPR_40x_IAC1          (0x3F4)
1902#define SPR_MMUCSR0           (0x3F4)
1903#define SPR_970_HID4          (0x3F4)
1904#define SPR_DABR              (0x3F5)
1905#define DABR_MASK (~(target_ulong)0x7)
1906#define SPR_Exxx_BUCSR        (0x3F5)
1907#define SPR_40x_IAC2          (0x3F5)
1908#define SPR_601_HID5          (0x3F5)
1909#define SPR_40x_DAC1          (0x3F6)
1910#define SPR_MSSCR0            (0x3F6)
1911#define SPR_970_HID5          (0x3F6)
1912#define SPR_MSSSR0            (0x3F7)
1913#define SPR_MSSCR1            (0x3F7)
1914#define SPR_DABRX             (0x3F7)
1915#define SPR_40x_DAC2          (0x3F7)
1916#define SPR_MMUCFG            (0x3F7)
1917#define SPR_LDSTCR            (0x3F8)
1918#define SPR_L2PMCR            (0x3F8)
1919#define SPR_750FX_HID2        (0x3F8)
1920#define SPR_Exxx_L1FINV0      (0x3F8)
1921#define SPR_L2CR              (0x3F9)
1922#define SPR_Exxx_L2CSR0       (0x3F9)
1923#define SPR_L3CR              (0x3FA)
1924#define SPR_750_TDCH          (0x3FA)
1925#define SPR_IABR2             (0x3FA)
1926#define SPR_40x_DCCR          (0x3FA)
1927#define SPR_ICTC              (0x3FB)
1928#define SPR_40x_ICCR          (0x3FB)
1929#define SPR_THRM1             (0x3FC)
1930#define SPR_403_PBL1          (0x3FC)
1931#define SPR_SP                (0x3FD)
1932#define SPR_THRM2             (0x3FD)
1933#define SPR_403_PBU1          (0x3FD)
1934#define SPR_604_HID13         (0x3FD)
1935#define SPR_LT                (0x3FE)
1936#define SPR_THRM3             (0x3FE)
1937#define SPR_RCPU_FPECR        (0x3FE)
1938#define SPR_403_PBL2          (0x3FE)
1939#define SPR_PIR               (0x3FF)
1940#define SPR_403_PBU2          (0x3FF)
1941#define SPR_601_HID15         (0x3FF)
1942#define SPR_604_HID15         (0x3FF)
1943#define SPR_E500_SVR          (0x3FF)
1944
1945/* Disable MAS Interrupt Updates for Hypervisor */
1946#define EPCR_DMIUH            (1 << 22)
1947/* Disable Guest TLB Management Instructions */
1948#define EPCR_DGTMI            (1 << 23)
1949/* Guest Interrupt Computation Mode */
1950#define EPCR_GICM             (1 << 24)
1951/* Interrupt Computation Mode */
1952#define EPCR_ICM              (1 << 25)
1953/* Disable Embedded Hypervisor Debug */
1954#define EPCR_DUVD             (1 << 26)
1955/* Instruction Storage Interrupt Directed to Guest State */
1956#define EPCR_ISIGS            (1 << 27)
1957/* Data Storage Interrupt Directed to Guest State */
1958#define EPCR_DSIGS            (1 << 28)
1959/* Instruction TLB Error Interrupt Directed to Guest State */
1960#define EPCR_ITLBGS           (1 << 29)
1961/* Data TLB Error Interrupt Directed to Guest State */
1962#define EPCR_DTLBGS           (1 << 30)
1963/* External Input Interrupt Directed to Guest State */
1964#define EPCR_EXTGS            (1 << 31)
1965
1966#define   L1CSR0_CPE    0x00010000  /* Data Cache Parity Enable */
1967#define   L1CSR0_CUL    0x00000400  /* (D-)Cache Unable to Lock */
1968#define   L1CSR0_DCLFR  0x00000100  /* D-Cache Lock Flash Reset */
1969#define   L1CSR0_DCFI   0x00000002  /* Data Cache Flash Invalidate */
1970#define   L1CSR0_DCE    0x00000001  /* Data Cache Enable */
1971
1972#define   L1CSR1_CPE    0x00010000  /* Instruction Cache Parity Enable */
1973#define   L1CSR1_ICUL   0x00000400  /* I-Cache Unable to Lock */
1974#define   L1CSR1_ICLFR  0x00000100  /* I-Cache Lock Flash Reset */
1975#define   L1CSR1_ICFI   0x00000002  /* Instruction Cache Flash Invalidate */
1976#define   L1CSR1_ICE    0x00000001  /* Instruction Cache Enable */
1977
1978/* E500 L2CSR0 */
1979#define E500_L2CSR0_L2FI    (1 << 21)   /* L2 cache flash invalidate */
1980#define E500_L2CSR0_L2FL    (1 << 11)   /* L2 cache flush */
1981#define E500_L2CSR0_L2LFC   (1 << 10)   /* L2 cache lock flash clear */
1982
1983/* HID0 bits */
1984#define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
1985#define HID0_DOZE           (1 << 23)           /* pre-2.06 */
1986#define HID0_NAP            (1 << 22)           /* pre-2.06 */
1987#define HID0_HILE           PPC_BIT(19) /* POWER8 */
1988#define HID0_POWER9_HILE    PPC_BIT(4)
1989
1990/*****************************************************************************/
1991/* PowerPC Instructions types definitions                                    */
1992enum {
1993    PPC_NONE           = 0x0000000000000000ULL,
1994    /* PowerPC base instructions set                                         */
1995    PPC_INSNS_BASE     = 0x0000000000000001ULL,
1996    /*   integer operations instructions                                     */
1997#define PPC_INTEGER PPC_INSNS_BASE
1998    /*   flow control instructions                                           */
1999#define PPC_FLOW    PPC_INSNS_BASE
2000    /*   virtual memory instructions                                         */

2001#define PPC_MEM     PPC_INSNS_BASE
2002    /*   ld/st with reservation instructions                                 */
2003#define PPC_RES     PPC_INSNS_BASE
2004    /*   spr/msr access instructions                                         */
2005#define PPC_MISC    PPC_INSNS_BASE
2006    /* Deprecated instruction sets                                           */
2007    /*   Original POWER instruction set                                      */
2008    PPC_POWER          = 0x0000000000000002ULL,
2009    /*   POWER2 instruction set extension                                    */
2010    PPC_POWER2         = 0x0000000000000004ULL,
2011    /*   Power RTC support                                                   */
2012    PPC_POWER_RTC      = 0x0000000000000008ULL,
2013    /*   Power-to-PowerPC bridge (601)                                       */
2014    PPC_POWER_BR       = 0x0000000000000010ULL,
2015    /* 64 bits PowerPC instruction set                                       */
2016    PPC_64B            = 0x0000000000000020ULL,
2017    /*   New 64 bits extensions (PowerPC 2.0x)                               */
2018    PPC_64BX           = 0x0000000000000040ULL,
2019    /*   64 bits hypervisor extensions                                       */
2020    PPC_64H            = 0x0000000000000080ULL,
2021    /*   New wait instruction (PowerPC 2.0x)                                 */
2022    PPC_WAIT           = 0x0000000000000100ULL,
2023    /*   Time base mftb instruction                                          */
2024    PPC_MFTB           = 0x0000000000000200ULL,
2025
2026    /* Fixed-point unit extensions                                           */
2027    /*   PowerPC 602 specific                                                */
2028    PPC_602_SPEC       = 0x0000000000000400ULL,
2029    /*   isel instruction                                                    */
2030    PPC_ISEL           = 0x0000000000000800ULL,
2031    /*   popcntb instruction                                                 */
2032    PPC_POPCNTB        = 0x0000000000001000ULL,
2033    /*   string load / store                                                 */
2034    PPC_STRING         = 0x0000000000002000ULL,
2035    /*   real mode cache inhibited load / store                              */
2036    PPC_CILDST         = 0x0000000000004000ULL,
2037
2038    /* Floating-point unit extensions                                        */
2039    /*   Optional floating point instructions                                */
2040    PPC_FLOAT          = 0x0000000000010000ULL,
2041    /* New floating-point extensions (PowerPC 2.0x)                          */
2042    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2043    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2044    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2045    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2046    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2047    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2048    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2049
2050    /* Vector/SIMD extensions                                                */
2051    /*   Altivec support                                                     */
2052    PPC_ALTIVEC        = 0x0000000001000000ULL,
2053    /*   PowerPC 2.03 SPE extension                                          */
2054    PPC_SPE            = 0x0000000002000000ULL,
2055    /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2056    PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2057    /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2058    PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2059
2060    /* Optional memory control instructions                                  */
2061    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2062    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2063    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2064    /*   sync instruction                                                    */
2065    PPC_MEM_SYNC       = 0x0000000080000000ULL,
2066    /*   eieio instruction                                                   */
2067    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2068
2069    /* Cache control instructions                                            */
2070    PPC_CACHE          = 0x0000000200000000ULL,
2071    /*   icbi instruction                                                    */
2072    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2073    /*   dcbz instruction                                                    */
2074    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2075    /*   dcba instruction                                                    */
2076    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2077    /*   Freescale cache locking instructions                                */
2078    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2079
2080    /* MMU related extensions                                                */
2081    /*   external control instructions                                       */
2082    PPC_EXTERN         = 0x0000010000000000ULL,
2083    /*   segment register access instructions                                */
2084    PPC_SEGMENT        = 0x0000020000000000ULL,
2085    /*   PowerPC 6xx TLB management instructions                             */
2086    PPC_6xx_TLB        = 0x0000040000000000ULL,
2087    /* PowerPC 74xx TLB management instructions                              */
2088    PPC_74xx_TLB       = 0x0000080000000000ULL,
2089    /*   PowerPC 40x TLB management instructions                             */
2090    PPC_40x_TLB        = 0x0000100000000000ULL,
2091    /*   segment register access instructions for PowerPC 64 "bridge"        */
2092    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2093    /*   SLB management                                                      */
2094    PPC_SLBI           = 0x0000400000000000ULL,
2095
2096    /* Embedded PowerPC dedicated instructions                               */
2097    PPC_WRTEE          = 0x0001000000000000ULL,
2098    /* PowerPC 40x exception model                                           */
2099    PPC_40x_EXCP       = 0x0002000000000000ULL,
2100    /* PowerPC 405 Mac instructions                                          */
2101    PPC_405_MAC        = 0x0004000000000000ULL,
2102    /* PowerPC 440 specific instructions                                     */
2103    PPC_440_SPEC       = 0x0008000000000000ULL,
2104    /* BookE (embedded) PowerPC specification                                */
2105    PPC_BOOKE          = 0x0010000000000000ULL,
2106    /* mfapidi instruction                                                   */
2107    PPC_MFAPIDI        = 0x0020000000000000ULL,
2108    /* tlbiva instruction                                                    */
2109    PPC_TLBIVA         = 0x0040000000000000ULL,
2110    /* tlbivax instruction                                                   */
2111    PPC_TLBIVAX        = 0x0080000000000000ULL,
2112    /* PowerPC 4xx dedicated instructions                                    */
2113    PPC_4xx_COMMON     = 0x0100000000000000ULL,
2114    /* PowerPC 40x ibct instructions                                         */
2115    PPC_40x_ICBT       = 0x0200000000000000ULL,
2116    /* rfmci is not implemented in all BookE PowerPC                         */
2117    PPC_RFMCI          = 0x0400000000000000ULL,
2118    /* rfdi instruction                                                      */
2119    PPC_RFDI           = 0x0800000000000000ULL,
2120    /* DCR accesses                                                          */
2121    PPC_DCR            = 0x1000000000000000ULL,
2122    /* DCR extended accesse                                                  */
2123    PPC_DCRX           = 0x2000000000000000ULL,
2124    /* user-mode DCR access, implemented in PowerPC 460                      */
2125    PPC_DCRUX          = 0x4000000000000000ULL,
2126    /* popcntw and popcntd instructions                                      */
2127    PPC_POPCNTWD       = 0x8000000000000000ULL,
2128
2129#define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2130                        | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2131                        | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2132                        | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2133                        | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2134                        | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2135                        | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2136                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2137                        | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2138                        | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2139                        | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2140                        | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2141                        | PPC_CACHE | PPC_CACHE_ICBI \
2142                        | PPC_CACHE_DCBZ \
2143                        | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2144                        | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2145                        | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2146                        | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2147                        | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2148                        | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2149                        | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2150                        | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2151                        | PPC_POPCNTWD | PPC_CILDST)
2152
2153    /* extended type values */
2154
2155    /* BookE 2.06 PowerPC specification                                      */
2156    PPC2_BOOKE206      = 0x0000000000000001ULL,
2157    /* VSX (extensions to Altivec / VMX)                                     */
2158    PPC2_VSX           = 0x0000000000000002ULL,
2159    /* Decimal Floating Point (DFP)                                          */
2160    PPC2_DFP           = 0x0000000000000004ULL,
2161    /* Embedded.Processor Control                                            */
2162    PPC2_PRCNTL        = 0x0000000000000008ULL,
2163    /* Byte-reversed, indexed, double-word load and store                    */
2164    PPC2_DBRX          = 0x0000000000000010ULL,
2165    /* Book I 2.05 PowerPC specification                                     */
2166    PPC2_ISA205        = 0x0000000000000020ULL,
2167    /* VSX additions in ISA 2.07                                             */
2168    PPC2_VSX207        = 0x0000000000000040ULL,
2169    /* ISA 2.06B bpermd                                                      */
2170    PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2171    /* ISA 2.06B divide extended variants                                    */
2172    PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2173    /* ISA 2.06B larx/stcx. instructions                                     */
2174    PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2175    /* ISA 2.06B floating point integer conversion                           */
2176    PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2177    /* ISA 2.06B floating point test instructions                            */
2178    PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2179    /* ISA 2.07 bctar instruction                                            */
2180    PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2181    /* ISA 2.07 load/store quadword                                          */
2182    PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2183    /* ISA 2.07 Altivec                                                      */
2184    PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2185    /* PowerISA 2.07 Book3s specification                                    */
2186    PPC2_ISA207S       = 0x0000000000008000ULL,
2187    /* Double precision floating point conversion for signed integer 64      */
2188    PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2189    /* Transactional Memory (ISA 2.07, Book II)                              */
2190    PPC2_TM            = 0x0000000000020000ULL,
2191    /* Server PM instructgions (ISA 2.06, Book III)                          */
2192    PPC2_PM_ISA206     = 0x0000000000040000ULL,
2193    /* POWER ISA 3.0                                                         */
2194    PPC2_ISA300        = 0x0000000000080000ULL,
2195    /* POWER ISA 3.1                                                         */
2196    PPC2_ISA310        = 0x0000000000100000ULL,
2197
2198#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2199                        PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2200                        PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2201                        PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2202                        PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2203                        PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2204                        PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2205                        PPC2_ISA300 | PPC2_ISA310)
2206};
2207
2208/*****************************************************************************/
2209/*
2210 * Memory access type :
2211 * may be needed for precise access rights control and precise exceptions.
2212 */
2213enum {
2214    /* Type of instruction that generated the access */
2215    ACCESS_CODE  = 0x10, /* Code fetch access                */
2216    ACCESS_INT   = 0x20, /* Integer load/store access        */
2217    ACCESS_FLOAT = 0x30, /* floating point load/store access */
2218    ACCESS_RES   = 0x40, /* load/store with reservation      */
2219    ACCESS_EXT   = 0x50, /* external access                  */
2220    ACCESS_CACHE = 0x60, /* Cache manipulation               */
2221};
2222
2223/*
2224 * Hardware interrupt sources:
2225 *   all those exception can be raised simulteaneously
2226 */
2227/* Input pins definitions */
2228enum {
2229    /* 6xx bus input pins */
2230    PPC6xx_INPUT_HRESET     = 0,
2231    PPC6xx_INPUT_SRESET     = 1,
2232    PPC6xx_INPUT_CKSTP_IN   = 2,
2233    PPC6xx_INPUT_MCP        = 3,
2234    PPC6xx_INPUT_SMI        = 4,
2235    PPC6xx_INPUT_INT        = 5,
2236    PPC6xx_INPUT_TBEN       = 6,
2237    PPC6xx_INPUT_WAKEUP     = 7,
2238    PPC6xx_INPUT_NB,
2239};
2240
2241enum {
2242    /* Embedded PowerPC input pins */
2243    PPCBookE_INPUT_HRESET     = 0,
2244    PPCBookE_INPUT_SRESET     = 1,
2245    PPCBookE_INPUT_CKSTP_IN   = 2,
2246    PPCBookE_INPUT_MCP        = 3,
2247    PPCBookE_INPUT_SMI        = 4,
2248    PPCBookE_INPUT_INT        = 5,
2249    PPCBookE_INPUT_CINT       = 6,
2250    PPCBookE_INPUT_NB,
2251};
2252
2253enum {
2254    /* PowerPC E500 input pins */
2255    PPCE500_INPUT_RESET_CORE = 0,
2256    PPCE500_INPUT_MCK        = 1,
2257    PPCE500_INPUT_CINT       = 3,
2258    PPCE500_INPUT_INT        = 4,
2259    PPCE500_INPUT_DEBUG      = 6,
2260    PPCE500_INPUT_NB,
2261};
2262
2263enum {
2264    /* PowerPC 40x input pins */
2265    PPC40x_INPUT_RESET_CORE = 0,
2266    PPC40x_INPUT_RESET_CHIP = 1,
2267    PPC40x_INPUT_RESET_SYS  = 2,
2268    PPC40x_INPUT_CINT       = 3,
2269    PPC40x_INPUT_INT        = 4,
2270    PPC40x_INPUT_HALT       = 5,
2271    PPC40x_INPUT_DEBUG      = 6,
2272    PPC40x_INPUT_NB,
2273};
2274
2275enum {
2276    /* RCPU input pins */
2277    PPCRCPU_INPUT_PORESET   = 0,
2278    PPCRCPU_INPUT_HRESET    = 1,
2279    PPCRCPU_INPUT_SRESET    = 2,
2280    PPCRCPU_INPUT_IRQ0      = 3,
2281    PPCRCPU_INPUT_IRQ1      = 4,
2282    PPCRCPU_INPUT_IRQ2      = 5,
2283    PPCRCPU_INPUT_IRQ3      = 6,
2284    PPCRCPU_INPUT_IRQ4      = 7,
2285    PPCRCPU_INPUT_IRQ5      = 8,
2286    PPCRCPU_INPUT_IRQ6      = 9,
2287    PPCRCPU_INPUT_IRQ7      = 10,
2288    PPCRCPU_INPUT_NB,
2289};
2290
2291#if defined(TARGET_PPC64)
2292enum {
2293    /* PowerPC 970 input pins */
2294    PPC970_INPUT_HRESET     = 0,
2295    PPC970_INPUT_SRESET     = 1,
2296    PPC970_INPUT_CKSTP      = 2,
2297    PPC970_INPUT_TBEN       = 3,
2298    PPC970_INPUT_MCP        = 4,
2299    PPC970_INPUT_INT        = 5,
2300    PPC970_INPUT_THINT      = 6,
2301    PPC970_INPUT_NB,
2302};
2303
2304enum {
2305    /* POWER7 input pins */
2306    POWER7_INPUT_INT        = 0,
2307    /*
2308     * POWER7 probably has other inputs, but we don't care about them
2309     * for any existing machine.  We can wire these up when we need
2310     * them
2311     */
2312    POWER7_INPUT_NB,
2313};
2314
2315enum {
2316    /* POWER9 input pins */
2317    POWER9_INPUT_INT        = 0,
2318    POWER9_INPUT_HINT       = 1,
2319    POWER9_INPUT_NB,
2320};
2321#endif
2322
2323/* Hardware exceptions definitions */
2324enum {
2325    /* External hardware exception sources */
2326    PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2327    PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2328    PPC_INTERRUPT_MCK,            /* Machine check exception              */
2329    PPC_INTERRUPT_EXT,            /* External interrupt                   */
2330    PPC_INTERRUPT_SMI,            /* System management interrupt          */
2331    PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2332    PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2333    PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2334    /* Internal hardware exception sources */
2335    PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2336    PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2337    PPC_INTERRUPT_PIT,            /* Programmable interval timer interrupt */
2338    PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2339    PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2340    PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2341    PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2342    PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2343    PPC_INTERRUPT_HMI,            /* Hypervisor Maintenance interrupt    */
2344    PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2345    PPC_INTERRUPT_HVIRT,          /* Hypervisor virtualization interrupt  */
2346};
2347
2348/* Processor Compatibility mask (PCR) */
2349enum {
2350    PCR_COMPAT_2_05     = PPC_BIT(62),
2351    PCR_COMPAT_2_06     = PPC_BIT(61),
2352    PCR_COMPAT_2_07     = PPC_BIT(60),
2353    PCR_COMPAT_3_00     = PPC_BIT(59),
2354    PCR_COMPAT_3_10     = PPC_BIT(58),
2355    PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2356    PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2357    PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2358};
2359
2360/* HMER/HMEER */
2361enum {
2362    HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
2363    HMER_PROC_RECV_DONE         = PPC_BIT(2),
2364    HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2365    HMER_TFAC_ERROR             = PPC_BIT(4),
2366    HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
2367    HMER_XSCOM_FAIL             = PPC_BIT(8),
2368    HMER_XSCOM_DONE             = PPC_BIT(9),
2369    HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
2370    HMER_WARN_RISE              = PPC_BIT(14),
2371    HMER_WARN_FALL              = PPC_BIT(15),
2372    HMER_SCOM_FIR_HMI           = PPC_BIT(16),
2373    HMER_TRIG_FIR_HMI           = PPC_BIT(17),
2374    HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
2375    HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
2376};
2377
2378/* Alternate Interrupt Location (AIL) */
2379enum {
2380    AIL_NONE                = 0,
2381    AIL_RESERVED            = 1,
2382    AIL_0001_8000           = 2,
2383    AIL_C000_0000_0000_4000 = 3,
2384};
2385
2386/*****************************************************************************/
2387
2388#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2389target_ulong cpu_read_xer(CPUPPCState *env);
2390void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2391
2392/*
2393 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2394 * have PPC_SEGMENT_64B.
2395 */
2396#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2397
2398static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2399                                        target_ulong *cs_base, uint32_t *flags)
2400{
2401    *pc = env->nip;
2402    *cs_base = 0;
2403    *flags = env->hflags;
2404}
2405
2406void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2407void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2408                                      uintptr_t raddr);
2409void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2410                                       uint32_t error_code);
2411void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2412                                          uint32_t error_code, uintptr_t raddr);
2413
2414#if !defined(CONFIG_USER_ONLY)
2415static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2416{
2417    uintptr_t tlbml = (uintptr_t)tlbm;
2418    uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2419
2420    return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2421}
2422
2423static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2424{
2425    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2426    int r = tlbncfg & TLBnCFG_N_ENTRY;
2427    return r;
2428}
2429
2430static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2431{
2432    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2433    int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2434    return r;
2435}
2436
2437static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2438{
2439    int id = booke206_tlbm_id(env, tlbm);
2440    int end = 0;
2441    int i;
2442
2443    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2444        end += booke206_tlb_size(env, i);
2445        if (id < end) {
2446            return i;
2447        }
2448    }
2449
2450    cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2451    return 0;
2452}
2453
2454static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2455{
2456    int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2457    int tlbid = booke206_tlbm_id(env, tlb);
2458    return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2459}
2460
2461static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2462                                              target_ulong ea, int way)
2463{
2464    int r;
2465    uint32_t ways = booke206_tlb_ways(env, tlbn);
2466    int ways_bits = ctz32(ways);
2467    int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2468    int i;
2469
2470    way &= ways - 1;
2471    ea >>= MAS2_EPN_SHIFT;
2472    ea &= (1 << (tlb_bits - ways_bits)) - 1;
2473    r = (ea << ways_bits) | way;
2474
2475    if (r >= booke206_tlb_size(env, tlbn)) {
2476        return NULL;
2477    }
2478
2479    /* bump up to tlbn index */
2480    for (i = 0; i < tlbn; i++) {
2481        r += booke206_tlb_size(env, i);
2482    }
2483
2484    return &env->tlb.tlbm[r];
2485}
2486
2487/* returns bitmap of supported page sizes for a given TLB */
2488static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2489{
2490    uint32_t ret = 0;
2491
2492    if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2493        /* MAV2 */
2494        ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2495    } else {
2496        uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2497        uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2498        uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2499        int i;
2500        for (i = min; i <= max; i++) {
2501            ret |= (1 << (i << 1));
2502        }
2503    }
2504
2505    return ret;
2506}
2507
2508static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2509                                            ppcmas_tlb_t *tlb)
2510{
2511    uint8_t i;
2512    int32_t tsize = -1;
2513
2514    for (i = 0; i < 32; i++) {
2515        if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2516            if (tsize == -1) {
2517                tsize = i;
2518            } else {
2519                return;
2520            }
2521        }
2522    }
2523
2524    /* TLBnPS unimplemented? Odd.. */
2525    assert(tsize != -1);
2526    tlb->mas1 &= ~MAS1_TSIZE_MASK;
2527    tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2528}
2529
2530#endif
2531
2532static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2533{
2534    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2535        return msr & (1ULL << MSR_CM);
2536    }
2537
2538    return msr & (1ULL << MSR_SF);
2539}
2540
2541/**
2542 * Check whether register rx is in the range between start and
2543 * start + nregs (as needed by the LSWX and LSWI instructions)
2544 */
2545static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2546{
2547    return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2548           (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2549}
2550
2551/* Accessors for FP, VMX and VSX registers */
2552#if defined(HOST_WORDS_BIGENDIAN)
2553#define VsrB(i) u8[i]
2554#define VsrSB(i) s8[i]
2555#define VsrH(i) u16[i]
2556#define VsrSH(i) s16[i]
2557#define VsrW(i) u32[i]
2558#define VsrSW(i) s32[i]
2559#define VsrD(i) u64[i]
2560#define VsrSD(i) s64[i]
2561#else
2562#define VsrB(i) u8[15 - (i)]
2563#define VsrSB(i) s8[15 - (i)]
2564#define VsrH(i) u16[7 - (i)]
2565#define VsrSH(i) s16[7 - (i)]
2566#define VsrW(i) u32[3 - (i)]
2567#define VsrSW(i) s32[3 - (i)]
2568#define VsrD(i) u64[1 - (i)]
2569#define VsrSD(i) s64[1 - (i)]
2570#endif
2571
2572static inline int vsr64_offset(int i, bool high)
2573{
2574    return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2575}
2576
2577static inline int vsr_full_offset(int i)
2578{
2579    return offsetof(CPUPPCState, vsr[i].u64[0]);
2580}
2581
2582static inline int fpr_offset(int i)
2583{
2584    return vsr64_offset(i, true);
2585}
2586
2587static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2588{
2589    return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2590}
2591
2592static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2593{
2594    return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2595}
2596
2597static inline long avr64_offset(int i, bool high)
2598{
2599    return vsr64_offset(i + 32, high);
2600}
2601
2602static inline int avr_full_offset(int i)
2603{
2604    return vsr_full_offset(i + 32);
2605}
2606
2607static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2608{
2609    return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2610}
2611
2612void dump_mmu(CPUPPCState *env);
2613
2614void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2615#endif /* PPC_CPU_H */
2616