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20#include "qemu/osdep.h"
21#include "qemu/qemu-print.h"
22#include "qemu/ctype.h"
23#include "qemu/log.h"
24#include "cpu.h"
25#include "internals.h"
26#include "exec/exec-all.h"
27#include "qapi/error.h"
28#include "qemu/error-report.h"
29#include "hw/qdev-properties.h"
30#include "migration/vmstate.h"
31#include "fpu/softfloat-helpers.h"
32
33
34
35static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
36
37const char * const riscv_int_regnames[] = {
38 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
39 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
40 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
41 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
42 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
43};
44
45const char * const riscv_fpr_regnames[] = {
46 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
47 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
48 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
49 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
50 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
51 "f30/ft10", "f31/ft11"
52};
53
54const char * const riscv_excp_names[] = {
55 "misaligned_fetch",
56 "fault_fetch",
57 "illegal_instruction",
58 "breakpoint",
59 "misaligned_load",
60 "fault_load",
61 "misaligned_store",
62 "fault_store",
63 "user_ecall",
64 "supervisor_ecall",
65 "hypervisor_ecall",
66 "machine_ecall",
67 "exec_page_fault",
68 "load_page_fault",
69 "reserved",
70 "store_page_fault",
71 "reserved",
72 "reserved",
73 "reserved",
74 "reserved",
75 "guest_exec_page_fault",
76 "guest_load_page_fault",
77 "reserved",
78 "guest_store_page_fault",
79};
80
81const char * const riscv_intr_names[] = {
82 "u_software",
83 "s_software",
84 "vs_software",
85 "m_software",
86 "u_timer",
87 "s_timer",
88 "vs_timer",
89 "m_timer",
90 "u_external",
91 "vs_external",
92 "h_external",
93 "m_external",
94 "reserved",
95 "reserved",
96 "reserved",
97 "reserved"
98};
99
100const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
101{
102 if (async) {
103 return (cause < ARRAY_SIZE(riscv_intr_names)) ?
104 riscv_intr_names[cause] : "(unknown)";
105 } else {
106 return (cause < ARRAY_SIZE(riscv_excp_names)) ?
107 riscv_excp_names[cause] : "(unknown)";
108 }
109}
110
111bool riscv_cpu_is_32bit(CPURISCVState *env)
112{
113 if (env->misa & RV64) {
114 return false;
115 }
116
117 return true;
118}
119
120static void set_misa(CPURISCVState *env, target_ulong misa)
121{
122 env->misa_mask = env->misa = misa;
123}
124
125static void set_priv_version(CPURISCVState *env, int priv_ver)
126{
127 env->priv_ver = priv_ver;
128}
129
130static void set_vext_version(CPURISCVState *env, int vext_ver)
131{
132 env->vext_ver = vext_ver;
133}
134
135static void set_feature(CPURISCVState *env, int feature)
136{
137 env->features |= (1ULL << feature);
138}
139
140static void set_resetvec(CPURISCVState *env, int resetvec)
141{
142#ifndef CONFIG_USER_ONLY
143 env->resetvec = resetvec;
144#endif
145}
146
147static void riscv_any_cpu_init(Object *obj)
148{
149 CPURISCVState *env = &RISCV_CPU(obj)->env;
150 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
151 set_priv_version(env, PRIV_VERSION_1_11_0);
152}
153
154#if defined(TARGET_RISCV64)
155static void rv64_base_cpu_init(Object *obj)
156{
157 CPURISCVState *env = &RISCV_CPU(obj)->env;
158
159 set_misa(env, RV64);
160}
161
162static void rv64_sifive_u_cpu_init(Object *obj)
163{
164 CPURISCVState *env = &RISCV_CPU(obj)->env;
165 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
166 set_priv_version(env, PRIV_VERSION_1_10_0);
167}
168
169static void rv64_sifive_e_cpu_init(Object *obj)
170{
171 CPURISCVState *env = &RISCV_CPU(obj)->env;
172 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
173 set_priv_version(env, PRIV_VERSION_1_10_0);
174 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
175}
176#else
177static void rv32_base_cpu_init(Object *obj)
178{
179 CPURISCVState *env = &RISCV_CPU(obj)->env;
180
181 set_misa(env, RV32);
182}
183
184static void rv32_sifive_u_cpu_init(Object *obj)
185{
186 CPURISCVState *env = &RISCV_CPU(obj)->env;
187 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
188 set_priv_version(env, PRIV_VERSION_1_10_0);
189}
190
191static void rv32_sifive_e_cpu_init(Object *obj)
192{
193 CPURISCVState *env = &RISCV_CPU(obj)->env;
194 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
195 set_priv_version(env, PRIV_VERSION_1_10_0);
196 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
197}
198
199static void rv32_ibex_cpu_init(Object *obj)
200{
201 CPURISCVState *env = &RISCV_CPU(obj)->env;
202 set_misa(env, RV32 | RVI | RVM | RVC | RVU);
203 set_priv_version(env, PRIV_VERSION_1_10_0);
204 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
205}
206
207static void rv32_imafcu_nommu_cpu_init(Object *obj)
208{
209 CPURISCVState *env = &RISCV_CPU(obj)->env;
210 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
211 set_priv_version(env, PRIV_VERSION_1_10_0);
212 set_resetvec(env, DEFAULT_RSTVEC);
213 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
214}
215#endif
216
217static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
218{
219 ObjectClass *oc;
220 char *typename;
221 char **cpuname;
222
223 cpuname = g_strsplit(cpu_model, ",", 1);
224 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
225 oc = object_class_by_name(typename);
226 g_strfreev(cpuname);
227 g_free(typename);
228 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
229 object_class_is_abstract(oc)) {
230 return NULL;
231 }
232 return oc;
233}
234
235static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
236{
237 RISCVCPU *cpu = RISCV_CPU(cs);
238 CPURISCVState *env = &cpu->env;
239 int i;
240
241#if !defined(CONFIG_USER_ONLY)
242 if (riscv_has_ext(env, RVH)) {
243 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
244 }
245#endif
246 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
247#ifndef CONFIG_USER_ONLY
248 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
249 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
250 if (riscv_cpu_is_32bit(env)) {
251 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
252 (target_ulong)(env->mstatus >> 32));
253 }
254 if (riscv_has_ext(env, RVH)) {
255 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
256 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
257 (target_ulong)env->vsstatus);
258 }
259 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
260 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
261 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
262 if (riscv_has_ext(env, RVH)) {
263 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
264 }
265 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
266 if (riscv_has_ext(env, RVH)) {
267 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
268 }
269 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
270 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
271 if (riscv_has_ext(env, RVH)) {
272 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec);
273 }
274 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
275 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc);
276 if (riscv_has_ext(env, RVH)) {
277 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc);
278 }
279 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
280 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause);
281 if (riscv_has_ext(env, RVH)) {
282 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
283 }
284 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
285 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
286 if (riscv_has_ext(env, RVH)) {
287 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
288 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
289 }
290#endif
291
292 for (i = 0; i < 32; i++) {
293 qemu_fprintf(f, " %s " TARGET_FMT_lx,
294 riscv_int_regnames[i], env->gpr[i]);
295 if ((i & 3) == 3) {
296 qemu_fprintf(f, "\n");
297 }
298 }
299 if (flags & CPU_DUMP_FPU) {
300 for (i = 0; i < 32; i++) {
301 qemu_fprintf(f, " %s %016" PRIx64,
302 riscv_fpr_regnames[i], env->fpr[i]);
303 if ((i & 3) == 3) {
304 qemu_fprintf(f, "\n");
305 }
306 }
307 }
308}
309
310static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
311{
312 RISCVCPU *cpu = RISCV_CPU(cs);
313 CPURISCVState *env = &cpu->env;
314 env->pc = value;
315}
316
317static void riscv_cpu_synchronize_from_tb(CPUState *cs,
318 const TranslationBlock *tb)
319{
320 RISCVCPU *cpu = RISCV_CPU(cs);
321 CPURISCVState *env = &cpu->env;
322 env->pc = tb->pc;
323}
324
325static bool riscv_cpu_has_work(CPUState *cs)
326{
327#ifndef CONFIG_USER_ONLY
328 RISCVCPU *cpu = RISCV_CPU(cs);
329 CPURISCVState *env = &cpu->env;
330
331
332
333
334 return (env->mip & env->mie) != 0;
335#else
336 return true;
337#endif
338}
339
340void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
341 target_ulong *data)
342{
343 env->pc = data[0];
344}
345
346static void riscv_cpu_reset(DeviceState *dev)
347{
348 CPUState *cs = CPU(dev);
349 RISCVCPU *cpu = RISCV_CPU(cs);
350 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
351 CPURISCVState *env = &cpu->env;
352
353 mcc->parent_reset(dev);
354#ifndef CONFIG_USER_ONLY
355 env->priv = PRV_M;
356 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
357 env->mcause = 0;
358 env->pc = env->resetvec;
359 env->two_stage_lookup = false;
360#endif
361 cs->exception_index = EXCP_NONE;
362 env->load_res = -1;
363 set_default_nan_mode(1, &env->fp_status);
364}
365
366static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
367{
368 RISCVCPU *cpu = RISCV_CPU(s);
369 if (riscv_cpu_is_32bit(&cpu->env)) {
370 info->print_insn = print_insn_riscv32;
371 } else {
372 info->print_insn = print_insn_riscv64;
373 }
374}
375
376static void riscv_cpu_realize(DeviceState *dev, Error **errp)
377{
378 CPUState *cs = CPU(dev);
379 RISCVCPU *cpu = RISCV_CPU(dev);
380 CPURISCVState *env = &cpu->env;
381 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
382 int priv_version = PRIV_VERSION_1_11_0;
383 int vext_version = VEXT_VERSION_0_07_1;
384 target_ulong target_misa = env->misa;
385 Error *local_err = NULL;
386
387 cpu_exec_realizefn(cs, &local_err);
388 if (local_err != NULL) {
389 error_propagate(errp, local_err);
390 return;
391 }
392
393 if (cpu->cfg.priv_spec) {
394 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
395 priv_version = PRIV_VERSION_1_11_0;
396 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
397 priv_version = PRIV_VERSION_1_10_0;
398 } else {
399 error_setg(errp,
400 "Unsupported privilege spec version '%s'",
401 cpu->cfg.priv_spec);
402 return;
403 }
404 }
405
406 set_priv_version(env, priv_version);
407 set_vext_version(env, vext_version);
408
409 if (cpu->cfg.mmu) {
410 set_feature(env, RISCV_FEATURE_MMU);
411 }
412
413 if (cpu->cfg.pmp) {
414 set_feature(env, RISCV_FEATURE_PMP);
415 }
416
417 set_resetvec(env, cpu->cfg.resetvec);
418
419
420 if (env->misa == RV32 || env->misa == RV64) {
421
422 if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
423 error_setg(errp,
424 "I and E extensions are incompatible");
425 return;
426 }
427
428 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
429 error_setg(errp,
430 "Either I or E extension must be set");
431 return;
432 }
433
434 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
435 cpu->cfg.ext_a & cpu->cfg.ext_f &
436 cpu->cfg.ext_d)) {
437 warn_report("Setting G will also set IMAFD");
438 cpu->cfg.ext_i = true;
439 cpu->cfg.ext_m = true;
440 cpu->cfg.ext_a = true;
441 cpu->cfg.ext_f = true;
442 cpu->cfg.ext_d = true;
443 }
444
445
446 if (cpu->cfg.ext_i) {
447 target_misa |= RVI;
448 }
449 if (cpu->cfg.ext_e) {
450 target_misa |= RVE;
451 }
452 if (cpu->cfg.ext_m) {
453 target_misa |= RVM;
454 }
455 if (cpu->cfg.ext_a) {
456 target_misa |= RVA;
457 }
458 if (cpu->cfg.ext_f) {
459 target_misa |= RVF;
460 }
461 if (cpu->cfg.ext_d) {
462 target_misa |= RVD;
463 }
464 if (cpu->cfg.ext_c) {
465 target_misa |= RVC;
466 }
467 if (cpu->cfg.ext_s) {
468 target_misa |= RVS;
469 }
470 if (cpu->cfg.ext_u) {
471 target_misa |= RVU;
472 }
473 if (cpu->cfg.ext_h) {
474 target_misa |= RVH;
475 }
476 if (cpu->cfg.ext_v) {
477 target_misa |= RVV;
478 if (!is_power_of_2(cpu->cfg.vlen)) {
479 error_setg(errp,
480 "Vector extension VLEN must be power of 2");
481 return;
482 }
483 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
484 error_setg(errp,
485 "Vector extension implementation only supports VLEN "
486 "in the range [128, %d]", RV_VLEN_MAX);
487 return;
488 }
489 if (!is_power_of_2(cpu->cfg.elen)) {
490 error_setg(errp,
491 "Vector extension ELEN must be power of 2");
492 return;
493 }
494 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
495 error_setg(errp,
496 "Vector extension implementation only supports ELEN "
497 "in the range [8, 64]");
498 return;
499 }
500 if (cpu->cfg.vext_spec) {
501 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
502 vext_version = VEXT_VERSION_0_07_1;
503 } else {
504 error_setg(errp,
505 "Unsupported vector spec version '%s'",
506 cpu->cfg.vext_spec);
507 return;
508 }
509 } else {
510 qemu_log("vector version is not specified, "
511 "use the default value v0.7.1\n");
512 }
513 set_vext_version(env, vext_version);
514 }
515
516 set_misa(env, target_misa);
517 }
518
519 riscv_cpu_register_gdb_regs_for_features(cs);
520
521 qemu_init_vcpu(cs);
522 cpu_reset(cs);
523
524 mcc->parent_realize(dev, errp);
525}
526
527static void riscv_cpu_init(Object *obj)
528{
529 RISCVCPU *cpu = RISCV_CPU(obj);
530
531 cpu_set_cpustate_pointers(cpu);
532}
533
534static Property riscv_cpu_properties[] = {
535 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
536 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
537 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
538 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
539 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
540 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
541 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
542 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
543 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
544 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
545
546 DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
547 DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
548 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
549 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
550 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
551 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
552 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
553 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
554 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
555 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
556 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
557 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
558 DEFINE_PROP_END_OF_LIST(),
559};
560
561static gchar *riscv_gdb_arch_name(CPUState *cs)
562{
563 RISCVCPU *cpu = RISCV_CPU(cs);
564 CPURISCVState *env = &cpu->env;
565
566 if (riscv_cpu_is_32bit(env)) {
567 return g_strdup("riscv:rv32");
568 } else {
569 return g_strdup("riscv:rv64");
570 }
571}
572
573static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
574{
575 RISCVCPU *cpu = RISCV_CPU(cs);
576
577 if (strcmp(xmlname, "riscv-csr.xml") == 0) {
578 return cpu->dyn_csr_xml;
579 }
580
581 return NULL;
582}
583
584#include "hw/core/tcg-cpu-ops.h"
585
586static struct TCGCPUOps riscv_tcg_ops = {
587 .initialize = riscv_translate_init,
588 .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
589 .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
590 .tlb_fill = riscv_cpu_tlb_fill,
591
592#ifndef CONFIG_USER_ONLY
593 .do_interrupt = riscv_cpu_do_interrupt,
594 .do_transaction_failed = riscv_cpu_do_transaction_failed,
595 .do_unaligned_access = riscv_cpu_do_unaligned_access,
596#endif
597};
598
599static void riscv_cpu_class_init(ObjectClass *c, void *data)
600{
601 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
602 CPUClass *cc = CPU_CLASS(c);
603 DeviceClass *dc = DEVICE_CLASS(c);
604
605 device_class_set_parent_realize(dc, riscv_cpu_realize,
606 &mcc->parent_realize);
607
608 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
609
610 cc->class_by_name = riscv_cpu_class_by_name;
611 cc->has_work = riscv_cpu_has_work;
612 cc->dump_state = riscv_cpu_dump_state;
613 cc->set_pc = riscv_cpu_set_pc;
614 cc->gdb_read_register = riscv_cpu_gdb_read_register;
615 cc->gdb_write_register = riscv_cpu_gdb_write_register;
616 cc->gdb_num_core_regs = 33;
617#if defined(TARGET_RISCV32)
618 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
619#elif defined(TARGET_RISCV64)
620 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
621#endif
622 cc->gdb_stop_before_watchpoint = true;
623 cc->disas_set_info = riscv_cpu_disas_set_info;
624#ifndef CONFIG_USER_ONLY
625 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
626
627 cc->vmsd = &vmstate_riscv_cpu;
628 cc->write_elf64_note = riscv_cpu_write_elf64_note;
629 cc->write_elf32_note = riscv_cpu_write_elf32_note;
630#endif
631 cc->gdb_arch_name = riscv_gdb_arch_name;
632 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
633 cc->tcg_ops = &riscv_tcg_ops;
634
635 device_class_set_props(dc, riscv_cpu_properties);
636}
637
638char *riscv_isa_string(RISCVCPU *cpu)
639{
640 int i;
641 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
642 char *isa_str = g_new(char, maxlen);
643 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
644 for (i = 0; i < sizeof(riscv_exts); i++) {
645 if (cpu->env.misa & RV(riscv_exts[i])) {
646 *p++ = qemu_tolower(riscv_exts[i]);
647 }
648 }
649 *p = '\0';
650 return isa_str;
651}
652
653static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
654{
655 ObjectClass *class_a = (ObjectClass *)a;
656 ObjectClass *class_b = (ObjectClass *)b;
657 const char *name_a, *name_b;
658
659 name_a = object_class_get_name(class_a);
660 name_b = object_class_get_name(class_b);
661 return strcmp(name_a, name_b);
662}
663
664static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
665{
666 const char *typename = object_class_get_name(OBJECT_CLASS(data));
667 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
668
669 qemu_printf("%.*s\n", len, typename);
670}
671
672void riscv_cpu_list(void)
673{
674 GSList *list;
675
676 list = object_class_get_list(TYPE_RISCV_CPU, false);
677 list = g_slist_sort(list, riscv_cpu_list_compare);
678 g_slist_foreach(list, riscv_cpu_list_entry, NULL);
679 g_slist_free(list);
680}
681
682#define DEFINE_CPU(type_name, initfn) \
683 { \
684 .name = type_name, \
685 .parent = TYPE_RISCV_CPU, \
686 .instance_init = initfn \
687 }
688
689static const TypeInfo riscv_cpu_type_infos[] = {
690 {
691 .name = TYPE_RISCV_CPU,
692 .parent = TYPE_CPU,
693 .instance_size = sizeof(RISCVCPU),
694 .instance_align = __alignof__(RISCVCPU),
695 .instance_init = riscv_cpu_init,
696 .abstract = true,
697 .class_size = sizeof(RISCVCPUClass),
698 .class_init = riscv_cpu_class_init,
699 },
700 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
701#if defined(TARGET_RISCV32)
702 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
703 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
704 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
705 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
706 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
707#elif defined(TARGET_RISCV64)
708 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
709 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
710 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
711#endif
712};
713
714DEFINE_TYPES(riscv_cpu_type_infos)
715
