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10#ifndef S390X_INTERNAL_H
11#define S390X_INTERNAL_H
12
13#include "cpu.h"
14
15#ifndef CONFIG_USER_ONLY
16typedef struct LowCore {
17
18 uint32_t ccw1[2];
19 uint32_t ccw2[4];
20 uint8_t pad1[0x80 - 0x18];
21 uint32_t ext_params;
22 uint16_t cpu_addr;
23 uint16_t ext_int_code;
24 uint16_t svc_ilen;
25 uint16_t svc_code;
26 uint16_t pgm_ilen;
27 uint16_t pgm_code;
28 uint32_t data_exc_code;
29 uint16_t mon_class_num;
30 uint16_t per_perc_atmid;
31 uint64_t per_address;
32 uint8_t exc_access_id;
33 uint8_t per_access_id;
34 uint8_t op_access_id;
35 uint8_t ar_access_id;
36 uint8_t pad2[0xA8 - 0xA4];
37 uint64_t trans_exc_code;
38 uint64_t monitor_code;
39 uint16_t subchannel_id;
40 uint16_t subchannel_nr;
41 uint32_t io_int_parm;
42 uint32_t io_int_word;
43 uint8_t pad3[0xc8 - 0xc4];
44 uint32_t stfl_fac_list;
45 uint8_t pad4[0xe8 - 0xcc];
46 uint64_t mcic;
47 uint8_t pad5[0xf4 - 0xf0];
48 uint32_t external_damage_code;
49 uint64_t failing_storage_address;
50 uint8_t pad6[0x110 - 0x100];
51 uint64_t per_breaking_event_addr;
52 uint8_t pad7[0x120 - 0x118];
53 PSW restart_old_psw;
54 PSW external_old_psw;
55 PSW svc_old_psw;
56 PSW program_old_psw;
57 PSW mcck_old_psw;
58 PSW io_old_psw;
59 uint8_t pad8[0x1a0 - 0x180];
60 PSW restart_new_psw;
61 PSW external_new_psw;
62 PSW svc_new_psw;
63 PSW program_new_psw;
64 PSW mcck_new_psw;
65 PSW io_new_psw;
66 uint8_t pad13[0x11b0 - 0x200];
67
68 uint64_t mcesad;
69
70
71 uint64_t ext_params2;
72
73 uint8_t pad14[0x1200 - 0x11C0];
74
75
76
77 uint64_t floating_pt_save_area[16];
78 uint64_t gpregs_save_area[16];
79 uint32_t st_status_fixed_logout[4];
80 uint8_t pad15[0x1318 - 0x1310];
81 uint32_t prefixreg_save_area;
82 uint32_t fpt_creg_save_area;
83 uint8_t pad16[0x1324 - 0x1320];
84 uint32_t tod_progreg_save_area;
85 uint64_t cpu_timer_save_area;
86 uint64_t clock_comp_save_area;
87 uint8_t pad17[0x1340 - 0x1338];
88 uint32_t access_regs_save_area[16];
89 uint64_t cregs_save_area[16];
90
91
92
93 uint8_t pad18[0x2000 - 0x1400];
94} QEMU_PACKED LowCore;
95QEMU_BUILD_BUG_ON(sizeof(LowCore) != 8192);
96#endif
97
98#define MAX_ILEN 6
99
100
101
102
103
104
105static inline int get_ilen(uint8_t opc)
106{
107 switch (opc >> 6) {
108 case 0:
109 return 2;
110 case 1:
111 case 2:
112 return 4;
113 default:
114 return 6;
115 }
116}
117
118
119
120static inline uint8_t get_per_atmid(CPUS390XState *env)
121{
122 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
123 (1 << 6) |
124 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
125 ((env->psw.mask & PSW_MASK_DAT) ? (1 << 4) : 0) |
126 ((env->psw.mask & PSW_ASC_SECONDARY) ? (1 << 3) : 0) |
127 ((env->psw.mask & PSW_ASC_ACCREG) ? (1 << 2) : 0);
128}
129
130static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
131{
132 if (!(env->psw.mask & PSW_MASK_64)) {
133 if (!(env->psw.mask & PSW_MASK_32)) {
134
135 a &= 0x00ffffff;
136 } else {
137
138 a &= 0x7fffffff;
139 }
140 }
141 return a;
142}
143
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151
152
153enum cc_op {
154 CC_OP_CONST0 = 0,
155 CC_OP_CONST1,
156 CC_OP_CONST2,
157 CC_OP_CONST3,
158
159 CC_OP_DYNAMIC,
160 CC_OP_STATIC,
161
162 CC_OP_NZ,
163 CC_OP_ADDU,
164 CC_OP_SUBU,
165
166 CC_OP_LTGT_32,
167 CC_OP_LTGT_64,
168 CC_OP_LTUGTU_32,
169 CC_OP_LTUGTU_64,
170 CC_OP_LTGT0_32,
171 CC_OP_LTGT0_64,
172
173 CC_OP_ADD_64,
174 CC_OP_SUB_64,
175 CC_OP_ABS_64,
176 CC_OP_NABS_64,
177 CC_OP_MULS_64,
178
179 CC_OP_ADD_32,
180 CC_OP_SUB_32,
181 CC_OP_ABS_32,
182 CC_OP_NABS_32,
183 CC_OP_MULS_32,
184
185 CC_OP_COMP_32,
186 CC_OP_COMP_64,
187
188 CC_OP_TM_32,
189 CC_OP_TM_64,
190
191 CC_OP_NZ_F32,
192 CC_OP_NZ_F64,
193 CC_OP_NZ_F128,
194
195 CC_OP_ICM,
196 CC_OP_SLA_32,
197 CC_OP_SLA_64,
198 CC_OP_FLOGR,
199 CC_OP_LCBB,
200 CC_OP_VC,
201 CC_OP_MAX
202};
203
204#ifndef CONFIG_USER_ONLY
205
206static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
207 uint8_t *ar)
208{
209 hwaddr addr = 0;
210 uint8_t reg;
211
212 reg = ipb >> 28;
213 if (reg > 0) {
214 addr = env->regs[reg];
215 }
216 addr += (ipb >> 16) & 0xfff;
217 if (ar) {
218 *ar = reg;
219 }
220
221 return addr;
222}
223
224
225#define decode_basedisp_rs decode_basedisp_s
226
227#endif
228
229
230int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
231 int cpuid, void *opaque);
232
233
234
235const char *cc_name(enum cc_op cc_op);
236uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
237 uint64_t vr);
238#ifndef CONFIG_USER_ONLY
239void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
240#endif
241
242
243
244#ifndef CONFIG_USER_ONLY
245unsigned int s390_cpu_halt(S390CPU *cpu);
246void s390_cpu_unhalt(S390CPU *cpu);
247#else
248static inline unsigned int s390_cpu_halt(S390CPU *cpu)
249{
250 return 0;
251}
252
253static inline void s390_cpu_unhalt(S390CPU *cpu)
254{
255}
256#endif
257
258
259
260void s390_cpu_model_class_register_props(ObjectClass *oc);
261void s390_realize_cpu_model(CPUState *cs, Error **errp);
262ObjectClass *s390_cpu_class_by_name(const char *name);
263
264
265
266void s390x_cpu_debug_excp_handler(CPUState *cs);
267void s390_cpu_do_interrupt(CPUState *cpu);
268bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
269bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
270 MMUAccessType access_type, int mmu_idx,
271 bool probe, uintptr_t retaddr);
272void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
273 MMUAccessType access_type,
274 int mmu_idx, uintptr_t retaddr);
275
276
277
278uint32_t set_cc_nz_f32(float32 v);
279uint32_t set_cc_nz_f64(float64 v);
280uint32_t set_cc_nz_f128(float128 v);
281#define S390_IEEE_MASK_INVALID 0x80
282#define S390_IEEE_MASK_DIVBYZERO 0x40
283#define S390_IEEE_MASK_OVERFLOW 0x20
284#define S390_IEEE_MASK_UNDERFLOW 0x10
285#define S390_IEEE_MASK_INEXACT 0x08
286#define S390_IEEE_MASK_QUANTUM 0x04
287uint8_t s390_softfloat_exc_to_ieee(unsigned int exc);
288int s390_swap_bfp_rounding_mode(CPUS390XState *env, int m3);
289void s390_restore_bfp_rounding_mode(CPUS390XState *env, int old_mode);
290int float_comp_to_cc(CPUS390XState *env, int float_compare);
291uint16_t float32_dcmask(CPUS390XState *env, float32 f1);
292uint16_t float64_dcmask(CPUS390XState *env, float64 f1);
293uint16_t float128_dcmask(CPUS390XState *env, float128 f1);
294
295
296
297int s390_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
298int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
299void s390_cpu_gdb_init(CPUState *cs);
300
301
302
303void s390_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
304void do_restart_interrupt(CPUS390XState *env);
305#ifndef CONFIG_USER_ONLY
306uint64_t get_psw_mask(CPUS390XState *env);
307void s390_cpu_recompute_watchpoints(CPUState *cs);
308void s390x_tod_timer(void *opaque);
309void s390x_cpu_timer(void *opaque);
310void s390_handle_wait(S390CPU *cpu);
311hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
312hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
313#define S390_STORE_STATUS_DEF_ADDR offsetof(LowCore, floating_pt_save_area)
314int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch);
315int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len);
316LowCore *cpu_map_lowcore(CPUS390XState *env);
317void cpu_unmap_lowcore(LowCore *lowcore);
318#endif
319
320
321
322void trigger_pgm_exception(CPUS390XState *env, uint32_t code);
323void cpu_inject_clock_comparator(S390CPU *cpu);
324void cpu_inject_cpu_timer(S390CPU *cpu);
325void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr);
326int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr);
327bool s390_cpu_has_io_int(S390CPU *cpu);
328bool s390_cpu_has_ext_int(S390CPU *cpu);
329bool s390_cpu_has_mcck_int(S390CPU *cpu);
330bool s390_cpu_has_int(S390CPU *cpu);
331bool s390_cpu_has_restart_int(S390CPU *cpu);
332bool s390_cpu_has_stop_int(S390CPU *cpu);
333void cpu_inject_restart(S390CPU *cpu);
334void cpu_inject_stop(S390CPU *cpu);
335
336
337
338void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
339void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
340void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
341void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
342 uintptr_t ra);
343void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
344 uintptr_t ra);
345void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb, uintptr_t ra);
346void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
347 uintptr_t ra);
348int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb, uintptr_t ra);
349void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb, uintptr_t ra);
350void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
351 uint32_t ipb, uintptr_t ra);
352void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
353void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
354void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
355
356
357
358target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr);
359void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
360 uintptr_t ra);
361
362
363
364int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
365 target_ulong *raddr, int *flags, uint64_t *tec);
366int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
367 target_ulong *addr, int *flags, uint64_t *tec);
368
369
370
371int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
372void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3,
373 uintptr_t ra);
374
375
376
377void s390x_translate_init(void);
378
379
380
381int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3);
382void do_stop_interrupt(CPUS390XState *env);
383
384#endif
385