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20#include "qemu/osdep.h"
21
22#include "cpu.h"
23#include "exec/exec-all.h"
24#include "exec/log.h"
25
26#if !defined(CONFIG_USER_ONLY)
27#include "hw/sh4/sh_intc.h"
28#include "sysemu/runstate.h"
29#endif
30
31#define MMU_OK 0
32#define MMU_ITLB_MISS (-1)
33#define MMU_ITLB_MULTIPLE (-2)
34#define MMU_ITLB_VIOLATION (-3)
35#define MMU_DTLB_MISS_READ (-4)
36#define MMU_DTLB_MISS_WRITE (-5)
37#define MMU_DTLB_INITIAL_WRITE (-6)
38#define MMU_DTLB_VIOLATION_READ (-7)
39#define MMU_DTLB_VIOLATION_WRITE (-8)
40#define MMU_DTLB_MULTIPLE (-9)
41#define MMU_DTLB_MISS (-10)
42#define MMU_IADDR_ERROR (-11)
43#define MMU_DADDR_ERROR_READ (-12)
44#define MMU_DADDR_ERROR_WRITE (-13)
45
46#if defined(CONFIG_USER_ONLY)
47
48void superh_cpu_do_interrupt(CPUState *cs)
49{
50 cs->exception_index = -1;
51}
52
53int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
54{
55
56 return !(addr & 0x80000000);
57}
58
59#else
60
61void superh_cpu_do_interrupt(CPUState *cs)
62{
63 SuperHCPU *cpu = SUPERH_CPU(cs);
64 CPUSH4State *env = &cpu->env;
65 int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
66 int do_exp, irq_vector = cs->exception_index;
67
68
69
70 do_exp = cs->exception_index != -1;
71 do_irq = do_irq && (cs->exception_index == -1);
72
73 if (env->sr & (1u << SR_BL)) {
74 if (do_exp && cs->exception_index != 0x1e0) {
75
76
77
78
79
80
81 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
82 return;
83 }
84 if (do_irq && !env->in_sleep) {
85 return;
86 }
87 }
88 env->in_sleep = 0;
89
90 if (do_irq) {
91 irq_vector = sh_intc_get_pending_vector(env->intc_handle,
92 (env->sr >> 4) & 0xf);
93 if (irq_vector == -1) {
94 return;
95 }
96 }
97
98 if (qemu_loglevel_mask(CPU_LOG_INT)) {
99 const char *expname;
100 switch (cs->exception_index) {
101 case 0x0e0:
102 expname = "addr_error";
103 break;
104 case 0x040:
105 expname = "tlb_miss";
106 break;
107 case 0x0a0:
108 expname = "tlb_violation";
109 break;
110 case 0x180:
111 expname = "illegal_instruction";
112 break;
113 case 0x1a0:
114 expname = "slot_illegal_instruction";
115 break;
116 case 0x800:
117 expname = "fpu_disable";
118 break;
119 case 0x820:
120 expname = "slot_fpu";
121 break;
122 case 0x100:
123 expname = "data_write";
124 break;
125 case 0x060:
126 expname = "dtlb_miss_write";
127 break;
128 case 0x0c0:
129 expname = "dtlb_violation_write";
130 break;
131 case 0x120:
132 expname = "fpu_exception";
133 break;
134 case 0x080:
135 expname = "initial_page_write";
136 break;
137 case 0x160:
138 expname = "trapa";
139 break;
140 default:
141 expname = do_irq ? "interrupt" : "???";
142 break;
143 }
144 qemu_log("exception 0x%03x [%s] raised\n",
145 irq_vector, expname);
146 log_cpu_state(cs, 0);
147 }
148
149 env->ssr = cpu_read_sr(env);
150 env->spc = env->pc;
151 env->sgr = env->gregs[15];
152 env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
153 env->lock_addr = -1;
154
155 if (env->flags & DELAY_SLOT_MASK) {
156
157 env->spc -= 2;
158
159 env->flags &= ~DELAY_SLOT_MASK;
160 }
161
162 if (do_exp) {
163 env->expevt = cs->exception_index;
164 switch (cs->exception_index) {
165 case 0x000:
166 case 0x020:
167 case 0x140:
168 env->sr &= ~(1u << SR_FD);
169 env->sr |= 0xf << 4;
170 env->pc = 0xa0000000;
171 break;
172 case 0x040:
173 case 0x060:
174 env->pc = env->vbr + 0x400;
175 break;
176 case 0x160:
177 env->spc += 2;
178
179 default:
180 env->pc = env->vbr + 0x100;
181 break;
182 }
183 return;
184 }
185
186 if (do_irq) {
187 env->intevt = irq_vector;
188 env->pc = env->vbr + 0x600;
189 return;
190 }
191}
192
193static void update_itlb_use(CPUSH4State * env, int itlbnb)
194{
195 uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
196
197 switch (itlbnb) {
198 case 0:
199 and_mask = 0x1f;
200 break;
201 case 1:
202 and_mask = 0xe7;
203 or_mask = 0x80;
204 break;
205 case 2:
206 and_mask = 0xfb;
207 or_mask = 0x50;
208 break;
209 case 3:
210 or_mask = 0x2c;
211 break;
212 }
213
214 env->mmucr &= (and_mask << 24) | 0x00ffffff;
215 env->mmucr |= (or_mask << 24);
216}
217
218static int itlb_replacement(CPUSH4State * env)
219{
220 if ((env->mmucr & 0xe0000000) == 0xe0000000) {
221 return 0;
222 }
223 if ((env->mmucr & 0x98000000) == 0x18000000) {
224 return 1;
225 }
226 if ((env->mmucr & 0x54000000) == 0x04000000) {
227 return 2;
228 }
229 if ((env->mmucr & 0x2c000000) == 0x00000000) {
230 return 3;
231 }
232 cpu_abort(env_cpu(env), "Unhandled itlb_replacement");
233}
234
235
236
237
238static int find_tlb_entry(CPUSH4State * env, target_ulong address,
239 tlb_t * entries, uint8_t nbtlb, int use_asid)
240{
241 int match = MMU_DTLB_MISS;
242 uint32_t start, end;
243 uint8_t asid;
244 int i;
245
246 asid = env->pteh & 0xff;
247
248 for (i = 0; i < nbtlb; i++) {
249 if (!entries[i].v)
250 continue;
251 if (!entries[i].sh && use_asid && entries[i].asid != asid)
252 continue;
253 start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
254 end = start + entries[i].size - 1;
255 if (address >= start && address <= end) {
256 if (match != MMU_DTLB_MISS)
257 return MMU_DTLB_MULTIPLE;
258 match = i;
259 }
260 }
261 return match;
262}
263
264static void increment_urc(CPUSH4State * env)
265{
266 uint8_t urb, urc;
267
268
269 urb = ((env->mmucr) >> 18) & 0x3f;
270 urc = ((env->mmucr) >> 10) & 0x3f;
271 urc++;
272 if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
273 urc = 0;
274 env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
275}
276
277
278
279
280static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
281{
282 int itlb;
283
284 tlb_t * ientry;
285 itlb = itlb_replacement(env);
286 ientry = &env->itlb[itlb];
287 if (ientry->v) {
288 tlb_flush_page(env_cpu(env), ientry->vpn << 10);
289 }
290 *ientry = env->utlb[utlb];
291 update_itlb_use(env, itlb);
292 return itlb;
293}
294
295
296
297
298static int find_itlb_entry(CPUSH4State * env, target_ulong address,
299 int use_asid)
300{
301 int e;
302
303 e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
304 if (e == MMU_DTLB_MULTIPLE) {
305 e = MMU_ITLB_MULTIPLE;
306 } else if (e == MMU_DTLB_MISS) {
307 e = MMU_ITLB_MISS;
308 } else if (e >= 0) {
309 update_itlb_use(env, e);
310 }
311 return e;
312}
313
314
315
316static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
317{
318
319 increment_urc(env);
320
321
322 return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
323}
324
325
326
327
328
329
330
331
332static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
333 int *prot, target_ulong address,
334 MMUAccessType access_type)
335{
336 int use_asid, n;
337 tlb_t *matching = NULL;
338
339 use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
340
341 if (access_type == MMU_INST_FETCH) {
342 n = find_itlb_entry(env, address, use_asid);
343 if (n >= 0) {
344 matching = &env->itlb[n];
345 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
346 n = MMU_ITLB_VIOLATION;
347 } else {
348 *prot = PAGE_EXEC;
349 }
350 } else {
351 n = find_utlb_entry(env, address, use_asid);
352 if (n >= 0) {
353 n = copy_utlb_entry_itlb(env, n);
354 matching = &env->itlb[n];
355 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
356 n = MMU_ITLB_VIOLATION;
357 } else {
358 *prot = PAGE_READ | PAGE_EXEC;
359 if ((matching->pr & 1) && matching->d) {
360 *prot |= PAGE_WRITE;
361 }
362 }
363 } else if (n == MMU_DTLB_MULTIPLE) {
364 n = MMU_ITLB_MULTIPLE;
365 } else if (n == MMU_DTLB_MISS) {
366 n = MMU_ITLB_MISS;
367 }
368 }
369 } else {
370 n = find_utlb_entry(env, address, use_asid);
371 if (n >= 0) {
372 matching = &env->utlb[n];
373 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
374 n = (access_type == MMU_DATA_STORE)
375 ? MMU_DTLB_VIOLATION_WRITE : MMU_DTLB_VIOLATION_READ;
376 } else if ((access_type == MMU_DATA_STORE) && !(matching->pr & 1)) {
377 n = MMU_DTLB_VIOLATION_WRITE;
378 } else if ((access_type == MMU_DATA_STORE) && !matching->d) {
379 n = MMU_DTLB_INITIAL_WRITE;
380 } else {
381 *prot = PAGE_READ;
382 if ((matching->pr & 1) && matching->d) {
383 *prot |= PAGE_WRITE;
384 }
385 }
386 } else if (n == MMU_DTLB_MISS) {
387 n = (access_type == MMU_DATA_STORE)
388 ? MMU_DTLB_MISS_WRITE : MMU_DTLB_MISS_READ;
389 }
390 }
391 if (n >= 0) {
392 n = MMU_OK;
393 *physical = ((matching->ppn << 10) & ~(matching->size - 1))
394 | (address & (matching->size - 1));
395 }
396 return n;
397}
398
399static int get_physical_address(CPUSH4State * env, target_ulong * physical,
400 int *prot, target_ulong address,
401 MMUAccessType access_type)
402{
403
404 if ((address >= 0x80000000 && address < 0xc0000000) || address >= 0xe0000000) {
405 if (!(env->sr & (1u << SR_MD))
406 && (address < 0xe0000000 || address >= 0xe4000000)) {
407
408 qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
409 if (access_type == MMU_DATA_LOAD) {
410 return MMU_DADDR_ERROR_READ;
411 } else if (access_type == MMU_DATA_STORE) {
412 return MMU_DADDR_ERROR_WRITE;
413 } else {
414 return MMU_IADDR_ERROR;
415 }
416 }
417 if (address >= 0x80000000 && address < 0xc0000000) {
418
419 *physical = address & 0x1fffffff;
420 } else {
421 *physical = address;
422 }
423 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
424 return MMU_OK;
425 }
426
427
428 if (!(env->mmucr & MMUCR_AT)) {
429 *physical = address & 0x1FFFFFFF;
430 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
431 return MMU_OK;
432 }
433
434
435 return get_mmu_address(env, physical, prot, address, access_type);
436}
437
438hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
439{
440 SuperHCPU *cpu = SUPERH_CPU(cs);
441 target_ulong physical;
442 int prot;
443
444 get_physical_address(&cpu->env, &physical, &prot, addr, MMU_DATA_LOAD);
445
446 return physical;
447}
448
449void cpu_load_tlb(CPUSH4State * env)
450{
451 CPUState *cs = env_cpu(env);
452 int n = cpu_mmucr_urc(env->mmucr);
453 tlb_t * entry = &env->utlb[n];
454
455 if (entry->v) {
456
457 target_ulong address = entry->vpn << 10;
458 tlb_flush_page(cs, address);
459 }
460
461
462 entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
463 entry->vpn = cpu_pteh_vpn(env->pteh);
464 entry->v = (uint8_t)cpu_ptel_v(env->ptel);
465 entry->ppn = cpu_ptel_ppn(env->ptel);
466 entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
467 switch (entry->sz) {
468 case 0:
469 entry->size = 1024;
470 break;
471 case 1:
472 entry->size = 1024 * 4;
473 break;
474 case 2:
475 entry->size = 1024 * 64;
476 break;
477 case 3:
478 entry->size = 1024 * 1024;
479 break;
480 default:
481 cpu_abort(cs, "Unhandled load_tlb");
482 break;
483 }
484 entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
485 entry->c = (uint8_t)cpu_ptel_c(env->ptel);
486 entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
487 entry->d = (uint8_t)cpu_ptel_d(env->ptel);
488 entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
489 entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
490 entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
491}
492
493 void cpu_sh4_invalidate_tlb(CPUSH4State *s)
494{
495 int i;
496
497
498 for (i = 0; i < UTLB_SIZE; i++) {
499 tlb_t * entry = &s->utlb[i];
500 entry->v = 0;
501 }
502
503 for (i = 0; i < ITLB_SIZE; i++) {
504 tlb_t * entry = &s->itlb[i];
505 entry->v = 0;
506 }
507
508 tlb_flush(env_cpu(s));
509}
510
511uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
512 hwaddr addr)
513{
514 int index = (addr & 0x00000300) >> 8;
515 tlb_t * entry = &s->itlb[index];
516
517 return (entry->vpn << 10) |
518 (entry->v << 8) |
519 (entry->asid);
520}
521
522void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
523 uint32_t mem_value)
524{
525 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
526 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
527 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
528
529 int index = (addr & 0x00000300) >> 8;
530 tlb_t * entry = &s->itlb[index];
531 if (entry->v) {
532
533 target_ulong address = entry->vpn << 10;
534 tlb_flush_page(env_cpu(s), address);
535 }
536 entry->asid = asid;
537 entry->vpn = vpn;
538 entry->v = v;
539}
540
541uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
542 hwaddr addr)
543{
544 int array = (addr & 0x00800000) >> 23;
545 int index = (addr & 0x00000300) >> 8;
546 tlb_t * entry = &s->itlb[index];
547
548 if (array == 0) {
549
550 return (entry->ppn << 10) |
551 (entry->v << 8) |
552 (entry->pr << 5) |
553 ((entry->sz & 1) << 6) |
554 ((entry->sz & 2) << 4) |
555 (entry->c << 3) |
556 (entry->sh << 1);
557 } else {
558
559 return (entry->tc << 1) |
560 (entry->sa);
561 }
562}
563
564void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
565 uint32_t mem_value)
566{
567 int array = (addr & 0x00800000) >> 23;
568 int index = (addr & 0x00000300) >> 8;
569 tlb_t * entry = &s->itlb[index];
570
571 if (array == 0) {
572
573 if (entry->v) {
574
575 target_ulong address = entry->vpn << 10;
576 tlb_flush_page(env_cpu(s), address);
577 }
578 entry->ppn = (mem_value & 0x1ffffc00) >> 10;
579 entry->v = (mem_value & 0x00000100) >> 8;
580 entry->sz = (mem_value & 0x00000080) >> 6 |
581 (mem_value & 0x00000010) >> 4;
582 entry->pr = (mem_value & 0x00000040) >> 5;
583 entry->c = (mem_value & 0x00000008) >> 3;
584 entry->sh = (mem_value & 0x00000002) >> 1;
585 } else {
586
587 entry->tc = (mem_value & 0x00000008) >> 3;
588 entry->sa = (mem_value & 0x00000007);
589 }
590}
591
592uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
593 hwaddr addr)
594{
595 int index = (addr & 0x00003f00) >> 8;
596 tlb_t * entry = &s->utlb[index];
597
598 increment_urc(s);
599
600 return (entry->vpn << 10) |
601 (entry->v << 8) |
602 (entry->asid);
603}
604
605void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
606 uint32_t mem_value)
607{
608 int associate = addr & 0x0000080;
609 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
610 uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
611 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
612 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
613 int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
614
615 if (associate) {
616 int i;
617 tlb_t * utlb_match_entry = NULL;
618 int needs_tlb_flush = 0;
619
620
621 for (i = 0; i < UTLB_SIZE; i++) {
622 tlb_t * entry = &s->utlb[i];
623 if (!entry->v)
624 continue;
625
626 if (entry->vpn == vpn
627 && (!use_asid || entry->asid == asid || entry->sh)) {
628 if (utlb_match_entry) {
629 CPUState *cs = env_cpu(s);
630
631
632 cs->exception_index = 0x140;
633 s->tea = addr;
634 break;
635 }
636 if (entry->v && !v)
637 needs_tlb_flush = 1;
638 entry->v = v;
639 entry->d = d;
640 utlb_match_entry = entry;
641 }
642 increment_urc(s);
643 }
644
645
646 for (i = 0; i < ITLB_SIZE; i++) {
647 tlb_t * entry = &s->itlb[i];
648 if (entry->vpn == vpn
649 && (!use_asid || entry->asid == asid || entry->sh)) {
650 if (entry->v && !v)
651 needs_tlb_flush = 1;
652 if (utlb_match_entry)
653 *entry = *utlb_match_entry;
654 else
655 entry->v = v;
656 break;
657 }
658 }
659
660 if (needs_tlb_flush) {
661 tlb_flush_page(env_cpu(s), vpn << 10);
662 }
663 } else {
664 int index = (addr & 0x00003f00) >> 8;
665 tlb_t * entry = &s->utlb[index];
666 if (entry->v) {
667 CPUState *cs = env_cpu(s);
668
669
670 target_ulong address = entry->vpn << 10;
671 tlb_flush_page(cs, address);
672 }
673 entry->asid = asid;
674 entry->vpn = vpn;
675 entry->d = d;
676 entry->v = v;
677 increment_urc(s);
678 }
679}
680
681uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
682 hwaddr addr)
683{
684 int array = (addr & 0x00800000) >> 23;
685 int index = (addr & 0x00003f00) >> 8;
686 tlb_t * entry = &s->utlb[index];
687
688 increment_urc(s);
689
690 if (array == 0) {
691
692 return (entry->ppn << 10) |
693 (entry->v << 8) |
694 (entry->pr << 5) |
695 ((entry->sz & 1) << 6) |
696 ((entry->sz & 2) << 4) |
697 (entry->c << 3) |
698 (entry->d << 2) |
699 (entry->sh << 1) |
700 (entry->wt);
701 } else {
702
703 return (entry->tc << 1) |
704 (entry->sa);
705 }
706}
707
708void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
709 uint32_t mem_value)
710{
711 int array = (addr & 0x00800000) >> 23;
712 int index = (addr & 0x00003f00) >> 8;
713 tlb_t * entry = &s->utlb[index];
714
715 increment_urc(s);
716
717 if (array == 0) {
718
719 if (entry->v) {
720
721 target_ulong address = entry->vpn << 10;
722 tlb_flush_page(env_cpu(s), address);
723 }
724 entry->ppn = (mem_value & 0x1ffffc00) >> 10;
725 entry->v = (mem_value & 0x00000100) >> 8;
726 entry->sz = (mem_value & 0x00000080) >> 6 |
727 (mem_value & 0x00000010) >> 4;
728 entry->pr = (mem_value & 0x00000060) >> 5;
729 entry->c = (mem_value & 0x00000008) >> 3;
730 entry->d = (mem_value & 0x00000004) >> 2;
731 entry->sh = (mem_value & 0x00000002) >> 1;
732 entry->wt = (mem_value & 0x00000001);
733 } else {
734
735 entry->tc = (mem_value & 0x00000008) >> 3;
736 entry->sa = (mem_value & 0x00000007);
737 }
738}
739
740int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
741{
742 int n;
743 int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
744
745
746 if (env->sr & (1u << SR_MD)) {
747
748 if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
749 return 0;
750 } else {
751
752 if (0x80000000 <= addr)
753 return 0;
754 }
755
756
757
758
759
760
761
762#if 0
763
764 if (!(env->ccr & 1))
765 return 0;
766#endif
767
768
769 if (env->mmucr & MMUCR_AT)
770 return 1;
771
772
773 n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
774 if (n >= 0)
775 return env->itlb[n].c;
776
777 n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
778 if (n >= 0)
779 return env->utlb[n].c;
780
781 return 0;
782}
783
784#endif
785
786bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
787{
788 if (interrupt_request & CPU_INTERRUPT_HARD) {
789 SuperHCPU *cpu = SUPERH_CPU(cs);
790 CPUSH4State *env = &cpu->env;
791
792
793 if (env->flags & DELAY_SLOT_MASK) {
794 return false;
795 } else {
796 superh_cpu_do_interrupt(cs);
797 return true;
798 }
799 }
800 return false;
801}
802
803bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
804 MMUAccessType access_type, int mmu_idx,
805 bool probe, uintptr_t retaddr)
806{
807 SuperHCPU *cpu = SUPERH_CPU(cs);
808 CPUSH4State *env = &cpu->env;
809 int ret;
810
811#ifdef CONFIG_USER_ONLY
812 ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE :
813 access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION :
814 MMU_DTLB_VIOLATION_READ);
815#else
816 target_ulong physical;
817 int prot;
818
819 ret = get_physical_address(env, &physical, &prot, address, access_type);
820
821 if (ret == MMU_OK) {
822 address &= TARGET_PAGE_MASK;
823 physical &= TARGET_PAGE_MASK;
824 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
825 return true;
826 }
827 if (probe) {
828 return false;
829 }
830
831 if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
832 env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK);
833 }
834#endif
835
836 env->tea = address;
837 switch (ret) {
838 case MMU_ITLB_MISS:
839 case MMU_DTLB_MISS_READ:
840 cs->exception_index = 0x040;
841 break;
842 case MMU_DTLB_MULTIPLE:
843 case MMU_ITLB_MULTIPLE:
844 cs->exception_index = 0x140;
845 break;
846 case MMU_ITLB_VIOLATION:
847 cs->exception_index = 0x0a0;
848 break;
849 case MMU_DTLB_MISS_WRITE:
850 cs->exception_index = 0x060;
851 break;
852 case MMU_DTLB_INITIAL_WRITE:
853 cs->exception_index = 0x080;
854 break;
855 case MMU_DTLB_VIOLATION_READ:
856 cs->exception_index = 0x0a0;
857 break;
858 case MMU_DTLB_VIOLATION_WRITE:
859 cs->exception_index = 0x0c0;
860 break;
861 case MMU_IADDR_ERROR:
862 case MMU_DADDR_ERROR_READ:
863 cs->exception_index = 0x0e0;
864 break;
865 case MMU_DADDR_ERROR_WRITE:
866 cs->exception_index = 0x100;
867 break;
868 default:
869 cpu_abort(cs, "Unhandled MMU fault");
870 }
871 cpu_loop_exit_restore(cs, retaddr);
872}
873