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31#include "qemu/osdep.h"
32#include "qapi/error.h"
33#include "cpu.h"
34#include "fpu/softfloat.h"
35#include "qemu/module.h"
36#include "migration/vmstate.h"
37
38
39static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
40{
41 XtensaCPU *cpu = XTENSA_CPU(cs);
42
43 cpu->env.pc = value;
44}
45
46static bool xtensa_cpu_has_work(CPUState *cs)
47{
48#ifndef CONFIG_USER_ONLY
49 XtensaCPU *cpu = XTENSA_CPU(cs);
50
51 return !cpu->env.runstall && cpu->env.pending_irq_level;
52#else
53 return true;
54#endif
55}
56
57#ifdef CONFIG_USER_ONLY
58static bool abi_call0;
59
60void xtensa_set_abi_call0(void)
61{
62 abi_call0 = true;
63}
64
65bool xtensa_abi_call0(void)
66{
67 return abi_call0;
68}
69#endif
70
71static void xtensa_cpu_reset(DeviceState *dev)
72{
73 CPUState *s = CPU(dev);
74 XtensaCPU *cpu = XTENSA_CPU(s);
75 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
76 CPUXtensaState *env = &cpu->env;
77 bool dfpu = xtensa_option_enabled(env->config,
78 XTENSA_OPTION_DFP_COPROCESSOR);
79
80 xcc->parent_reset(dev);
81
82 env->exception_taken = 0;
83 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
84 env->sregs[LITBASE] &= ~1;
85#ifndef CONFIG_USER_ONLY
86 env->sregs[PS] = xtensa_option_enabled(env->config,
87 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
88 env->pending_irq_level = 0;
89#else
90 env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
91 if (xtensa_option_enabled(env->config,
92 XTENSA_OPTION_WINDOWED_REGISTER) &&
93 !xtensa_abi_call0()) {
94 env->sregs[PS] |= PS_WOE;
95 }
96 env->sregs[CPENABLE] = 0xff;
97#endif
98 env->sregs[VECBASE] = env->config->vecbase;
99 env->sregs[IBREAKENABLE] = 0;
100 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
101 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
102 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
103 env->sregs[CONFIGID0] = env->config->configid[0];
104 env->sregs[CONFIGID1] = env->config->configid[1];
105 env->exclusive_addr = -1;
106
107#ifndef CONFIG_USER_ONLY
108 reset_mmu(env);
109 s->halted = env->runstall;
110#endif
111 set_no_signaling_nans(!dfpu, &env->fp_status);
112 set_use_first_nan(!dfpu, &env->fp_status);
113}
114
115static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
116{
117 ObjectClass *oc;
118 char *typename;
119
120 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
121 oc = object_class_by_name(typename);
122 g_free(typename);
123 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
124 object_class_is_abstract(oc)) {
125 return NULL;
126 }
127 return oc;
128}
129
130static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
131{
132 XtensaCPU *cpu = XTENSA_CPU(cs);
133
134 info->private_data = cpu->env.config->isa;
135 info->print_insn = print_insn_xtensa;
136}
137
138static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
139{
140 CPUState *cs = CPU(dev);
141 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
142 Error *local_err = NULL;
143
144#ifndef CONFIG_USER_ONLY
145 xtensa_irq_init(&XTENSA_CPU(dev)->env);
146#endif
147
148 cpu_exec_realizefn(cs, &local_err);
149 if (local_err != NULL) {
150 error_propagate(errp, local_err);
151 return;
152 }
153
154 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
155
156 qemu_init_vcpu(cs);
157
158 xcc->parent_realize(dev, errp);
159}
160
161static void xtensa_cpu_initfn(Object *obj)
162{
163 XtensaCPU *cpu = XTENSA_CPU(obj);
164 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
165 CPUXtensaState *env = &cpu->env;
166
167 cpu_set_cpustate_pointers(cpu);
168 env->config = xcc->config;
169
170#ifndef CONFIG_USER_ONLY
171 env->address_space_er = g_malloc(sizeof(*env->address_space_er));
172 env->system_er = g_malloc(sizeof(*env->system_er));
173 memory_region_init_io(env->system_er, obj, NULL, env, "er",
174 UINT64_C(0x100000000));
175 address_space_init(env->address_space_er, env->system_er, "ER");
176#endif
177}
178
179static const VMStateDescription vmstate_xtensa_cpu = {
180 .name = "cpu",
181 .unmigratable = 1,
182};
183
184#include "hw/core/tcg-cpu-ops.h"
185
186static struct TCGCPUOps xtensa_tcg_ops = {
187 .initialize = xtensa_translate_init,
188 .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
189 .tlb_fill = xtensa_cpu_tlb_fill,
190 .debug_excp_handler = xtensa_breakpoint_handler,
191
192#ifndef CONFIG_USER_ONLY
193 .do_interrupt = xtensa_cpu_do_interrupt,
194 .do_transaction_failed = xtensa_cpu_do_transaction_failed,
195 .do_unaligned_access = xtensa_cpu_do_unaligned_access,
196#endif
197};
198
199static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
200{
201 DeviceClass *dc = DEVICE_CLASS(oc);
202 CPUClass *cc = CPU_CLASS(oc);
203 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
204
205 device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
206 &xcc->parent_realize);
207
208 device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
209
210 cc->class_by_name = xtensa_cpu_class_by_name;
211 cc->has_work = xtensa_cpu_has_work;
212 cc->dump_state = xtensa_cpu_dump_state;
213 cc->set_pc = xtensa_cpu_set_pc;
214 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
215 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
216 cc->gdb_stop_before_watchpoint = true;
217#ifndef CONFIG_USER_ONLY
218 cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
219#endif
220 cc->disas_set_info = xtensa_cpu_disas_set_info;
221 dc->vmsd = &vmstate_xtensa_cpu;
222 cc->tcg_ops = &xtensa_tcg_ops;
223}
224
225static const TypeInfo xtensa_cpu_type_info = {
226 .name = TYPE_XTENSA_CPU,
227 .parent = TYPE_CPU,
228 .instance_size = sizeof(XtensaCPU),
229 .instance_init = xtensa_cpu_initfn,
230 .abstract = true,
231 .class_size = sizeof(XtensaCPUClass),
232 .class_init = xtensa_cpu_class_init,
233};
234
235static void xtensa_cpu_register_types(void)
236{
237 type_register_static(&xtensa_cpu_type_info);
238}
239
240type_init(xtensa_cpu_register_types)
241
