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25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu/units.h"
28#include "qemu/log.h"
29#include "hw/mips/mips.h"
30#include "hw/pci/pci.h"
31#include "hw/pci/pci_host.h"
32#include "hw/southbridge/piix.h"
33#include "migration/vmstate.h"
34#include "hw/intc/i8259.h"
35#include "hw/irq.h"
36#include "exec/address-spaces.h"
37#include "trace.h"
38#include "qom/object.h"
39
40#define GT_REGS (0x1000 >> 2)
41
42
43#define GT_CPU (0x000 >> 2)
44#define GT_MULTI (0x120 >> 2)
45
46
47#define GT_SCS10LD (0x008 >> 2)
48#define GT_SCS10HD (0x010 >> 2)
49#define GT_SCS32LD (0x018 >> 2)
50#define GT_SCS32HD (0x020 >> 2)
51#define GT_CS20LD (0x028 >> 2)
52#define GT_CS20HD (0x030 >> 2)
53#define GT_CS3BOOTLD (0x038 >> 2)
54#define GT_CS3BOOTHD (0x040 >> 2)
55#define GT_PCI0IOLD (0x048 >> 2)
56#define GT_PCI0IOHD (0x050 >> 2)
57#define GT_PCI0M0LD (0x058 >> 2)
58#define GT_PCI0M0HD (0x060 >> 2)
59#define GT_PCI0M1LD (0x080 >> 2)
60#define GT_PCI0M1HD (0x088 >> 2)
61#define GT_PCI1IOLD (0x090 >> 2)
62#define GT_PCI1IOHD (0x098 >> 2)
63#define GT_PCI1M0LD (0x0a0 >> 2)
64#define GT_PCI1M0HD (0x0a8 >> 2)
65#define GT_PCI1M1LD (0x0b0 >> 2)
66#define GT_PCI1M1HD (0x0b8 >> 2)
67#define GT_ISD (0x068 >> 2)
68
69#define GT_SCS10AR (0x0d0 >> 2)
70#define GT_SCS32AR (0x0d8 >> 2)
71#define GT_CS20R (0x0e0 >> 2)
72#define GT_CS3BOOTR (0x0e8 >> 2)
73
74#define GT_PCI0IOREMAP (0x0f0 >> 2)
75#define GT_PCI0M0REMAP (0x0f8 >> 2)
76#define GT_PCI0M1REMAP (0x100 >> 2)
77#define GT_PCI1IOREMAP (0x108 >> 2)
78#define GT_PCI1M0REMAP (0x110 >> 2)
79#define GT_PCI1M1REMAP (0x118 >> 2)
80
81
82#define GT_CPUERR_ADDRLO (0x070 >> 2)
83#define GT_CPUERR_ADDRHI (0x078 >> 2)
84#define GT_CPUERR_DATALO (0x128 >> 2)
85#define GT_CPUERR_DATAHI (0x130 >> 2)
86#define GT_CPUERR_PARITY (0x138 >> 2)
87
88
89#define GT_PCI0SYNC (0x0c0 >> 2)
90#define GT_PCI1SYNC (0x0c8 >> 2)
91
92
93#define GT_SCS0LD (0x400 >> 2)
94#define GT_SCS0HD (0x404 >> 2)
95#define GT_SCS1LD (0x408 >> 2)
96#define GT_SCS1HD (0x40c >> 2)
97#define GT_SCS2LD (0x410 >> 2)
98#define GT_SCS2HD (0x414 >> 2)
99#define GT_SCS3LD (0x418 >> 2)
100#define GT_SCS3HD (0x41c >> 2)
101#define GT_CS0LD (0x420 >> 2)
102#define GT_CS0HD (0x424 >> 2)
103#define GT_CS1LD (0x428 >> 2)
104#define GT_CS1HD (0x42c >> 2)
105#define GT_CS2LD (0x430 >> 2)
106#define GT_CS2HD (0x434 >> 2)
107#define GT_CS3LD (0x438 >> 2)
108#define GT_CS3HD (0x43c >> 2)
109#define GT_BOOTLD (0x440 >> 2)
110#define GT_BOOTHD (0x444 >> 2)
111#define GT_ADERR (0x470 >> 2)
112
113
114#define GT_SDRAM_CFG (0x448 >> 2)
115#define GT_SDRAM_OPMODE (0x474 >> 2)
116#define GT_SDRAM_BM (0x478 >> 2)
117#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
118
119
120#define GT_SDRAM_B0 (0x44c >> 2)
121#define GT_SDRAM_B1 (0x450 >> 2)
122#define GT_SDRAM_B2 (0x454 >> 2)
123#define GT_SDRAM_B3 (0x458 >> 2)
124
125
126#define GT_DEV_B0 (0x45c >> 2)
127#define GT_DEV_B1 (0x460 >> 2)
128#define GT_DEV_B2 (0x464 >> 2)
129#define GT_DEV_B3 (0x468 >> 2)
130#define GT_DEV_BOOT (0x46c >> 2)
131
132
133#define GT_ECC_ERRDATALO (0x480 >> 2)
134#define GT_ECC_ERRDATAHI (0x484 >> 2)
135#define GT_ECC_MEM (0x488 >> 2)
136#define GT_ECC_CALC (0x48c >> 2)
137#define GT_ECC_ERRADDR (0x490 >> 2)
138
139
140#define GT_DMA0_CNT (0x800 >> 2)
141#define GT_DMA1_CNT (0x804 >> 2)
142#define GT_DMA2_CNT (0x808 >> 2)
143#define GT_DMA3_CNT (0x80c >> 2)
144#define GT_DMA0_SA (0x810 >> 2)
145#define GT_DMA1_SA (0x814 >> 2)
146#define GT_DMA2_SA (0x818 >> 2)
147#define GT_DMA3_SA (0x81c >> 2)
148#define GT_DMA0_DA (0x820 >> 2)
149#define GT_DMA1_DA (0x824 >> 2)
150#define GT_DMA2_DA (0x828 >> 2)
151#define GT_DMA3_DA (0x82c >> 2)
152#define GT_DMA0_NEXT (0x830 >> 2)
153#define GT_DMA1_NEXT (0x834 >> 2)
154#define GT_DMA2_NEXT (0x838 >> 2)
155#define GT_DMA3_NEXT (0x83c >> 2)
156#define GT_DMA0_CUR (0x870 >> 2)
157#define GT_DMA1_CUR (0x874 >> 2)
158#define GT_DMA2_CUR (0x878 >> 2)
159#define GT_DMA3_CUR (0x87c >> 2)
160
161
162#define GT_DMA0_CTRL (0x840 >> 2)
163#define GT_DMA1_CTRL (0x844 >> 2)
164#define GT_DMA2_CTRL (0x848 >> 2)
165#define GT_DMA3_CTRL (0x84c >> 2)
166
167
168#define GT_DMA_ARB (0x860 >> 2)
169
170
171#define GT_TC0 (0x850 >> 2)
172#define GT_TC1 (0x854 >> 2)
173#define GT_TC2 (0x858 >> 2)
174#define GT_TC3 (0x85c >> 2)
175#define GT_TC_CONTROL (0x864 >> 2)
176
177
178#define GT_PCI0_CMD (0xc00 >> 2)
179#define GT_PCI0_TOR (0xc04 >> 2)
180#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
181#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
182#define GT_PCI0_BS_CS20 (0xc10 >> 2)
183#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
184#define GT_PCI1_IACK (0xc30 >> 2)
185#define GT_PCI0_IACK (0xc34 >> 2)
186#define GT_PCI0_BARE (0xc3c >> 2)
187#define GT_PCI0_PREFMBR (0xc40 >> 2)
188#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
189#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
190#define GT_PCI0_CS20_BAR (0xc50 >> 2)
191#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
192#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
193#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
194#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
195#define GT_PCI1_CMD (0xc80 >> 2)
196#define GT_PCI1_TOR (0xc84 >> 2)
197#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
198#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
199#define GT_PCI1_BS_CS20 (0xc90 >> 2)
200#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
201#define GT_PCI1_BARE (0xcbc >> 2)
202#define GT_PCI1_PREFMBR (0xcc0 >> 2)
203#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
204#define GT_PCI1_SCS32_BAR (0xccc >> 2)
205#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
206#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
207#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
208#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
209#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
210#define GT_PCI1_CFGADDR (0xcf0 >> 2)
211#define GT_PCI1_CFGDATA (0xcf4 >> 2)
212#define GT_PCI0_CFGADDR (0xcf8 >> 2)
213#define GT_PCI0_CFGDATA (0xcfc >> 2)
214
215
216#define GT_INTRCAUSE (0xc18 >> 2)
217#define GT_INTRMASK (0xc1c >> 2)
218#define GT_PCI0_ICMASK (0xc24 >> 2)
219#define GT_PCI0_SERR0MASK (0xc28 >> 2)
220#define GT_CPU_INTSEL (0xc70 >> 2)
221#define GT_PCI0_INTSEL (0xc74 >> 2)
222#define GT_HINTRCAUSE (0xc98 >> 2)
223#define GT_HINTRMASK (0xc9c >> 2)
224#define GT_PCI0_HICMASK (0xca4 >> 2)
225#define GT_PCI1_SERR1MASK (0xca8 >> 2)
226
227#define PCI_MAPPING_ENTRY(regname) \
228 hwaddr regname ##_start; \
229 hwaddr regname ##_length; \
230 MemoryRegion regname ##_mem
231
232#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
233
234OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE)
235
236struct GT64120State {
237 PCIHostState parent_obj;
238
239 uint32_t regs[GT_REGS];
240 PCI_MAPPING_ENTRY(PCI0IO);
241 PCI_MAPPING_ENTRY(PCI0M0);
242 PCI_MAPPING_ENTRY(PCI0M1);
243 PCI_MAPPING_ENTRY(ISD);
244 MemoryRegion pci0_mem;
245 AddressSpace pci0_mem_as;
246};
247
248
249
250
251
252
253static void check_reserved_space(hwaddr *start, hwaddr *length)
254{
255 hwaddr begin = *start;
256 hwaddr end = *start + *length;
257
258 if (end >= 0x1e000000LL && end < 0x1f100000LL) {
259 end = 0x1e000000LL;
260 }
261 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
262 begin = 0x1f100000LL;
263 }
264 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
265 end = 0x1fc00000LL;
266 }
267 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
268 begin = 0x1fd00000LL;
269 }
270
271 if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
272 end = 0x1e000000LL;
273 }
274 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
275 end = 0x1fc00000LL;
276 }
277
278 *start = begin;
279 *length = end - begin;
280}
281
282static void gt64120_isd_mapping(GT64120State *s)
283{
284
285 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
286 hwaddr length = 0x1000;
287
288 if (s->ISD_length) {
289 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
290 }
291 check_reserved_space(&start, &length);
292 length = 0x1000;
293
294 trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);
295 s->ISD_start = start;
296 s->ISD_length = length;
297 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
298}
299
300static void gt64120_pci_mapping(GT64120State *s)
301{
302
303 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
304
305 if (s->PCI0IO_length) {
306 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
307 object_unparent(OBJECT(&s->PCI0IO_mem));
308 }
309
310 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
311 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
312 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
313 if (s->PCI0IO_length) {
314 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
315 get_system_io(), 0, s->PCI0IO_length);
316 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
317 &s->PCI0IO_mem);
318 }
319 }
320
321
322 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
323
324 if (s->PCI0M0_length) {
325 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
326 object_unparent(OBJECT(&s->PCI0M0_mem));
327 }
328
329 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
330 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
331 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
332 if (s->PCI0M0_length) {
333 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
334 &s->pci0_mem, s->PCI0M0_start,
335 s->PCI0M0_length);
336 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
337 &s->PCI0M0_mem);
338 }
339 }
340
341
342 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
343
344 if (s->PCI0M1_length) {
345 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
346 object_unparent(OBJECT(&s->PCI0M1_mem));
347 }
348
349 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
350 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
351 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
352 if (s->PCI0M1_length) {
353 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
354 &s->pci0_mem, s->PCI0M1_start,
355 s->PCI0M1_length);
356 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
357 &s->PCI0M1_mem);
358 }
359 }
360}
361
362static int gt64120_post_load(void *opaque, int version_id)
363{
364 GT64120State *s = opaque;
365
366 gt64120_isd_mapping(s);
367 gt64120_pci_mapping(s);
368
369 return 0;
370}
371
372static const VMStateDescription vmstate_gt64120 = {
373 .name = "gt64120",
374 .version_id = 1,
375 .minimum_version_id = 1,
376 .post_load = gt64120_post_load,
377 .fields = (VMStateField[]) {
378 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
379 VMSTATE_END_OF_LIST()
380 }
381};
382
383static void gt64120_writel(void *opaque, hwaddr addr,
384 uint64_t val, unsigned size)
385{
386 GT64120State *s = opaque;
387 PCIHostState *phb = PCI_HOST_BRIDGE(s);
388 uint32_t saddr = addr >> 2;
389
390 trace_gt64120_write(addr, val);
391 if (!(s->regs[GT_CPU] & 0x00001000)) {
392 val = bswap32(val);
393 }
394
395 switch (saddr) {
396
397
398 case GT_CPU:
399 s->regs[GT_CPU] = val;
400 break;
401 case GT_MULTI:
402
403 break;
404
405
406 case GT_PCI0IOLD:
407 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
408 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
409 gt64120_pci_mapping(s);
410 break;
411 case GT_PCI0M0LD:
412 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
413 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
414 gt64120_pci_mapping(s);
415 break;
416 case GT_PCI0M1LD:
417 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
418 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
419 gt64120_pci_mapping(s);
420 break;
421 case GT_PCI1IOLD:
422 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
423 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
424 break;
425 case GT_PCI1M0LD:
426 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
427 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
428 break;
429 case GT_PCI1M1LD:
430 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
431 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
432 break;
433 case GT_PCI0M0HD:
434 case GT_PCI0M1HD:
435 case GT_PCI0IOHD:
436 s->regs[saddr] = val & 0x0000007f;
437 gt64120_pci_mapping(s);
438 break;
439 case GT_PCI1IOHD:
440 case GT_PCI1M0HD:
441 case GT_PCI1M1HD:
442 s->regs[saddr] = val & 0x0000007f;
443 break;
444 case GT_ISD:
445 s->regs[saddr] = val & 0x00007fff;
446 gt64120_isd_mapping(s);
447 break;
448
449 case GT_PCI0IOREMAP:
450 case GT_PCI0M0REMAP:
451 case GT_PCI0M1REMAP:
452 case GT_PCI1IOREMAP:
453 case GT_PCI1M0REMAP:
454 case GT_PCI1M1REMAP:
455 s->regs[saddr] = val & 0x000007ff;
456 break;
457
458
459 case GT_CPUERR_ADDRLO:
460 case GT_CPUERR_ADDRHI:
461 case GT_CPUERR_DATALO:
462 case GT_CPUERR_DATAHI:
463 case GT_CPUERR_PARITY:
464
465 qemu_log_mask(LOG_GUEST_ERROR,
466 "gt64120: Read-only register write "
467 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
468 saddr << 2, size, size << 1, val);
469 break;
470
471
472 case GT_PCI0SYNC:
473 case GT_PCI1SYNC:
474
475 qemu_log_mask(LOG_GUEST_ERROR,
476 "gt64120: Read-only register write "
477 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
478 saddr << 2, size, size << 1, val);
479 break;
480
481
482 case GT_SCS0LD:
483 case GT_SCS0HD:
484 case GT_SCS1LD:
485 case GT_SCS1HD:
486 case GT_SCS2LD:
487 case GT_SCS2HD:
488 case GT_SCS3LD:
489 case GT_SCS3HD:
490 case GT_CS0LD:
491 case GT_CS0HD:
492 case GT_CS1LD:
493 case GT_CS1HD:
494 case GT_CS2LD:
495 case GT_CS2HD:
496 case GT_CS3LD:
497 case GT_CS3HD:
498 case GT_BOOTLD:
499 case GT_BOOTHD:
500 case GT_ADERR:
501
502 case GT_SDRAM_CFG:
503 case GT_SDRAM_OPMODE:
504 case GT_SDRAM_BM:
505 case GT_SDRAM_ADDRDECODE:
506
507 s->regs[saddr] = val;
508 break;
509
510
511 case GT_DEV_B0:
512 case GT_DEV_B1:
513 case GT_DEV_B2:
514 case GT_DEV_B3:
515 case GT_DEV_BOOT:
516
517 qemu_log_mask(LOG_UNIMP,
518 "gt64120: Unimplemented device register write "
519 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
520 saddr << 2, size, size << 1, val);
521 break;
522
523
524 case GT_ECC_ERRDATALO:
525 case GT_ECC_ERRDATAHI:
526 case GT_ECC_MEM:
527 case GT_ECC_CALC:
528 case GT_ECC_ERRADDR:
529
530 qemu_log_mask(LOG_GUEST_ERROR,
531 "gt64120: Read-only register write "
532 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
533 saddr << 2, size, size << 1, val);
534 break;
535
536
537 case GT_DMA0_CNT:
538 case GT_DMA1_CNT:
539 case GT_DMA2_CNT:
540 case GT_DMA3_CNT:
541 case GT_DMA0_SA:
542 case GT_DMA1_SA:
543 case GT_DMA2_SA:
544 case GT_DMA3_SA:
545 case GT_DMA0_DA:
546 case GT_DMA1_DA:
547 case GT_DMA2_DA:
548 case GT_DMA3_DA:
549 case GT_DMA0_NEXT:
550 case GT_DMA1_NEXT:
551 case GT_DMA2_NEXT:
552 case GT_DMA3_NEXT:
553 case GT_DMA0_CUR:
554 case GT_DMA1_CUR:
555 case GT_DMA2_CUR:
556 case GT_DMA3_CUR:
557
558
559 case GT_DMA0_CTRL:
560 case GT_DMA1_CTRL:
561 case GT_DMA2_CTRL:
562 case GT_DMA3_CTRL:
563
564
565 case GT_DMA_ARB:
566
567 qemu_log_mask(LOG_UNIMP,
568 "gt64120: Unimplemented DMA register write "
569 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
570 saddr << 2, size, size << 1, val);
571 break;
572
573
574 case GT_TC0:
575 case GT_TC1:
576 case GT_TC2:
577 case GT_TC3:
578 case GT_TC_CONTROL:
579
580 qemu_log_mask(LOG_UNIMP,
581 "gt64120: Unimplemented timer register write "
582 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
583 saddr << 2, size, size << 1, val);
584 break;
585
586
587 case GT_PCI0_CMD:
588 case GT_PCI1_CMD:
589 s->regs[saddr] = val & 0x0401fc0f;
590 break;
591 case GT_PCI0_TOR:
592 case GT_PCI0_BS_SCS10:
593 case GT_PCI0_BS_SCS32:
594 case GT_PCI0_BS_CS20:
595 case GT_PCI0_BS_CS3BT:
596 case GT_PCI1_IACK:
597 case GT_PCI0_IACK:
598 case GT_PCI0_BARE:
599 case GT_PCI0_PREFMBR:
600 case GT_PCI0_SCS10_BAR:
601 case GT_PCI0_SCS32_BAR:
602 case GT_PCI0_CS20_BAR:
603 case GT_PCI0_CS3BT_BAR:
604 case GT_PCI0_SSCS10_BAR:
605 case GT_PCI0_SSCS32_BAR:
606 case GT_PCI0_SCS3BT_BAR:
607 case GT_PCI1_TOR:
608 case GT_PCI1_BS_SCS10:
609 case GT_PCI1_BS_SCS32:
610 case GT_PCI1_BS_CS20:
611 case GT_PCI1_BS_CS3BT:
612 case GT_PCI1_BARE:
613 case GT_PCI1_PREFMBR:
614 case GT_PCI1_SCS10_BAR:
615 case GT_PCI1_SCS32_BAR:
616 case GT_PCI1_CS20_BAR:
617 case GT_PCI1_CS3BT_BAR:
618 case GT_PCI1_SSCS10_BAR:
619 case GT_PCI1_SSCS32_BAR:
620 case GT_PCI1_SCS3BT_BAR:
621 case GT_PCI1_CFGADDR:
622 case GT_PCI1_CFGDATA:
623
624 qemu_log_mask(LOG_UNIMP,
625 "gt64120: Unimplemented PCI register write "
626 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
627 saddr << 2, size, size << 1, val);
628 break;
629 case GT_PCI0_CFGADDR:
630 phb->config_reg = val & 0x80fffffc;
631 break;
632 case GT_PCI0_CFGDATA:
633 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
634 val = bswap32(val);
635 }
636 if (phb->config_reg & (1u << 31)) {
637 pci_data_write(phb->bus, phb->config_reg, val, 4);
638 }
639 break;
640
641
642 case GT_INTRCAUSE:
643
644 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
645 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
646 trace_gt64120_write_intreg("INTRCAUSE", size, val);
647 break;
648 case GT_INTRMASK:
649 s->regs[saddr] = val & 0x3c3ffffe;
650 trace_gt64120_write_intreg("INTRMASK", size, val);
651 break;
652 case GT_PCI0_ICMASK:
653 s->regs[saddr] = val & 0x03fffffe;
654 trace_gt64120_write_intreg("ICMASK", size, val);
655 break;
656 case GT_PCI0_SERR0MASK:
657 s->regs[saddr] = val & 0x0000003f;
658 trace_gt64120_write_intreg("SERR0MASK", size, val);
659 break;
660
661
662 case GT_HINTRCAUSE:
663 case GT_CPU_INTSEL:
664 case GT_PCI0_INTSEL:
665 case GT_HINTRMASK:
666 case GT_PCI0_HICMASK:
667 case GT_PCI1_SERR1MASK:
668
669 break;
670
671
672 case GT_SDRAM_B0:
673 case GT_SDRAM_B1:
674 case GT_SDRAM_B2:
675 case GT_SDRAM_B3:
676
677
678
679
680 s->regs[saddr] = val;
681 break;
682
683 default:
684 qemu_log_mask(LOG_GUEST_ERROR,
685 "gt64120: Illegal register write "
686 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
687 saddr << 2, size, size << 1, val);
688 break;
689 }
690}
691
692static uint64_t gt64120_readl(void *opaque,
693 hwaddr addr, unsigned size)
694{
695 GT64120State *s = opaque;
696 PCIHostState *phb = PCI_HOST_BRIDGE(s);
697 uint32_t val;
698 uint32_t saddr = addr >> 2;
699
700 switch (saddr) {
701
702
703 case GT_MULTI:
704
705
706
707
708 val = s->regs[saddr];
709 break;
710
711
712 case GT_CPUERR_ADDRLO:
713 case GT_CPUERR_ADDRHI:
714 case GT_CPUERR_DATALO:
715 case GT_CPUERR_DATAHI:
716 case GT_CPUERR_PARITY:
717
718 val = s->regs[saddr];
719 break;
720
721
722 case GT_PCI0SYNC:
723 case GT_PCI1SYNC:
724
725
726
727
728
729 val = 0xc000ffee;
730 break;
731
732
733 case GT_ECC_ERRDATALO:
734 case GT_ECC_ERRDATAHI:
735 case GT_ECC_MEM:
736 case GT_ECC_CALC:
737 case GT_ECC_ERRADDR:
738
739 val = s->regs[saddr];
740 break;
741
742 case GT_CPU:
743 case GT_SCS10LD:
744 case GT_SCS10HD:
745 case GT_SCS32LD:
746 case GT_SCS32HD:
747 case GT_CS20LD:
748 case GT_CS20HD:
749 case GT_CS3BOOTLD:
750 case GT_CS3BOOTHD:
751 case GT_SCS10AR:
752 case GT_SCS32AR:
753 case GT_CS20R:
754 case GT_CS3BOOTR:
755 case GT_PCI0IOLD:
756 case GT_PCI0M0LD:
757 case GT_PCI0M1LD:
758 case GT_PCI1IOLD:
759 case GT_PCI1M0LD:
760 case GT_PCI1M1LD:
761 case GT_PCI0IOHD:
762 case GT_PCI0M0HD:
763 case GT_PCI0M1HD:
764 case GT_PCI1IOHD:
765 case GT_PCI1M0HD:
766 case GT_PCI1M1HD:
767 case GT_PCI0IOREMAP:
768 case GT_PCI0M0REMAP:
769 case GT_PCI0M1REMAP:
770 case GT_PCI1IOREMAP:
771 case GT_PCI1M0REMAP:
772 case GT_PCI1M1REMAP:
773 case GT_ISD:
774 val = s->regs[saddr];
775 break;
776 case GT_PCI0_IACK:
777
778 val = pic_read_irq(isa_pic);
779 break;
780
781
782 case GT_SCS0LD:
783 case GT_SCS0HD:
784 case GT_SCS1LD:
785 case GT_SCS1HD:
786 case GT_SCS2LD:
787 case GT_SCS2HD:
788 case GT_SCS3LD:
789 case GT_SCS3HD:
790 case GT_CS0LD:
791 case GT_CS0HD:
792 case GT_CS1LD:
793 case GT_CS1HD:
794 case GT_CS2LD:
795 case GT_CS2HD:
796 case GT_CS3LD:
797 case GT_CS3HD:
798 case GT_BOOTLD:
799 case GT_BOOTHD:
800 case GT_ADERR:
801 val = s->regs[saddr];
802 break;
803
804
805 case GT_SDRAM_CFG:
806 case GT_SDRAM_OPMODE:
807 case GT_SDRAM_BM:
808 case GT_SDRAM_ADDRDECODE:
809 val = s->regs[saddr];
810 break;
811
812
813 case GT_SDRAM_B0:
814 case GT_SDRAM_B1:
815 case GT_SDRAM_B2:
816 case GT_SDRAM_B3:
817
818
819
820
821 val = s->regs[saddr];
822 break;
823
824
825 case GT_DEV_B0:
826 case GT_DEV_B1:
827 case GT_DEV_B2:
828 case GT_DEV_B3:
829 case GT_DEV_BOOT:
830 val = s->regs[saddr];
831 break;
832
833
834 case GT_DMA0_CNT:
835 case GT_DMA1_CNT:
836 case GT_DMA2_CNT:
837 case GT_DMA3_CNT:
838 case GT_DMA0_SA:
839 case GT_DMA1_SA:
840 case GT_DMA2_SA:
841 case GT_DMA3_SA:
842 case GT_DMA0_DA:
843 case GT_DMA1_DA:
844 case GT_DMA2_DA:
845 case GT_DMA3_DA:
846 case GT_DMA0_NEXT:
847 case GT_DMA1_NEXT:
848 case GT_DMA2_NEXT:
849 case GT_DMA3_NEXT:
850 case GT_DMA0_CUR:
851 case GT_DMA1_CUR:
852 case GT_DMA2_CUR:
853 case GT_DMA3_CUR:
854 val = s->regs[saddr];
855 break;
856
857
858 case GT_DMA0_CTRL:
859 case GT_DMA1_CTRL:
860 case GT_DMA2_CTRL:
861 case GT_DMA3_CTRL:
862 val = s->regs[saddr];
863 break;
864
865
866 case GT_DMA_ARB:
867 val = s->regs[saddr];
868 break;
869
870
871 case GT_TC0:
872 case GT_TC1:
873 case GT_TC2:
874 case GT_TC3:
875 case GT_TC_CONTROL:
876 val = s->regs[saddr];
877 break;
878
879
880 case GT_PCI0_CFGADDR:
881 val = phb->config_reg;
882 break;
883 case GT_PCI0_CFGDATA:
884 if (!(phb->config_reg & (1 << 31))) {
885 val = 0xffffffff;
886 } else {
887 val = pci_data_read(phb->bus, phb->config_reg, 4);
888 }
889 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
890 val = bswap32(val);
891 }
892 break;
893
894 case GT_PCI0_CMD:
895 case GT_PCI0_TOR:
896 case GT_PCI0_BS_SCS10:
897 case GT_PCI0_BS_SCS32:
898 case GT_PCI0_BS_CS20:
899 case GT_PCI0_BS_CS3BT:
900 case GT_PCI1_IACK:
901 case GT_PCI0_BARE:
902 case GT_PCI0_PREFMBR:
903 case GT_PCI0_SCS10_BAR:
904 case GT_PCI0_SCS32_BAR:
905 case GT_PCI0_CS20_BAR:
906 case GT_PCI0_CS3BT_BAR:
907 case GT_PCI0_SSCS10_BAR:
908 case GT_PCI0_SSCS32_BAR:
909 case GT_PCI0_SCS3BT_BAR:
910 case GT_PCI1_CMD:
911 case GT_PCI1_TOR:
912 case GT_PCI1_BS_SCS10:
913 case GT_PCI1_BS_SCS32:
914 case GT_PCI1_BS_CS20:
915 case GT_PCI1_BS_CS3BT:
916 case GT_PCI1_BARE:
917 case GT_PCI1_PREFMBR:
918 case GT_PCI1_SCS10_BAR:
919 case GT_PCI1_SCS32_BAR:
920 case GT_PCI1_CS20_BAR:
921 case GT_PCI1_CS3BT_BAR:
922 case GT_PCI1_SSCS10_BAR:
923 case GT_PCI1_SSCS32_BAR:
924 case GT_PCI1_SCS3BT_BAR:
925 case GT_PCI1_CFGADDR:
926 case GT_PCI1_CFGDATA:
927 val = s->regs[saddr];
928 break;
929
930
931 case GT_INTRCAUSE:
932 val = s->regs[saddr];
933 trace_gt64120_read_intreg("INTRCAUSE", size, val);
934 break;
935 case GT_INTRMASK:
936 val = s->regs[saddr];
937 trace_gt64120_read_intreg("INTRMASK", size, val);
938 break;
939 case GT_PCI0_ICMASK:
940 val = s->regs[saddr];
941 trace_gt64120_read_intreg("ICMASK", size, val);
942 break;
943 case GT_PCI0_SERR0MASK:
944 val = s->regs[saddr];
945 trace_gt64120_read_intreg("SERR0MASK", size, val);
946 break;
947
948
949 case GT_HINTRCAUSE:
950 case GT_CPU_INTSEL:
951 case GT_PCI0_INTSEL:
952 case GT_HINTRMASK:
953 case GT_PCI0_HICMASK:
954 case GT_PCI1_SERR1MASK:
955 val = s->regs[saddr];
956 break;
957
958 default:
959 val = s->regs[saddr];
960 qemu_log_mask(LOG_GUEST_ERROR,
961 "gt64120: Illegal register read "
962 "reg:0x%03x size:%u value:0x%0*x\n",
963 saddr << 2, size, size << 1, val);
964 break;
965 }
966
967 if (!(s->regs[GT_CPU] & 0x00001000)) {
968 val = bswap32(val);
969 }
970 trace_gt64120_read(addr, val);
971
972 return val;
973}
974
975static const MemoryRegionOps isd_mem_ops = {
976 .read = gt64120_readl,
977 .write = gt64120_writel,
978 .endianness = DEVICE_NATIVE_ENDIAN,
979 .impl = {
980 .min_access_size = 4,
981 .max_access_size = 4,
982 },
983};
984
985static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
986{
987 int slot;
988
989 slot = PCI_SLOT(pci_dev->devfn);
990
991 switch (slot) {
992
993 case 10:
994 return 3;
995
996 case 11:
997 return 1;
998
999 case 12:
1000 return 2;
1001
1002 case 18 ... 21:
1003 return ((slot - 18) + irq_num) & 0x03;
1004
1005 default:
1006 return irq_num;
1007 }
1008}
1009
1010static int pci_irq_levels[4];
1011
1012static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
1013{
1014 int i, pic_irq, pic_level;
1015 qemu_irq *pic = opaque;
1016
1017 pci_irq_levels[irq_num] = level;
1018
1019
1020
1021 pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
1022 if (pic_irq < 16) {
1023
1024 pic_level = 0;
1025 for (i = 0; i < 4; i++) {
1026 if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
1027 pic_level |= pci_irq_levels[i];
1028 }
1029 }
1030 qemu_set_irq(pic[pic_irq], pic_level);
1031 }
1032}
1033
1034
1035static void gt64120_reset(DeviceState *dev)
1036{
1037 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1038
1039
1040
1041
1042#ifdef TARGET_WORDS_BIGENDIAN
1043 s->regs[GT_CPU] = 0x00000000;
1044#else
1045 s->regs[GT_CPU] = 0x00001000;
1046#endif
1047 s->regs[GT_MULTI] = 0x00000003;
1048
1049
1050 s->regs[GT_SCS10LD] = 0x00000000;
1051 s->regs[GT_SCS10HD] = 0x00000007;
1052 s->regs[GT_SCS32LD] = 0x00000008;
1053 s->regs[GT_SCS32HD] = 0x0000000f;
1054 s->regs[GT_CS20LD] = 0x000000e0;
1055 s->regs[GT_CS20HD] = 0x00000070;
1056 s->regs[GT_CS3BOOTLD] = 0x000000f8;
1057 s->regs[GT_CS3BOOTHD] = 0x0000007f;
1058
1059 s->regs[GT_PCI0IOLD] = 0x00000080;
1060 s->regs[GT_PCI0IOHD] = 0x0000000f;
1061 s->regs[GT_PCI0M0LD] = 0x00000090;
1062 s->regs[GT_PCI0M0HD] = 0x0000001f;
1063 s->regs[GT_ISD] = 0x000000a0;
1064 s->regs[GT_PCI0M1LD] = 0x00000790;
1065 s->regs[GT_PCI0M1HD] = 0x0000001f;
1066 s->regs[GT_PCI1IOLD] = 0x00000100;
1067 s->regs[GT_PCI1IOHD] = 0x0000000f;
1068 s->regs[GT_PCI1M0LD] = 0x00000110;
1069 s->regs[GT_PCI1M0HD] = 0x0000001f;
1070 s->regs[GT_PCI1M1LD] = 0x00000120;
1071 s->regs[GT_PCI1M1HD] = 0x0000002f;
1072
1073 s->regs[GT_SCS10AR] = 0x00000000;
1074 s->regs[GT_SCS32AR] = 0x00000008;
1075 s->regs[GT_CS20R] = 0x000000e0;
1076 s->regs[GT_CS3BOOTR] = 0x000000f8;
1077
1078 s->regs[GT_PCI0IOREMAP] = 0x00000080;
1079 s->regs[GT_PCI0M0REMAP] = 0x00000090;
1080 s->regs[GT_PCI0M1REMAP] = 0x00000790;
1081 s->regs[GT_PCI1IOREMAP] = 0x00000100;
1082 s->regs[GT_PCI1M0REMAP] = 0x00000110;
1083 s->regs[GT_PCI1M1REMAP] = 0x00000120;
1084
1085
1086 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1087 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1088 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1089 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1090 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1091
1092
1093 s->regs[GT_PCI0SYNC] = 0x00000000;
1094 s->regs[GT_PCI1SYNC] = 0x00000000;
1095
1096
1097 s->regs[GT_SCS0LD] = 0x00000000;
1098 s->regs[GT_SCS0HD] = 0x00000007;
1099 s->regs[GT_SCS1LD] = 0x00000008;
1100 s->regs[GT_SCS1HD] = 0x0000000f;
1101 s->regs[GT_SCS2LD] = 0x00000010;
1102 s->regs[GT_SCS2HD] = 0x00000017;
1103 s->regs[GT_SCS3LD] = 0x00000018;
1104 s->regs[GT_SCS3HD] = 0x0000001f;
1105 s->regs[GT_CS0LD] = 0x000000c0;
1106 s->regs[GT_CS0HD] = 0x000000c7;
1107 s->regs[GT_CS1LD] = 0x000000c8;
1108 s->regs[GT_CS1HD] = 0x000000cf;
1109 s->regs[GT_CS2LD] = 0x000000d0;
1110 s->regs[GT_CS2HD] = 0x000000df;
1111 s->regs[GT_CS3LD] = 0x000000f0;
1112 s->regs[GT_CS3HD] = 0x000000fb;
1113 s->regs[GT_BOOTLD] = 0x000000fc;
1114 s->regs[GT_BOOTHD] = 0x000000ff;
1115 s->regs[GT_ADERR] = 0xffffffff;
1116
1117
1118 s->regs[GT_SDRAM_CFG] = 0x00000200;
1119 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1120 s->regs[GT_SDRAM_BM] = 0x00000007;
1121 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1122
1123
1124 s->regs[GT_SDRAM_B0] = 0x00000005;
1125 s->regs[GT_SDRAM_B1] = 0x00000005;
1126 s->regs[GT_SDRAM_B2] = 0x00000005;
1127 s->regs[GT_SDRAM_B3] = 0x00000005;
1128
1129
1130 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1131 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1132 s->regs[GT_ECC_MEM] = 0x00000000;
1133 s->regs[GT_ECC_CALC] = 0x00000000;
1134 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1135
1136
1137 s->regs[GT_DEV_B0] = 0x386fffff;
1138 s->regs[GT_DEV_B1] = 0x386fffff;
1139 s->regs[GT_DEV_B2] = 0x386fffff;
1140 s->regs[GT_DEV_B3] = 0x386fffff;
1141 s->regs[GT_DEV_BOOT] = 0x146fffff;
1142
1143
1144
1145
1146 s->regs[GT_TC0] = 0xffffffff;
1147 s->regs[GT_TC1] = 0x00ffffff;
1148 s->regs[GT_TC2] = 0x00ffffff;
1149 s->regs[GT_TC3] = 0x00ffffff;
1150 s->regs[GT_TC_CONTROL] = 0x00000000;
1151
1152
1153#ifdef TARGET_WORDS_BIGENDIAN
1154 s->regs[GT_PCI0_CMD] = 0x00000000;
1155#else
1156 s->regs[GT_PCI0_CMD] = 0x00010001;
1157#endif
1158 s->regs[GT_PCI0_TOR] = 0x0000070f;
1159 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1160 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1161 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1162 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1163 s->regs[GT_PCI1_IACK] = 0x00000000;
1164 s->regs[GT_PCI0_IACK] = 0x00000000;
1165 s->regs[GT_PCI0_BARE] = 0x0000000f;
1166 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1167 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1168 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1169 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1170 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1171 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1172 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1173 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1174#ifdef TARGET_WORDS_BIGENDIAN
1175 s->regs[GT_PCI1_CMD] = 0x00000000;
1176#else
1177 s->regs[GT_PCI1_CMD] = 0x00010001;
1178#endif
1179 s->regs[GT_PCI1_TOR] = 0x0000070f;
1180 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1181 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1182 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1183 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1184 s->regs[GT_PCI1_BARE] = 0x0000000f;
1185 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1186 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1187 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1188 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1189 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1190 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1191 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1192 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1193 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1194 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1195 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1196
1197
1198
1199 gt64120_isd_mapping(s);
1200 gt64120_pci_mapping(s);
1201}
1202
1203static void gt64120_realize(DeviceState *dev, Error **errp)
1204{
1205 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1206
1207 memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
1208 "gt64120-isd", 0x1000);
1209}
1210
1211PCIBus *gt64120_register(qemu_irq *pic)
1212{
1213 GT64120State *d;
1214 PCIHostState *phb;
1215 DeviceState *dev;
1216
1217 dev = qdev_new(TYPE_GT64120_PCI_HOST_BRIDGE);
1218 d = GT64120_PCI_HOST_BRIDGE(dev);
1219 phb = PCI_HOST_BRIDGE(dev);
1220 memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
1221 address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
1222 phb->bus = pci_register_root_bus(dev, "pci",
1223 gt64120_pci_set_irq, gt64120_pci_map_irq,
1224 pic,
1225 &d->pci0_mem,
1226 get_system_io(),
1227 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
1228 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1229
1230 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1231 return phb->bus;
1232}
1233
1234static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1235{
1236
1237 pci_set_word(d->config + PCI_COMMAND, 0);
1238 pci_set_word(d->config + PCI_STATUS,
1239 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1240 pci_config_set_prog_interface(d->config, 0);
1241 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1242 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1243 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1244 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1245 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1246 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1247 pci_set_byte(d->config + 0x3d, 0x01);
1248}
1249
1250static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1251{
1252 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1253 DeviceClass *dc = DEVICE_CLASS(klass);
1254
1255 k->realize = gt64120_pci_realize;
1256 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1257 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1258 k->revision = 0x10;
1259 k->class_id = PCI_CLASS_BRIDGE_HOST;
1260
1261
1262
1263
1264 dc->user_creatable = false;
1265}
1266
1267static const TypeInfo gt64120_pci_info = {
1268 .name = "gt64120_pci",
1269 .parent = TYPE_PCI_DEVICE,
1270 .instance_size = sizeof(PCIDevice),
1271 .class_init = gt64120_pci_class_init,
1272 .interfaces = (InterfaceInfo[]) {
1273 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1274 { },
1275 },
1276};
1277
1278static void gt64120_class_init(ObjectClass *klass, void *data)
1279{
1280 DeviceClass *dc = DEVICE_CLASS(klass);
1281
1282 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1283 dc->realize = gt64120_realize;
1284 dc->reset = gt64120_reset;
1285 dc->vmsd = &vmstate_gt64120;
1286}
1287
1288static const TypeInfo gt64120_info = {
1289 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1290 .parent = TYPE_PCI_HOST_BRIDGE,
1291 .instance_size = sizeof(GT64120State),
1292 .class_init = gt64120_class_init,
1293};
1294
1295static void gt64120_pci_register_types(void)
1296{
1297 type_register_static(>64120_info);
1298 type_register_static(>64120_pci_info);
1299}
1300
1301type_init(gt64120_pci_register_types)
1302
