LXR qemu/hw/mips/mips

   1/*
   2 * QEMU MIPS interrupt support
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a copy
   5 * of this software and associated documentation files (the "Software"), to deal
   6 * in the Software without restriction, including without limitation the rights
   7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8 * copies of the Software, and to permit persons to whom the Software is
   9 * furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20 * THE SOFTWARE.
  21 */
  22
  23#include "qemu/osdep.h"
  24#include "qemu/main-loop.h"
  25#include "hw/irq.h"
  26#include "hw/mips/cpudevs.h"
  27#include "cpu.h"
  28#include "sysemu/kvm.h"
  29#include "kvm_mips.h"
  30
  31static void cpu_mips_irq_request(void *opaque, int irq, int level)
  32{
  33    MIPSCPU *cpu = opaque;
  34    CPUMIPSState *env = &cpu->env;
  35    CPUState *cs = CPU(cpu);
  36    bool locked = false;
  37
  38    if (irq < 0 || irq > 7) {
  39        return;
  40    }
  41
  42    /* Make sure locking works even if BQL is already held by the caller */
  43    if (!qemu_mutex_iothread_locked()) {
  44        locked = true;
  45        qemu_mutex_lock_iothread();
  46    }
  47
  48    if (level) {
  49        env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
  50    } else {
  51        env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
  52    }
  53
  54    if (kvm_enabled() && (irq == 2 || irq == 3)) {
  55        kvm_mips_set_interrupt(cpu, irq, level);
  56    }
  57
  58    if (env->CP0_Cause & CP0Ca_IP_mask) {
  59        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  60    } else {
  61        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  62    }
  63
  64    if (locked) {
  65        qemu_mutex_unlock_iothread();
  66    }
  67}
  68
  69void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
  70{
  71    CPUMIPSState *env = &cpu->env;
  72    qemu_irq *qi;
  73    int i;
  74
  75    qi = qemu_allocate_irqs(cpu_mips_irq_request, cpu, 8);
  76    for (i = 0; i < 8; i++) {
  77        env->irq[i] = qi[i];
  78    }
  79    g_free(qi);
  80}
  81
  82void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
  83{
  84    if (irq < 0 || irq > 2) {
  85        return;
  86    }
  87
  88    qemu_set_irq(env->irq[irq], level);
  89}
  90