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27#include "qemu/osdep.h"
28#include "hw/irq.h"
29#include "hw/qdev-properties.h"
30#include "hw/sysbus.h"
31#include "migration/vmstate.h"
32#include "qemu/log.h"
33#include "qemu/module.h"
34#include "net/net.h"
35#include "qom/object.h"
36
37#ifdef DEBUG_XGMAC
38#define DEBUGF_BRK(message, args...) do { \
39 fprintf(stderr, (message), ## args); \
40 } while (0)
41#else
42#define DEBUGF_BRK(message, args...) do { } while (0)
43#endif
44
45#define XGMAC_CONTROL 0x00000000
46#define XGMAC_FRAME_FILTER 0x00000001
47#define XGMAC_FLOW_CTRL 0x00000006
48#define XGMAC_VLAN_TAG 0x00000007
49#define XGMAC_VERSION 0x00000008
50
51#define XGMAC_VLAN_INCL 0x00000009
52#define XGMAC_LPI_CTRL 0x0000000a
53#define XGMAC_LPI_TIMER 0x0000000b
54#define XGMAC_TX_PACE 0x0000000c
55#define XGMAC_VLAN_HASH 0x0000000d
56#define XGMAC_DEBUG 0x0000000e
57#define XGMAC_INT_STATUS 0x0000000f
58
59#define XGMAC_HASH(n) ((0x00000300/4) + (n))
60#define XGMAC_NUM_HASH 16
61
62#define XGMAC_OPMODE (0x00000400/4)
63
64#define XGMAC_REMOTE_WAKE (0x00000700/4)
65
66#define XGMAC_PMT (0x00000704/4)
67
68#define XGMAC_ADDR_HIGH(reg) (0x00000010+((reg) * 2))
69#define XGMAC_ADDR_LOW(reg) (0x00000011+((reg) * 2))
70
71#define DMA_BUS_MODE 0x000003c0
72#define DMA_XMT_POLL_DEMAND 0x000003c1
73#define DMA_RCV_POLL_DEMAND 0x000003c2
74#define DMA_RCV_BASE_ADDR 0x000003c3
75#define DMA_TX_BASE_ADDR 0x000003c4
76#define DMA_STATUS 0x000003c5
77#define DMA_CONTROL 0x000003c6
78#define DMA_INTR_ENA 0x000003c7
79#define DMA_MISSED_FRAME_CTR 0x000003c8
80
81#define DMA_RI_WATCHDOG_TIMER 0x000003c9
82#define DMA_AXI_BUS 0x000003ca
83#define DMA_AXI_STATUS 0x000003cb
84#define DMA_CUR_TX_DESC_ADDR 0x000003d2
85#define DMA_CUR_RX_DESC_ADDR 0x000003d3
86#define DMA_CUR_TX_BUF_ADDR 0x000003d4
87#define DMA_CUR_RX_BUF_ADDR 0x000003d5
88#define DMA_HW_FEATURE 0x000003d6
89
90
91#define DMA_STATUS_GMI 0x08000000
92#define DMA_STATUS_GLI 0x04000000
93#define DMA_STATUS_EB_MASK 0x00380000
94#define DMA_STATUS_EB_TX_ABORT 0x00080000
95#define DMA_STATUS_EB_RX_ABORT 0x00100000
96#define DMA_STATUS_TS_MASK 0x00700000
97#define DMA_STATUS_TS_SHIFT 20
98#define DMA_STATUS_RS_MASK 0x000e0000
99#define DMA_STATUS_RS_SHIFT 17
100#define DMA_STATUS_NIS 0x00010000
101#define DMA_STATUS_AIS 0x00008000
102#define DMA_STATUS_ERI 0x00004000
103#define DMA_STATUS_FBI 0x00002000
104#define DMA_STATUS_ETI 0x00000400
105#define DMA_STATUS_RWT 0x00000200
106#define DMA_STATUS_RPS 0x00000100
107#define DMA_STATUS_RU 0x00000080
108#define DMA_STATUS_RI 0x00000040
109#define DMA_STATUS_UNF 0x00000020
110#define DMA_STATUS_OVF 0x00000010
111#define DMA_STATUS_TJT 0x00000008
112#define DMA_STATUS_TU 0x00000004
113#define DMA_STATUS_TPS 0x00000002
114#define DMA_STATUS_TI 0x00000001
115
116
117#define DMA_CONTROL_ST 0x00002000
118#define DMA_CONTROL_SR 0x00000002
119#define DMA_CONTROL_DFF 0x01000000
120
121struct desc {
122 uint32_t ctl_stat;
123 uint16_t buffer1_size;
124 uint16_t buffer2_size;
125 uint32_t buffer1_addr;
126 uint32_t buffer2_addr;
127 uint32_t ext_stat;
128 uint32_t res[3];
129};
130
131#define R_MAX 0x400
132
133typedef struct RxTxStats {
134 uint64_t rx_bytes;
135 uint64_t tx_bytes;
136
137 uint64_t rx;
138 uint64_t rx_bcast;
139 uint64_t rx_mcast;
140} RxTxStats;
141
142#define TYPE_XGMAC "xgmac"
143OBJECT_DECLARE_SIMPLE_TYPE(XgmacState, XGMAC)
144
145struct XgmacState {
146 SysBusDevice parent_obj;
147
148 MemoryRegion iomem;
149 qemu_irq sbd_irq;
150 qemu_irq pmt_irq;
151 qemu_irq mci_irq;
152 NICState *nic;
153 NICConf conf;
154
155 struct RxTxStats stats;
156 uint32_t regs[R_MAX];
157};
158
159static const VMStateDescription vmstate_rxtx_stats = {
160 .name = "xgmac_stats",
161 .version_id = 1,
162 .minimum_version_id = 1,
163 .fields = (VMStateField[]) {
164 VMSTATE_UINT64(rx_bytes, RxTxStats),
165 VMSTATE_UINT64(tx_bytes, RxTxStats),
166 VMSTATE_UINT64(rx, RxTxStats),
167 VMSTATE_UINT64(rx_bcast, RxTxStats),
168 VMSTATE_UINT64(rx_mcast, RxTxStats),
169 VMSTATE_END_OF_LIST()
170 }
171};
172
173static const VMStateDescription vmstate_xgmac = {
174 .name = "xgmac",
175 .version_id = 1,
176 .minimum_version_id = 1,
177 .fields = (VMStateField[]) {
178 VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats),
179 VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX),
180 VMSTATE_END_OF_LIST()
181 }
182};
183
184static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx)
185{
186 uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] :
187 s->regs[DMA_CUR_TX_DESC_ADDR];
188 cpu_physical_memory_read(addr, d, sizeof(*d));
189}
190
191static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx)
192{
193 int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR;
194 uint32_t addr = s->regs[reg];
195
196 if (!rx && (d->ctl_stat & 0x00200000)) {
197 s->regs[reg] = s->regs[DMA_TX_BASE_ADDR];
198 } else if (rx && (d->buffer1_size & 0x8000)) {
199 s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR];
200 } else {
201 s->regs[reg] += sizeof(*d);
202 }
203 cpu_physical_memory_write(addr, d, sizeof(*d));
204}
205
206static void xgmac_enet_send(XgmacState *s)
207{
208 struct desc bd;
209 int frame_size;
210 int len;
211 uint8_t frame[8192];
212 uint8_t *ptr;
213
214 ptr = frame;
215 frame_size = 0;
216 while (1) {
217 xgmac_read_desc(s, &bd, 0);
218 if ((bd.ctl_stat & 0x80000000) == 0) {
219
220 break;
221 }
222 len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff);
223
224
225
226
227
228
229
230
231 if ((bd.buffer1_size & 0xfff) > 2048) {
232 DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
233 "xgmac buffer 1 len on send > 2048 (0x%x)\n",
234 __func__, bd.buffer1_size & 0xfff);
235 break;
236 }
237 if ((bd.buffer2_size & 0xfff) != 0) {
238 DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
239 "xgmac buffer 2 len on send != 0 (0x%x)\n",
240 __func__, bd.buffer2_size & 0xfff);
241 break;
242 }
243 if (frame_size + len >= sizeof(frame)) {
244 DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu "
245 "buffer\n" , __func__, frame_size + len, sizeof(frame));
246 DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n",
247 __func__, bd.buffer1_size, bd.buffer2_size);
248 break;
249 }
250
251 cpu_physical_memory_read(bd.buffer1_addr, ptr, len);
252 ptr += len;
253 frame_size += len;
254 if (bd.ctl_stat & 0x20000000) {
255
256 qemu_send_packet(qemu_get_queue(s->nic), frame, len);
257 ptr = frame;
258 frame_size = 0;
259 s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS;
260 }
261 bd.ctl_stat &= ~0x80000000;
262
263 xgmac_write_desc(s, &bd, 0);
264 }
265}
266
267static void enet_update_irq(XgmacState *s)
268{
269 int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA];
270 qemu_set_irq(s->sbd_irq, !!stat);
271}
272
273static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
274{
275 XgmacState *s = opaque;
276 uint64_t r = 0;
277 addr >>= 2;
278
279 switch (addr) {
280 case XGMAC_VERSION:
281 r = 0x1012;
282 break;
283 default:
284 if (addr < ARRAY_SIZE(s->regs)) {
285 r = s->regs[addr];
286 }
287 break;
288 }
289 return r;
290}
291
292static void enet_write(void *opaque, hwaddr addr,
293 uint64_t value, unsigned size)
294{
295 XgmacState *s = opaque;
296
297 addr >>= 2;
298 switch (addr) {
299 case DMA_BUS_MODE:
300 s->regs[DMA_BUS_MODE] = value & ~0x1;
301 break;
302 case DMA_XMT_POLL_DEMAND:
303 xgmac_enet_send(s);
304 break;
305 case DMA_STATUS:
306 s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value;
307 break;
308 case DMA_RCV_BASE_ADDR:
309 s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value;
310 break;
311 case DMA_TX_BASE_ADDR:
312 s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value;
313 break;
314 default:
315 if (addr < ARRAY_SIZE(s->regs)) {
316 s->regs[addr] = value;
317 }
318 break;
319 }
320 enet_update_irq(s);
321}
322
323static const MemoryRegionOps enet_mem_ops = {
324 .read = enet_read,
325 .write = enet_write,
326 .endianness = DEVICE_LITTLE_ENDIAN,
327};
328
329static int eth_can_rx(XgmacState *s)
330{
331
332 return s->regs[DMA_CONTROL] & DMA_CONTROL_SR;
333}
334
335static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
336{
337 XgmacState *s = qemu_get_nic_opaque(nc);
338 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
339 0xff, 0xff, 0xff};
340 int unicast, broadcast, multicast;
341 struct desc bd;
342 ssize_t ret;
343
344 if (!eth_can_rx(s)) {
345 return -1;
346 }
347 unicast = ~buf[0] & 0x1;
348 broadcast = memcmp(buf, sa_bcast, 6) == 0;
349 multicast = !unicast && !broadcast;
350 if (size < 12) {
351 s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
352 ret = -1;
353 goto out;
354 }
355
356 xgmac_read_desc(s, &bd, 1);
357 if ((bd.ctl_stat & 0x80000000) == 0) {
358 s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS;
359 ret = size;
360 goto out;
361 }
362
363 cpu_physical_memory_write(bd.buffer1_addr, buf, size);
364
365
366 size += 4;
367 bd.ctl_stat = (size << 16) | 0x300;
368 xgmac_write_desc(s, &bd, 1);
369
370 s->stats.rx_bytes += size;
371 s->stats.rx++;
372 if (multicast) {
373 s->stats.rx_mcast++;
374 } else if (broadcast) {
375 s->stats.rx_bcast++;
376 }
377
378 s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
379 ret = size;
380
381out:
382 enet_update_irq(s);
383 return ret;
384}
385
386static NetClientInfo net_xgmac_enet_info = {
387 .type = NET_CLIENT_DRIVER_NIC,
388 .size = sizeof(NICState),
389 .receive = eth_rx,
390};
391
392static void xgmac_enet_realize(DeviceState *dev, Error **errp)
393{
394 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
395 XgmacState *s = XGMAC(dev);
396
397 memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s,
398 "xgmac", 0x1000);
399 sysbus_init_mmio(sbd, &s->iomem);
400 sysbus_init_irq(sbd, &s->sbd_irq);
401 sysbus_init_irq(sbd, &s->pmt_irq);
402 sysbus_init_irq(sbd, &s->mci_irq);
403
404 qemu_macaddr_default_if_unset(&s->conf.macaddr);
405 s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf,
406 object_get_typename(OBJECT(dev)), dev->id, s);
407 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
408
409 s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) |
410 s->conf.macaddr.a[4];
411 s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) |
412 (s->conf.macaddr.a[2] << 16) |
413 (s->conf.macaddr.a[1] << 8) |
414 s->conf.macaddr.a[0];
415}
416
417static Property xgmac_properties[] = {
418 DEFINE_NIC_PROPERTIES(XgmacState, conf),
419 DEFINE_PROP_END_OF_LIST(),
420};
421
422static void xgmac_enet_class_init(ObjectClass *klass, void *data)
423{
424 DeviceClass *dc = DEVICE_CLASS(klass);
425
426 dc->realize = xgmac_enet_realize;
427 dc->vmsd = &vmstate_xgmac;
428 device_class_set_props(dc, xgmac_properties);
429}
430
431static const TypeInfo xgmac_enet_info = {
432 .name = TYPE_XGMAC,
433 .parent = TYPE_SYS_BUS_DEVICE,
434 .instance_size = sizeof(XgmacState),
435 .class_init = xgmac_enet_class_init,
436};
437
438static void xgmac_enet_register_types(void)
439{
440 type_register_static(&xgmac_enet_info);
441}
442
443type_init(xgmac_enet_register_types)
444