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26#include "qemu/osdep.h"
27#include "qemu-common.h"
28#include "qemu/datadir.h"
29#include "qemu/units.h"
30#include "qemu/log.h"
31#include "qapi/error.h"
32#include "hw/pci/pci.h"
33#include "hw/pci/pci_bus.h"
34#include "hw/pci/pci_host.h"
35#include "hw/qdev-properties.h"
36#include "migration/vmstate.h"
37#include "hw/intc/i8259.h"
38#include "hw/irq.h"
39#include "hw/loader.h"
40#include "hw/or-irq.h"
41#include "exec/address-spaces.h"
42#include "elf.h"
43#include "qom/object.h"
44
45#define TYPE_RAVEN_PCI_DEVICE "raven"
46#define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
47
48OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE)
49
50struct RavenPCIState {
51 PCIDevice dev;
52
53 uint32_t elf_machine;
54 char *bios_name;
55 MemoryRegion bios;
56};
57
58typedef struct PRePPCIState PREPPCIState;
59DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
60 TYPE_RAVEN_PCI_HOST_BRIDGE)
61
62struct PRePPCIState {
63 PCIHostState parent_obj;
64
65 qemu_or_irq *or_irq;
66 qemu_irq pci_irqs[PCI_NUM_PINS];
67 PCIBus pci_bus;
68 AddressSpace pci_io_as;
69 MemoryRegion pci_io;
70 MemoryRegion pci_io_non_contiguous;
71 MemoryRegion pci_memory;
72 MemoryRegion pci_intack;
73 MemoryRegion bm;
74 MemoryRegion bm_ram_alias;
75 MemoryRegion bm_pci_memory_alias;
76 AddressSpace bm_as;
77 RavenPCIState pci_dev;
78
79 int contiguous_map;
80 bool is_legacy_prep;
81};
82
83#define BIOS_SIZE (1 * MiB)
84
85static inline uint32_t raven_pci_io_config(hwaddr addr)
86{
87 int i;
88
89 for (i = 0; i < 11; i++) {
90 if ((addr & (1 << (11 + i))) != 0) {
91 break;
92 }
93 }
94 return (addr & 0x7ff) | (i << 11);
95}
96
97static void raven_pci_io_write(void *opaque, hwaddr addr,
98 uint64_t val, unsigned int size)
99{
100 PREPPCIState *s = opaque;
101 PCIHostState *phb = PCI_HOST_BRIDGE(s);
102 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
103}
104
105static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
106 unsigned int size)
107{
108 PREPPCIState *s = opaque;
109 PCIHostState *phb = PCI_HOST_BRIDGE(s);
110 return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
111}
112
113static const MemoryRegionOps raven_pci_io_ops = {
114 .read = raven_pci_io_read,
115 .write = raven_pci_io_write,
116 .endianness = DEVICE_LITTLE_ENDIAN,
117};
118
119static uint64_t raven_intack_read(void *opaque, hwaddr addr,
120 unsigned int size)
121{
122 return pic_read_irq(isa_pic);
123}
124
125static void raven_intack_write(void *opaque, hwaddr addr,
126 uint64_t data, unsigned size)
127{
128 qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
129}
130
131static const MemoryRegionOps raven_intack_ops = {
132 .read = raven_intack_read,
133 .write = raven_intack_write,
134 .valid = {
135 .max_access_size = 1,
136 },
137};
138
139static inline hwaddr raven_io_address(PREPPCIState *s,
140 hwaddr addr)
141{
142 if (s->contiguous_map == 0) {
143
144 addr &= 0xFFFF;
145 } else {
146
147 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
148 }
149
150
151
152 return addr;
153}
154
155static uint64_t raven_io_read(void *opaque, hwaddr addr,
156 unsigned int size)
157{
158 PREPPCIState *s = opaque;
159 uint8_t buf[4];
160
161 addr = raven_io_address(s, addr);
162 address_space_read(&s->pci_io_as, addr + 0x80000000,
163 MEMTXATTRS_UNSPECIFIED, buf, size);
164
165 if (size == 1) {
166 return buf[0];
167 } else if (size == 2) {
168 return lduw_le_p(buf);
169 } else if (size == 4) {
170 return ldl_le_p(buf);
171 } else {
172 g_assert_not_reached();
173 }
174}
175
176static void raven_io_write(void *opaque, hwaddr addr,
177 uint64_t val, unsigned int size)
178{
179 PREPPCIState *s = opaque;
180 uint8_t buf[4];
181
182 addr = raven_io_address(s, addr);
183
184 if (size == 1) {
185 buf[0] = val;
186 } else if (size == 2) {
187 stw_le_p(buf, val);
188 } else if (size == 4) {
189 stl_le_p(buf, val);
190 } else {
191 g_assert_not_reached();
192 }
193
194 address_space_write(&s->pci_io_as, addr + 0x80000000,
195 MEMTXATTRS_UNSPECIFIED, buf, size);
196}
197
198static const MemoryRegionOps raven_io_ops = {
199 .read = raven_io_read,
200 .write = raven_io_write,
201 .endianness = DEVICE_LITTLE_ENDIAN,
202 .impl.max_access_size = 4,
203 .valid.unaligned = true,
204};
205
206static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
207{
208 return (irq_num + (pci_dev->devfn >> 3)) & 1;
209}
210
211static void raven_set_irq(void *opaque, int irq_num, int level)
212{
213 PREPPCIState *s = opaque;
214
215 qemu_set_irq(s->pci_irqs[irq_num], level);
216}
217
218static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
219 int devfn)
220{
221 PREPPCIState *s = opaque;
222
223 return &s->bm_as;
224}
225
226static void raven_change_gpio(void *opaque, int n, int level)
227{
228 PREPPCIState *s = opaque;
229
230 s->contiguous_map = level;
231}
232
233static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
234{
235 SysBusDevice *dev = SYS_BUS_DEVICE(d);
236 PCIHostState *h = PCI_HOST_BRIDGE(dev);
237 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
238 MemoryRegion *address_space_mem = get_system_memory();
239 int i;
240
241 if (s->is_legacy_prep) {
242 for (i = 0; i < PCI_NUM_PINS; i++) {
243 sysbus_init_irq(dev, &s->pci_irqs[i]);
244 }
245 } else {
246
247
248 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
249 object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS,
250 &error_fatal);
251 qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
252 sysbus_init_irq(dev, &s->or_irq->out_irq);
253
254 for (i = 0; i < PCI_NUM_PINS; i++) {
255 s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
256 }
257 }
258
259 qdev_init_gpio_in(d, raven_change_gpio, 1);
260
261 pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
262
263 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
264 "pci-conf-idx", 4);
265 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
266
267 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
268 "pci-conf-data", 4);
269 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
270
271 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
272 "pciio", 0x00400000);
273 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
274
275 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
276 "pci-intack", 1);
277 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
278
279
280 qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp);
281}
282
283static void raven_pcihost_initfn(Object *obj)
284{
285 PCIHostState *h = PCI_HOST_BRIDGE(obj);
286 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
287 MemoryRegion *address_space_mem = get_system_memory();
288 DeviceState *pci_dev;
289
290 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
291 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
292 "pci-io-non-contiguous", 0x00800000);
293 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
294 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
295
296
297 memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
298 memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
299 &s->pci_io_non_contiguous, 1);
300 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
301 pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
302 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
303
304
305 memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
306 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
307 &s->pci_memory, 0,
308 memory_region_size(&s->pci_memory));
309 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
310 get_system_memory(), 0, 0x80000000);
311 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
312 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
313 address_space_init(&s->bm_as, &s->bm, "raven-bm");
314 pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
315
316 h->bus = &s->pci_bus;
317
318 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
319 pci_dev = DEVICE(&s->pci_dev);
320 object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0),
321 NULL);
322 qdev_prop_set_bit(pci_dev, "multifunction", false);
323}
324
325static void raven_realize(PCIDevice *d, Error **errp)
326{
327 RavenPCIState *s = RAVEN_PCI_DEVICE(d);
328 char *filename;
329 int bios_size = -1;
330
331 d->config[0x0C] = 0x08;
332 d->config[0x0D] = 0x10;
333 d->config[0x34] = 0x00;
334
335 memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
336 &error_fatal);
337 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
338 &s->bios);
339 if (s->bios_name) {
340 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
341 if (filename) {
342 if (s->elf_machine != EM_NONE) {
343 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
344 NULL, NULL, NULL, 1, s->elf_machine,
345 0, 0);
346 }
347 if (bios_size < 0) {
348 bios_size = get_image_size(filename);
349 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
350 hwaddr bios_addr;
351 bios_size = (bios_size + 0xfff) & ~0xfff;
352 bios_addr = (uint32_t)(-BIOS_SIZE);
353 bios_size = load_image_targphys(filename, bios_addr,
354 bios_size);
355 }
356 }
357 }
358 g_free(filename);
359 if (bios_size < 0 || bios_size > BIOS_SIZE) {
360 memory_region_del_subregion(get_system_memory(), &s->bios);
361 error_setg(errp, "Could not load bios image '%s'", s->bios_name);
362 return;
363 }
364 }
365
366 vmstate_register_ram_global(&s->bios);
367}
368
369static const VMStateDescription vmstate_raven = {
370 .name = "raven",
371 .version_id = 0,
372 .minimum_version_id = 0,
373 .fields = (VMStateField[]) {
374 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
375 VMSTATE_END_OF_LIST()
376 },
377};
378
379static void raven_class_init(ObjectClass *klass, void *data)
380{
381 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
382 DeviceClass *dc = DEVICE_CLASS(klass);
383
384 k->realize = raven_realize;
385 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
386 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
387 k->revision = 0x00;
388 k->class_id = PCI_CLASS_BRIDGE_HOST;
389 dc->desc = "PReP Host Bridge - Motorola Raven";
390 dc->vmsd = &vmstate_raven;
391
392
393
394
395 dc->user_creatable = false;
396}
397
398static const TypeInfo raven_info = {
399 .name = TYPE_RAVEN_PCI_DEVICE,
400 .parent = TYPE_PCI_DEVICE,
401 .instance_size = sizeof(RavenPCIState),
402 .class_init = raven_class_init,
403 .interfaces = (InterfaceInfo[]) {
404 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
405 { },
406 },
407};
408
409static Property raven_pcihost_properties[] = {
410 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
411 EM_NONE),
412 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
413
414 DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
415 false),
416 DEFINE_PROP_END_OF_LIST()
417};
418
419static void raven_pcihost_class_init(ObjectClass *klass, void *data)
420{
421 DeviceClass *dc = DEVICE_CLASS(klass);
422
423 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
424 dc->realize = raven_pcihost_realizefn;
425 device_class_set_props(dc, raven_pcihost_properties);
426 dc->fw_name = "pci";
427}
428
429static const TypeInfo raven_pcihost_info = {
430 .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
431 .parent = TYPE_PCI_HOST_BRIDGE,
432 .instance_size = sizeof(PREPPCIState),
433 .instance_init = raven_pcihost_initfn,
434 .class_init = raven_pcihost_class_init,
435};
436
437static void raven_register_types(void)
438{
439 type_register_static(&raven_pcihost_info);
440 type_register_static(&raven_info);
441}
442
443type_init(raven_register_types)
444
