LXR qemu/include/hw/i386/x86-iommu.h

   1/*
   2 * Common IOMMU interface for X86 platform
   3 *
   4 * Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15
  16 * You should have received a copy of the GNU General Public License along
  17 * with this program; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef HW_I386_X86_IOMMU_H
  21#define HW_I386_X86_IOMMU_H
  22
  23#include "hw/sysbus.h"
  24#include "hw/pci/pci.h"
  25#include "hw/pci/msi.h"
  26#include "qom/object.h"
  27
  28#define  TYPE_X86_IOMMU_DEVICE  ("x86-iommu")
  29OBJECT_DECLARE_TYPE(X86IOMMUState, X86IOMMUClass, X86_IOMMU_DEVICE)
  30
  31#define X86_IOMMU_SID_INVALID             (0xffff)
  32
  33typedef struct X86IOMMUIrq X86IOMMUIrq;
  34typedef struct X86IOMMU_MSIMessage X86IOMMU_MSIMessage;
  35
  36typedef enum IommuType {
  37    TYPE_INTEL,
  38    TYPE_AMD,
  39    TYPE_NONE
  40} IommuType;
  41
  42struct X86IOMMUClass {
  43    SysBusDeviceClass parent;
  44    /* Intel/AMD specific realize() hook */
  45    DeviceRealize realize;
  46    /* MSI-based interrupt remapping */
  47    int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src,
  48                     MSIMessage *dst, uint16_t sid);
  49};
  50
  51/**
  52 * iec_notify_fn - IEC (Interrupt Entry Cache) notifier hook,
  53 *                 triggered when IR invalidation happens.
  54 * @private: private data
  55 * @global: whether this is a global IEC invalidation
  56 * @index: IRTE index to invalidate (start from)
  57 * @mask: invalidation mask
  58 */
  59typedef void (*iec_notify_fn)(void *private, bool global,
  60                              uint32_t index, uint32_t mask);
  61
  62struct IEC_Notifier {
  63    iec_notify_fn iec_notify;
  64    void *private;
  65    QLIST_ENTRY(IEC_Notifier) list;
  66};
  67typedef struct IEC_Notifier IEC_Notifier;
  68
  69struct X86IOMMUState {
  70    SysBusDevice busdev;
  71    OnOffAuto intr_supported;   /* Whether vIOMMU supports IR */
  72    bool dt_supported;          /* Whether vIOMMU supports DT */
  73    bool pt_supported;          /* Whether vIOMMU supports pass-through */
  74    IommuType type;             /* IOMMU type - AMD/Intel     */
  75    QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */
  76};
  77
  78bool x86_iommu_ir_supported(X86IOMMUState *s);
  79
  80/* Generic IRQ entry information when interrupt remapping is enabled */
  81struct X86IOMMUIrq {
  82    /* Used by both IOAPIC/MSI interrupt remapping */
  83    uint8_t trigger_mode;
  84    uint8_t vector;
  85    uint8_t delivery_mode;
  86    uint32_t dest;
  87    uint8_t dest_mode;
  88
  89    /* only used by MSI interrupt remapping */
  90    uint8_t redir_hint;
  91    uint8_t msi_addr_last_bits;
  92};
  93
  94struct X86IOMMU_MSIMessage {
  95    union {
  96        struct {
  97#ifdef HOST_WORDS_BIGENDIAN
  98            uint32_t __addr_head:12; /* 0xfee */
  99            uint32_t dest:8;
 100            uint32_t __reserved:8;
 101            uint32_t redir_hint:1;
 102            uint32_t dest_mode:1;
 103            uint32_t __not_used:2;
 104#else
 105            uint32_t __not_used:2;
 106            uint32_t dest_mode:1;
 107            uint32_t redir_hint:1;
 108            uint32_t __reserved:8;
 109            uint32_t dest:8;
 110            uint32_t __addr_head:12; /* 0xfee */
 111#endif
 112            uint32_t __addr_hi;
 113        } QEMU_PACKED;
 114        uint64_t msi_addr;
 115    };
 116    union {
 117        struct {
 118#ifdef HOST_WORDS_BIGENDIAN
 119            uint16_t trigger_mode:1;
 120            uint16_t level:1;
 121            uint16_t __resved:3;
 122            uint16_t delivery_mode:3;
 123            uint16_t vector:8;
 124#else
 125            uint16_t vector:8;
 126            uint16_t delivery_mode:3;
 127            uint16_t __resved:3;
 128            uint16_t level:1;
 129            uint16_t trigger_mode:1;
 130#endif
 131            uint16_t __resved1;
 132        } QEMU_PACKED;
 133        uint32_t msi_data;
 134    };
 135};
 136
 137/**
 138 * x86_iommu_get_default - get default IOMMU device
 139 * @return: pointer to default IOMMU device
 140 */
 141X86IOMMUState *x86_iommu_get_default(void);
 142
 143/*
 144 * x86_iommu_get_type - get IOMMU type
 145 */
 146IommuType x86_iommu_get_type(void);
 147
 148/**
 149 * x86_iommu_iec_register_notifier - register IEC (Interrupt Entry
 150 *                                   Cache) notifiers
 151 * @iommu: IOMMU device to register
 152 * @fn: IEC notifier hook function
 153 * @data: notifier private data
 154 */
 155void x86_iommu_iec_register_notifier(X86IOMMUState *iommu,
 156                                     iec_notify_fn fn, void *data);
 157
 158/**
 159 * x86_iommu_iec_notify_all - Notify IEC invalidations
 160 * @iommu: IOMMU device that sends the notification
 161 * @global: whether this is a global invalidation. If true, @index
 162 *          and @mask are undefined.
 163 * @index: starting index of interrupt entry to invalidate
 164 * @mask: index mask for the invalidation
 165 */
 166void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
 167                              uint32_t index, uint32_t mask);
 168
 169/**
 170 * x86_iommu_irq_to_msi_message - Populate one MSIMessage from X86IOMMUIrq
 171 * @X86IOMMUIrq: The IRQ information
 172 * @out: Output MSI message
 173 */
 174void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *out);
 175#endif
 176