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10#ifndef PCI_HOST_PNV_PHB3_H
11#define PCI_HOST_PNV_PHB3_H
12
13#include "hw/pci/pcie_host.h"
14#include "hw/pci/pcie_port.h"
15#include "hw/ppc/xics.h"
16#include "qom/object.h"
17
18typedef struct PnvPHB3 PnvPHB3;
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22
23#define TYPE_PHB3_MSI "phb3-msi"
24typedef struct Phb3MsiState Phb3MsiState;
25DECLARE_INSTANCE_CHECKER(Phb3MsiState, PHB3_MSI,
26 TYPE_PHB3_MSI)
27
28#define PHB3_MAX_MSI 2048
29
30struct Phb3MsiState {
31 ICSState ics;
32 qemu_irq *qirqs;
33
34 PnvPHB3 *phb;
35 uint64_t rba[PHB3_MAX_MSI / 64];
36 uint32_t rba_sum;
37};
38
39void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
40 uint32_t count);
41void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
42 int32_t dev_pe);
43void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val);
44void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, Monitor *mon);
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57
58typedef struct PnvPhb3DMASpace {
59 PCIBus *bus;
60 uint8_t devfn;
61 int pe_num;
62#define PHB_INVALID_PE (-1)
63 PnvPHB3 *phb;
64 AddressSpace dma_as;
65 IOMMUMemoryRegion dma_mr;
66 MemoryRegion msi32_mr;
67 MemoryRegion msi64_mr;
68 QLIST_ENTRY(PnvPhb3DMASpace) list;
69} PnvPhb3DMASpace;
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72
73
74#define TYPE_PNV_PBCQ "pnv-pbcq"
75OBJECT_DECLARE_SIMPLE_TYPE(PnvPBCQState, PNV_PBCQ)
76
77struct PnvPBCQState {
78 DeviceState parent;
79
80 uint32_t nest_xbase;
81 uint32_t spci_xbase;
82 uint32_t pci_xbase;
83#define PBCQ_NEST_REGS_COUNT 0x46
84#define PBCQ_PCI_REGS_COUNT 0x15
85#define PBCQ_SPCI_REGS_COUNT 0x5
86
87 uint64_t nest_regs[PBCQ_NEST_REGS_COUNT];
88 uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT];
89 uint64_t pci_regs[PBCQ_PCI_REGS_COUNT];
90 MemoryRegion mmbar0;
91 MemoryRegion mmbar1;
92 MemoryRegion phbbar;
93 uint64_t mmio0_base;
94 uint64_t mmio0_size;
95 uint64_t mmio1_base;
96 uint64_t mmio1_size;
97 PnvPHB3 *phb;
98
99 MemoryRegion xscom_nest_regs;
100 MemoryRegion xscom_pci_regs;
101 MemoryRegion xscom_spci_regs;
102};
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106
107#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root-bus"
108
109#define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port"
110
111typedef struct PnvPHB3RootPort {
112 PCIESlot parent_obj;
113} PnvPHB3RootPort;
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117
118#define TYPE_PNV_PHB3 "pnv-phb3"
119OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3)
120
121#define PNV_PHB3_NUM_M64 16
122#define PNV_PHB3_NUM_REGS (0x1000 >> 3)
123#define PNV_PHB3_NUM_LSI 8
124#define PNV_PHB3_NUM_PE 256
125
126#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
127
128struct PnvPHB3 {
129 PCIExpressHost parent_obj;
130
131 uint32_t chip_id;
132 uint32_t phb_id;
133 char bus_path[8];
134
135 uint64_t regs[PNV_PHB3_NUM_REGS];
136 MemoryRegion mr_regs;
137
138 MemoryRegion mr_m32;
139 MemoryRegion mr_m64[PNV_PHB3_NUM_M64];
140 MemoryRegion pci_mmio;
141 MemoryRegion pci_io;
142
143 uint64_t ioda_LIST[8];
144 uint64_t ioda_LXIVT[8];
145 uint64_t ioda_TVT[512];
146 uint64_t ioda_M64BT[16];
147 uint64_t ioda_MDT[256];
148 uint64_t ioda_PEEV[4];
149
150 uint32_t total_irq;
151 ICSState lsis;
152 qemu_irq *qirqs;
153 Phb3MsiState msis;
154
155 PnvPBCQState pbcq;
156
157 PnvPHB3RootPort root;
158
159 QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces;
160};
161
162uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
163void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
164void pnv_phb3_update_regions(PnvPHB3 *phb);
165void pnv_phb3_remap_irqs(PnvPHB3 *phb);
166
167#endif
168