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31#include "qemu/osdep.h"
32#include "qemu-common.h"
33#include "qemu/datadir.h"
34#include "qemu/units.h"
35#include "qemu/option.h"
36#include "monitor/qdev.h"
37#include "qapi/error.h"
38#include "hw/sysbus.h"
39#include "hw/arm/boot.h"
40#include "hw/arm/primecell.h"
41#include "hw/arm/virt.h"
42#include "hw/block/flash.h"
43#include "hw/vfio/vfio-calxeda-xgmac.h"
44#include "hw/vfio/vfio-amd-xgbe.h"
45#include "hw/display/ramfb.h"
46#include "net/net.h"
47#include "sysemu/device_tree.h"
48#include "sysemu/numa.h"
49#include "sysemu/runstate.h"
50#include "sysemu/tpm.h"
51#include "sysemu/kvm.h"
52#include "hw/loader.h"
53#include "qapi/error.h"
54#include "qemu/bitops.h"
55#include "qemu/error-report.h"
56#include "qemu/module.h"
57#include "hw/pci-host/gpex.h"
58#include "hw/virtio/virtio-pci.h"
59#include "hw/arm/sysbus-fdt.h"
60#include "hw/platform-bus.h"
61#include "hw/qdev-properties.h"
62#include "hw/arm/fdt.h"
63#include "hw/intc/arm_gic.h"
64#include "hw/intc/arm_gicv3_common.h"
65#include "hw/irq.h"
66#include "kvm_arm.h"
67#include "hw/firmware/smbios.h"
68#include "qapi/visitor.h"
69#include "qapi/qapi-visit-common.h"
70#include "standard-headers/linux/input.h"
71#include "hw/arm/smmuv3.h"
72#include "hw/acpi/acpi.h"
73#include "target/arm/internals.h"
74#include "hw/mem/pc-dimm.h"
75#include "hw/mem/nvdimm.h"
76#include "hw/acpi/generic_event_device.h"
77#include "hw/virtio/virtio-iommu.h"
78#include "hw/char/pl011.h"
79#include "qemu/guest-random.h"
80
81#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
82 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
83 void *data) \
84 { \
85 MachineClass *mc = MACHINE_CLASS(oc); \
86 virt_machine_##major##_##minor##_options(mc); \
87 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
88 if (latest) { \
89 mc->alias = "virt"; \
90 } \
91 } \
92 static const TypeInfo machvirt_##major##_##minor##_info = { \
93 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
94 .parent = TYPE_VIRT_MACHINE, \
95 .class_init = virt_##major##_##minor##_class_init, \
96 }; \
97 static void machvirt_machine_##major##_##minor##_init(void) \
98 { \
99 type_register_static(&machvirt_##major##_##minor##_info); \
100 } \
101 type_init(machvirt_machine_##major##_##minor##_init);
102
103#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
104 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
105#define DEFINE_VIRT_MACHINE(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
107
108
109
110#define NUM_IRQS 256
111
112#define PLATFORM_BUS_NUM_IRQS 64
113
114
115#define LEGACY_RAMLIMIT_GB 255
116#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
117
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129
130static const MemMapEntry base_memmap[] = {
131
132 [VIRT_FLASH] = { 0, 0x08000000 },
133 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
134
135 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
136 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
137 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
138 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
139 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
140
141 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
142
143 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
144 [VIRT_UART] = { 0x09000000, 0x00001000 },
145 [VIRT_RTC] = { 0x09010000, 0x00001000 },
146 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
147 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
148 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
149 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
150 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
151 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
152 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
153 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
154 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
155 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
156
157 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
158 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
159 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
160 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
161 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
162
163 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
164};
165
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174
175
176static MemMapEntry extended_memmap[] = {
177
178 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
179 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
180
181 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
182};
183
184static const int a15irqmap[] = {
185 [VIRT_UART] = 1,
186 [VIRT_RTC] = 2,
187 [VIRT_PCIE] = 3,
188 [VIRT_GPIO] = 7,
189 [VIRT_SECURE_UART] = 8,
190 [VIRT_ACPI_GED] = 9,
191 [VIRT_MMIO] = 16,
192 [VIRT_GIC_V2M] = 48,
193 [VIRT_SMMU] = 74,
194 [VIRT_PLATFORM_BUS] = 112,
195};
196
197static const char *valid_cpus[] = {
198 ARM_CPU_TYPE_NAME("cortex-a7"),
199 ARM_CPU_TYPE_NAME("cortex-a15"),
200 ARM_CPU_TYPE_NAME("cortex-a53"),
201 ARM_CPU_TYPE_NAME("cortex-a57"),
202 ARM_CPU_TYPE_NAME("cortex-a72"),
203 ARM_CPU_TYPE_NAME("host"),
204 ARM_CPU_TYPE_NAME("max"),
205};
206
207static bool cpu_type_valid(const char *cpu)
208{
209 int i;
210
211 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
212 if (strcmp(cpu, valid_cpus[i]) == 0) {
213 return true;
214 }
215 }
216 return false;
217}
218
219static void create_kaslr_seed(MachineState *ms, const char *node)
220{
221 uint64_t seed;
222
223 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
224 return;
225 }
226 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed);
227}
228
229static void create_fdt(VirtMachineState *vms)
230{
231 MachineState *ms = MACHINE(vms);
232 int nb_numa_nodes = ms->numa_state->num_nodes;
233 void *fdt = create_device_tree(&vms->fdt_size);
234
235 if (!fdt) {
236 error_report("create_device_tree() failed");
237 exit(1);
238 }
239
240 ms->fdt = fdt;
241
242
243 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
244 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
245 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
246
247
248 qemu_fdt_add_subnode(fdt, "/chosen");
249 create_kaslr_seed(ms, "/chosen");
250
251 if (vms->secure) {
252 qemu_fdt_add_subnode(fdt, "/secure-chosen");
253 create_kaslr_seed(ms, "/secure-chosen");
254 }
255
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260
261 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
262 qemu_fdt_add_subnode(fdt, "/apb-pclk");
263 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
264 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
265 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
266 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
267 "clk24mhz");
268 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
269
270 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
271 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
272 uint32_t *matrix = g_malloc0(size);
273 int idx, i, j;
274
275 for (i = 0; i < nb_numa_nodes; i++) {
276 for (j = 0; j < nb_numa_nodes; j++) {
277 idx = (i * nb_numa_nodes + j) * 3;
278 matrix[idx + 0] = cpu_to_be32(i);
279 matrix[idx + 1] = cpu_to_be32(j);
280 matrix[idx + 2] =
281 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
282 }
283 }
284
285 qemu_fdt_add_subnode(fdt, "/distance-map");
286 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
287 "numa-distance-map-v1");
288 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
289 matrix, size);
290 g_free(matrix);
291 }
292}
293
294static void fdt_add_timer_nodes(const VirtMachineState *vms)
295{
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314 ARMCPU *armcpu;
315 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
316 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
317 MachineState *ms = MACHINE(vms);
318
319 if (vmc->claim_edge_triggered_timers) {
320 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
321 }
322
323 if (vms->gic_version == VIRT_GIC_VERSION_2) {
324 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
325 GIC_FDT_IRQ_PPI_CPU_WIDTH,
326 (1 << MACHINE(vms)->smp.cpus) - 1);
327 }
328
329 qemu_fdt_add_subnode(ms->fdt, "/timer");
330
331 armcpu = ARM_CPU(qemu_get_cpu(0));
332 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
333 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
334 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
335 compat, sizeof(compat));
336 } else {
337 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
338 "arm,armv7-timer");
339 }
340 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
341 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
342 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
343 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
344 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
345 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
346}
347
348static void fdt_add_cpu_nodes(const VirtMachineState *vms)
349{
350 int cpu;
351 int addr_cells = 1;
352 const MachineState *ms = MACHINE(vms);
353 int smp_cpus = ms->smp.cpus;
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366
367
368 for (cpu = 0; cpu < smp_cpus; cpu++) {
369 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
370
371 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
372 addr_cells = 2;
373 break;
374 }
375 }
376
377 qemu_fdt_add_subnode(ms->fdt, "/cpus");
378 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
379 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
380
381 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
382 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
383 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
384 CPUState *cs = CPU(armcpu);
385
386 qemu_fdt_add_subnode(ms->fdt, nodename);
387 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
388 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
389 armcpu->dtb_compatible);
390
391 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
392 qemu_fdt_setprop_string(ms->fdt, nodename,
393 "enable-method", "psci");
394 }
395
396 if (addr_cells == 2) {
397 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
398 armcpu->mp_affinity);
399 } else {
400 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
401 armcpu->mp_affinity);
402 }
403
404 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
405 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
406 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
407 }
408
409 g_free(nodename);
410 }
411}
412
413static void fdt_add_its_gic_node(VirtMachineState *vms)
414{
415 char *nodename;
416 MachineState *ms = MACHINE(vms);
417
418 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
419 nodename = g_strdup_printf("/intc/its@%" PRIx64,
420 vms->memmap[VIRT_GIC_ITS].base);
421 qemu_fdt_add_subnode(ms->fdt, nodename);
422 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
423 "arm,gic-v3-its");
424 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
425 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
426 2, vms->memmap[VIRT_GIC_ITS].base,
427 2, vms->memmap[VIRT_GIC_ITS].size);
428 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
429 g_free(nodename);
430}
431
432static void fdt_add_v2m_gic_node(VirtMachineState *vms)
433{
434 MachineState *ms = MACHINE(vms);
435 char *nodename;
436
437 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
438 vms->memmap[VIRT_GIC_V2M].base);
439 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
440 qemu_fdt_add_subnode(ms->fdt, nodename);
441 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
442 "arm,gic-v2m-frame");
443 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
444 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
445 2, vms->memmap[VIRT_GIC_V2M].base,
446 2, vms->memmap[VIRT_GIC_V2M].size);
447 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
448 g_free(nodename);
449}
450
451static void fdt_add_gic_node(VirtMachineState *vms)
452{
453 MachineState *ms = MACHINE(vms);
454 char *nodename;
455
456 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
457 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
458
459 nodename = g_strdup_printf("/intc@%" PRIx64,
460 vms->memmap[VIRT_GIC_DIST].base);
461 qemu_fdt_add_subnode(ms->fdt, nodename);
462 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
463 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
464 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
465 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
466 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
467 if (vms->gic_version == VIRT_GIC_VERSION_3) {
468 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
469
470 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
471 "arm,gic-v3");
472
473 qemu_fdt_setprop_cell(ms->fdt, nodename,
474 "#redistributor-regions", nb_redist_regions);
475
476 if (nb_redist_regions == 1) {
477 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
478 2, vms->memmap[VIRT_GIC_DIST].base,
479 2, vms->memmap[VIRT_GIC_DIST].size,
480 2, vms->memmap[VIRT_GIC_REDIST].base,
481 2, vms->memmap[VIRT_GIC_REDIST].size);
482 } else {
483 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
484 2, vms->memmap[VIRT_GIC_DIST].base,
485 2, vms->memmap[VIRT_GIC_DIST].size,
486 2, vms->memmap[VIRT_GIC_REDIST].base,
487 2, vms->memmap[VIRT_GIC_REDIST].size,
488 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
489 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
490 }
491
492 if (vms->virt) {
493 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
494 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
495 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
496 }
497 } else {
498
499 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
500 "arm,cortex-a15-gic");
501 if (!vms->virt) {
502 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
503 2, vms->memmap[VIRT_GIC_DIST].base,
504 2, vms->memmap[VIRT_GIC_DIST].size,
505 2, vms->memmap[VIRT_GIC_CPU].base,
506 2, vms->memmap[VIRT_GIC_CPU].size);
507 } else {
508 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
509 2, vms->memmap[VIRT_GIC_DIST].base,
510 2, vms->memmap[VIRT_GIC_DIST].size,
511 2, vms->memmap[VIRT_GIC_CPU].base,
512 2, vms->memmap[VIRT_GIC_CPU].size,
513 2, vms->memmap[VIRT_GIC_HYP].base,
514 2, vms->memmap[VIRT_GIC_HYP].size,
515 2, vms->memmap[VIRT_GIC_VCPU].base,
516 2, vms->memmap[VIRT_GIC_VCPU].size);
517 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
518 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
519 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
520 }
521 }
522
523 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
524 g_free(nodename);
525}
526
527static void fdt_add_pmu_nodes(const VirtMachineState *vms)
528{
529 ARMCPU *armcpu = ARM_CPU(first_cpu);
530 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
531 MachineState *ms = MACHINE(vms);
532
533 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
534 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
535 return;
536 }
537
538 if (vms->gic_version == VIRT_GIC_VERSION_2) {
539 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
540 GIC_FDT_IRQ_PPI_CPU_WIDTH,
541 (1 << MACHINE(vms)->smp.cpus) - 1);
542 }
543
544 qemu_fdt_add_subnode(ms->fdt, "/pmu");
545 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
546 const char compat[] = "arm,armv8-pmuv3";
547 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
548 compat, sizeof(compat));
549 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
550 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
551 }
552}
553
554static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
555{
556 DeviceState *dev;
557 MachineState *ms = MACHINE(vms);
558 int irq = vms->irqmap[VIRT_ACPI_GED];
559 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
560
561 if (ms->ram_slots) {
562 event |= ACPI_GED_MEM_HOTPLUG_EVT;
563 }
564
565 if (ms->nvdimms_state->is_enabled) {
566 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
567 }
568
569 dev = qdev_new(TYPE_ACPI_GED);
570 qdev_prop_set_uint32(dev, "ged-event", event);
571
572 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
573 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
574 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
575
576 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
577
578 return dev;
579}
580
581static void create_its(VirtMachineState *vms)
582{
583 const char *itsclass = its_class_name();
584 DeviceState *dev;
585
586 if (!itsclass) {
587
588 return;
589 }
590
591 dev = qdev_new(itsclass);
592
593 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
594 &error_abort);
595 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
596 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
597
598 fdt_add_its_gic_node(vms);
599 vms->msi_controller = VIRT_MSI_CTRL_ITS;
600}
601
602static void create_v2m(VirtMachineState *vms)
603{
604 int i;
605 int irq = vms->irqmap[VIRT_GIC_V2M];
606 DeviceState *dev;
607
608 dev = qdev_new("arm-gicv2m");
609 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
610 qdev_prop_set_uint32(dev, "base-spi", irq);
611 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
612 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
613
614 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
615 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
616 qdev_get_gpio_in(vms->gic, irq + i));
617 }
618
619 fdt_add_v2m_gic_node(vms);
620 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
621}
622
623static void create_gic(VirtMachineState *vms)
624{
625 MachineState *ms = MACHINE(vms);
626
627 SysBusDevice *gicbusdev;
628 const char *gictype;
629 int type = vms->gic_version, i;
630 unsigned int smp_cpus = ms->smp.cpus;
631 uint32_t nb_redist_regions = 0;
632
633 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
634
635 vms->gic = qdev_new(gictype);
636 qdev_prop_set_uint32(vms->gic, "revision", type);
637 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
638
639
640
641 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
642 if (!kvm_irqchip_in_kernel()) {
643 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
644 }
645
646 if (type == 3) {
647 uint32_t redist0_capacity =
648 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
649 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
650
651 nb_redist_regions = virt_gicv3_redist_region_count(vms);
652
653 qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
654 nb_redist_regions);
655 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
656
657 if (nb_redist_regions == 2) {
658 uint32_t redist1_capacity =
659 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
660
661 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
662 MIN(smp_cpus - redist0_count, redist1_capacity));
663 }
664 } else {
665 if (!kvm_irqchip_in_kernel()) {
666 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
667 vms->virt);
668 }
669 }
670 gicbusdev = SYS_BUS_DEVICE(vms->gic);
671 sysbus_realize_and_unref(gicbusdev, &error_fatal);
672 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
673 if (type == 3) {
674 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
675 if (nb_redist_regions == 2) {
676 sysbus_mmio_map(gicbusdev, 2,
677 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
678 }
679 } else {
680 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
681 if (vms->virt) {
682 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
683 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
684 }
685 }
686
687
688
689
690
691 for (i = 0; i < smp_cpus; i++) {
692 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
693 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
694 int irq;
695
696
697
698 const int timer_irq[] = {
699 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
700 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
701 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
702 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
703 };
704
705 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
706 qdev_connect_gpio_out(cpudev, irq,
707 qdev_get_gpio_in(vms->gic,
708 ppibase + timer_irq[irq]));
709 }
710
711 if (type == 3) {
712 qemu_irq irq = qdev_get_gpio_in(vms->gic,
713 ppibase + ARCH_GIC_MAINT_IRQ);
714 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
715 0, irq);
716 } else if (vms->virt) {
717 qemu_irq irq = qdev_get_gpio_in(vms->gic,
718 ppibase + ARCH_GIC_MAINT_IRQ);
719 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
720 }
721
722 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
723 qdev_get_gpio_in(vms->gic, ppibase
724 + VIRTUAL_PMU_IRQ));
725
726 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
727 sysbus_connect_irq(gicbusdev, i + smp_cpus,
728 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
729 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
730 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
731 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
732 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
733 }
734
735 fdt_add_gic_node(vms);
736
737 if (type == 3 && vms->its) {
738 create_its(vms);
739 } else if (type == 2) {
740 create_v2m(vms);
741 }
742}
743
744static void create_uart(const VirtMachineState *vms, int uart,
745 MemoryRegion *mem, Chardev *chr)
746{
747 char *nodename;
748 hwaddr base = vms->memmap[uart].base;
749 hwaddr size = vms->memmap[uart].size;
750 int irq = vms->irqmap[uart];
751 const char compat[] = "arm,pl011\0arm,primecell";
752 const char clocknames[] = "uartclk\0apb_pclk";
753 DeviceState *dev = qdev_new(TYPE_PL011);
754 SysBusDevice *s = SYS_BUS_DEVICE(dev);
755 MachineState *ms = MACHINE(vms);
756
757 qdev_prop_set_chr(dev, "chardev", chr);
758 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
759 memory_region_add_subregion(mem, base,
760 sysbus_mmio_get_region(s, 0));
761 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
762
763 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
764 qemu_fdt_add_subnode(ms->fdt, nodename);
765
766 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
767 compat, sizeof(compat));
768 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
769 2, base, 2, size);
770 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
771 GIC_FDT_IRQ_TYPE_SPI, irq,
772 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
773 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
774 vms->clock_phandle, vms->clock_phandle);
775 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
776 clocknames, sizeof(clocknames));
777
778 if (uart == VIRT_UART) {
779 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
780 } else {
781
782 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
783 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
784
785 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
786 nodename);
787 }
788
789 g_free(nodename);
790}
791
792static void create_rtc(const VirtMachineState *vms)
793{
794 char *nodename;
795 hwaddr base = vms->memmap[VIRT_RTC].base;
796 hwaddr size = vms->memmap[VIRT_RTC].size;
797 int irq = vms->irqmap[VIRT_RTC];
798 const char compat[] = "arm,pl031\0arm,primecell";
799 MachineState *ms = MACHINE(vms);
800
801 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
802
803 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
804 qemu_fdt_add_subnode(ms->fdt, nodename);
805 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
806 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
807 2, base, 2, size);
808 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
809 GIC_FDT_IRQ_TYPE_SPI, irq,
810 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
811 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
812 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
813 g_free(nodename);
814}
815
816static DeviceState *gpio_key_dev;
817static void virt_powerdown_req(Notifier *n, void *opaque)
818{
819 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
820
821 if (s->acpi_dev) {
822 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
823 } else {
824
825 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
826 }
827}
828
829static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
830 uint32_t phandle)
831{
832 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
833 qdev_get_gpio_in(pl061_dev, 3));
834
835 qemu_fdt_add_subnode(fdt, "/gpio-keys");
836 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
837 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0);
838 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1);
839
840 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
841 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
842 "label", "GPIO Key Poweroff");
843 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
844 KEY_POWER);
845 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
846 "gpios", phandle, 3, 0);
847}
848
849#define SECURE_GPIO_POWEROFF 0
850#define SECURE_GPIO_RESET 1
851
852static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
853 uint32_t phandle)
854{
855 DeviceState *gpio_pwr_dev;
856
857
858 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
859
860
861 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
862 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
863 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
864 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
865
866 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
867 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
868 "gpio-poweroff");
869 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
870 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
871 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
872 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
873 "okay");
874
875 qemu_fdt_add_subnode(fdt, "/gpio-restart");
876 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
877 "gpio-restart");
878 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
879 "gpios", phandle, SECURE_GPIO_RESET, 0);
880 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
881 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
882 "okay");
883}
884
885static void create_gpio_devices(const VirtMachineState *vms, int gpio,
886 MemoryRegion *mem)
887{
888 char *nodename;
889 DeviceState *pl061_dev;
890 hwaddr base = vms->memmap[gpio].base;
891 hwaddr size = vms->memmap[gpio].size;
892 int irq = vms->irqmap[gpio];
893 const char compat[] = "arm,pl061\0arm,primecell";
894 SysBusDevice *s;
895 MachineState *ms = MACHINE(vms);
896
897 pl061_dev = qdev_new("pl061");
898
899 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
900 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
901 s = SYS_BUS_DEVICE(pl061_dev);
902 sysbus_realize_and_unref(s, &error_fatal);
903 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
904 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
905
906 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
907 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
908 qemu_fdt_add_subnode(ms->fdt, nodename);
909 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
910 2, base, 2, size);
911 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
912 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
913 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
914 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
915 GIC_FDT_IRQ_TYPE_SPI, irq,
916 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
917 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
918 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
919 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
920
921 if (gpio != VIRT_GPIO) {
922
923 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
924 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
925 }
926 g_free(nodename);
927
928
929 if (gpio == VIRT_GPIO) {
930 create_gpio_keys(ms->fdt, pl061_dev, phandle);
931 } else {
932 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
933 }
934}
935
936static void create_virtio_devices(const VirtMachineState *vms)
937{
938 int i;
939 hwaddr size = vms->memmap[VIRT_MMIO].size;
940 MachineState *ms = MACHINE(vms);
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
970 int irq = vms->irqmap[VIRT_MMIO] + i;
971 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
972
973 sysbus_create_simple("virtio-mmio", base,
974 qdev_get_gpio_in(vms->gic, irq));
975 }
976
977
978
979
980
981
982
983
984 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
985 char *nodename;
986 int irq = vms->irqmap[VIRT_MMIO] + i;
987 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
988
989 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
990 qemu_fdt_add_subnode(ms->fdt, nodename);
991 qemu_fdt_setprop_string(ms->fdt, nodename,
992 "compatible", "virtio,mmio");
993 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
994 2, base, 2, size);
995 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
996 GIC_FDT_IRQ_TYPE_SPI, irq,
997 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
998 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
999 g_free(nodename);
1000 }
1001}
1002
1003#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1004
1005static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1006 const char *name,
1007 const char *alias_prop_name)
1008{
1009
1010
1011
1012
1013 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1014
1015 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1016 qdev_prop_set_uint8(dev, "width", 4);
1017 qdev_prop_set_uint8(dev, "device-width", 2);
1018 qdev_prop_set_bit(dev, "big-endian", false);
1019 qdev_prop_set_uint16(dev, "id0", 0x89);
1020 qdev_prop_set_uint16(dev, "id1", 0x18);
1021 qdev_prop_set_uint16(dev, "id2", 0x00);
1022 qdev_prop_set_uint16(dev, "id3", 0x00);
1023 qdev_prop_set_string(dev, "name", name);
1024 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1025 object_property_add_alias(OBJECT(vms), alias_prop_name,
1026 OBJECT(dev), "drive");
1027 return PFLASH_CFI01(dev);
1028}
1029
1030static void virt_flash_create(VirtMachineState *vms)
1031{
1032 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1033 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1034}
1035
1036static void virt_flash_map1(PFlashCFI01 *flash,
1037 hwaddr base, hwaddr size,
1038 MemoryRegion *sysmem)
1039{
1040 DeviceState *dev = DEVICE(flash);
1041
1042 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1043 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1044 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1045 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1046
1047 memory_region_add_subregion(sysmem, base,
1048 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1049 0));
1050}
1051
1052static void virt_flash_map(VirtMachineState *vms,
1053 MemoryRegion *sysmem,
1054 MemoryRegion *secure_sysmem)
1055{
1056
1057
1058
1059
1060
1061
1062
1063
1064 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1065 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1066
1067 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1068 secure_sysmem);
1069 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1070 sysmem);
1071}
1072
1073static void virt_flash_fdt(VirtMachineState *vms,
1074 MemoryRegion *sysmem,
1075 MemoryRegion *secure_sysmem)
1076{
1077 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1078 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1079 MachineState *ms = MACHINE(vms);
1080 char *nodename;
1081
1082 if (sysmem == secure_sysmem) {
1083
1084 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1085 qemu_fdt_add_subnode(ms->fdt, nodename);
1086 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1087 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1088 2, flashbase, 2, flashsize,
1089 2, flashbase + flashsize, 2, flashsize);
1090 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1091 g_free(nodename);
1092 } else {
1093
1094
1095
1096
1097 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1098 qemu_fdt_add_subnode(ms->fdt, nodename);
1099 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1100 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1101 2, flashbase, 2, flashsize);
1102 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1103 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1104 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1105 g_free(nodename);
1106
1107 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1108 qemu_fdt_add_subnode(ms->fdt, nodename);
1109 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1110 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1111 2, flashbase + flashsize, 2, flashsize);
1112 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1113 g_free(nodename);
1114 }
1115}
1116
1117static bool virt_firmware_init(VirtMachineState *vms,
1118 MemoryRegion *sysmem,
1119 MemoryRegion *secure_sysmem)
1120{
1121 int i;
1122 const char *bios_name;
1123 BlockBackend *pflash_blk0;
1124
1125
1126 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1127 pflash_cfi01_legacy_drive(vms->flash[i],
1128 drive_get(IF_PFLASH, 0, i));
1129 }
1130
1131 virt_flash_map(vms, sysmem, secure_sysmem);
1132
1133 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1134
1135 bios_name = MACHINE(vms)->firmware;
1136 if (bios_name) {
1137 char *fname;
1138 MemoryRegion *mr;
1139 int image_size;
1140
1141 if (pflash_blk0) {
1142 error_report("The contents of the first flash device may be "
1143 "specified with -bios or with -drive if=pflash... "
1144 "but you cannot use both options at once");
1145 exit(1);
1146 }
1147
1148
1149
1150 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1151 if (!fname) {
1152 error_report("Could not find ROM image '%s'", bios_name);
1153 exit(1);
1154 }
1155 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1156 image_size = load_image_mr(fname, mr);
1157 g_free(fname);
1158 if (image_size < 0) {
1159 error_report("Could not load ROM image '%s'", bios_name);
1160 exit(1);
1161 }
1162 }
1163
1164 return pflash_blk0 || bios_name;
1165}
1166
1167static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1168{
1169 MachineState *ms = MACHINE(vms);
1170 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1171 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1172 FWCfgState *fw_cfg;
1173 char *nodename;
1174
1175 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1176 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1177
1178 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1179 qemu_fdt_add_subnode(ms->fdt, nodename);
1180 qemu_fdt_setprop_string(ms->fdt, nodename,
1181 "compatible", "qemu,fw-cfg-mmio");
1182 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1183 2, base, 2, size);
1184 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1185 g_free(nodename);
1186 return fw_cfg;
1187}
1188
1189static void create_pcie_irq_map(const MachineState *ms,
1190 uint32_t gic_phandle,
1191 int first_irq, const char *nodename)
1192{
1193 int devfn, pin;
1194 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1195 uint32_t *irq_map = full_irq_map;
1196
1197 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1198 for (pin = 0; pin < 4; pin++) {
1199 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1200 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1201 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1202 int i;
1203
1204 uint32_t map[] = {
1205 devfn << 8, 0, 0,
1206 pin + 1,
1207 gic_phandle, 0, 0, irq_type, irq_nr, irq_level };
1208
1209
1210 for (i = 0; i < 10; i++) {
1211 irq_map[i] = cpu_to_be32(map[i]);
1212 }
1213 irq_map += 10;
1214 }
1215 }
1216
1217 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1218 full_irq_map, sizeof(full_irq_map));
1219
1220 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1221 cpu_to_be16(PCI_DEVFN(3, 0)),
1222 0, 0,
1223 0x7 );
1224}
1225
1226static void create_smmu(const VirtMachineState *vms,
1227 PCIBus *bus)
1228{
1229 char *node;
1230 const char compat[] = "arm,smmu-v3";
1231 int irq = vms->irqmap[VIRT_SMMU];
1232 int i;
1233 hwaddr base = vms->memmap[VIRT_SMMU].base;
1234 hwaddr size = vms->memmap[VIRT_SMMU].size;
1235 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1236 DeviceState *dev;
1237 MachineState *ms = MACHINE(vms);
1238
1239 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1240 return;
1241 }
1242
1243 dev = qdev_new("arm-smmuv3");
1244
1245 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1246 &error_abort);
1247 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1248 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1249 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1250 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1251 qdev_get_gpio_in(vms->gic, irq + i));
1252 }
1253
1254 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1255 qemu_fdt_add_subnode(ms->fdt, node);
1256 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1257 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1258
1259 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1260 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1261 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1262 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1263 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1264
1265 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1266 sizeof(irq_names));
1267
1268 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
1269 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
1270 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1271
1272 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1273
1274 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1275 g_free(node);
1276}
1277
1278static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1279{
1280 const char compat[] = "virtio,pci-iommu";
1281 uint16_t bdf = vms->virtio_iommu_bdf;
1282 MachineState *ms = MACHINE(vms);
1283 char *node;
1284
1285 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1286
1287 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf);
1288 qemu_fdt_add_subnode(ms->fdt, node);
1289 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1290 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1291 1, bdf << 8, 1, 0, 1, 0,
1292 1, 0, 1, 0);
1293
1294 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1295 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1296 g_free(node);
1297
1298 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1299 0x0, vms->iommu_phandle, 0x0, bdf,
1300 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1301}
1302
1303static void create_pcie(VirtMachineState *vms)
1304{
1305 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1306 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1307 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1308 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1309 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1310 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1311 hwaddr base_ecam, size_ecam;
1312 hwaddr base = base_mmio;
1313 int nr_pcie_buses;
1314 int irq = vms->irqmap[VIRT_PCIE];
1315 MemoryRegion *mmio_alias;
1316 MemoryRegion *mmio_reg;
1317 MemoryRegion *ecam_alias;
1318 MemoryRegion *ecam_reg;
1319 DeviceState *dev;
1320 char *nodename;
1321 int i, ecam_id;
1322 PCIHostState *pci;
1323 MachineState *ms = MACHINE(vms);
1324
1325 dev = qdev_new(TYPE_GPEX_HOST);
1326 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1327
1328 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1329 base_ecam = vms->memmap[ecam_id].base;
1330 size_ecam = vms->memmap[ecam_id].size;
1331 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1332
1333 ecam_alias = g_new0(MemoryRegion, 1);
1334 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1335 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1336 ecam_reg, 0, size_ecam);
1337 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1338
1339
1340
1341
1342
1343
1344 mmio_alias = g_new0(MemoryRegion, 1);
1345 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1346 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1347 mmio_reg, base_mmio, size_mmio);
1348 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1349
1350 if (vms->highmem) {
1351
1352 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1353
1354 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1355 mmio_reg, base_mmio_high, size_mmio_high);
1356 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1357 high_mmio_alias);
1358 }
1359
1360
1361 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1362
1363 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1364 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1365 qdev_get_gpio_in(vms->gic, irq + i));
1366 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1367 }
1368
1369 pci = PCI_HOST_BRIDGE(dev);
1370 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1371 vms->bus = pci->bus;
1372 if (vms->bus) {
1373 for (i = 0; i < nb_nics; i++) {
1374 NICInfo *nd = &nd_table[i];
1375
1376 if (!nd->model) {
1377 nd->model = g_strdup("virtio");
1378 }
1379
1380 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1381 }
1382 }
1383
1384 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1385 qemu_fdt_add_subnode(ms->fdt, nodename);
1386 qemu_fdt_setprop_string(ms->fdt, nodename,
1387 "compatible", "pci-host-ecam-generic");
1388 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1389 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1390 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1391 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1392 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1393 nr_pcie_buses - 1);
1394 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1395
1396 if (vms->msi_phandle) {
1397 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
1398 vms->msi_phandle);
1399 }
1400
1401 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1402 2, base_ecam, 2, size_ecam);
1403
1404 if (vms->highmem) {
1405 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1406 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1407 2, base_pio, 2, size_pio,
1408 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1409 2, base_mmio, 2, size_mmio,
1410 1, FDT_PCI_RANGE_MMIO_64BIT,
1411 2, base_mmio_high,
1412 2, base_mmio_high, 2, size_mmio_high);
1413 } else {
1414 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1415 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1416 2, base_pio, 2, size_pio,
1417 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1418 2, base_mmio, 2, size_mmio);
1419 }
1420
1421 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1422 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1423
1424 if (vms->iommu) {
1425 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1426
1427 switch (vms->iommu) {
1428 case VIRT_IOMMU_SMMUV3:
1429 create_smmu(vms, vms->bus);
1430 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1431 0x0, vms->iommu_phandle, 0x0, 0x10000);
1432 break;
1433 default:
1434 g_assert_not_reached();
1435 }
1436 }
1437}
1438
1439static void create_platform_bus(VirtMachineState *vms)
1440{
1441 DeviceState *dev;
1442 SysBusDevice *s;
1443 int i;
1444 MemoryRegion *sysmem = get_system_memory();
1445
1446 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1447 dev->id = TYPE_PLATFORM_BUS_DEVICE;
1448 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1449 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1450 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1451 vms->platform_bus_dev = dev;
1452
1453 s = SYS_BUS_DEVICE(dev);
1454 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1455 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1456 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1457 }
1458
1459 memory_region_add_subregion(sysmem,
1460 vms->memmap[VIRT_PLATFORM_BUS].base,
1461 sysbus_mmio_get_region(s, 0));
1462}
1463
1464static void create_tag_ram(MemoryRegion *tag_sysmem,
1465 hwaddr base, hwaddr size,
1466 const char *name)
1467{
1468 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1469
1470 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1471 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1472}
1473
1474static void create_secure_ram(VirtMachineState *vms,
1475 MemoryRegion *secure_sysmem,
1476 MemoryRegion *secure_tag_sysmem)
1477{
1478 MemoryRegion *secram = g_new(MemoryRegion, 1);
1479 char *nodename;
1480 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1481 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1482 MachineState *ms = MACHINE(vms);
1483
1484 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1485 &error_fatal);
1486 memory_region_add_subregion(secure_sysmem, base, secram);
1487
1488 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1489 qemu_fdt_add_subnode(ms->fdt, nodename);
1490 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1491 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1492 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1493 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1494
1495 if (secure_tag_sysmem) {
1496 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1497 }
1498
1499 g_free(nodename);
1500}
1501
1502static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1503{
1504 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1505 bootinfo);
1506 MachineState *ms = MACHINE(board);
1507
1508
1509 *fdt_size = board->fdt_size;
1510 return ms->fdt;
1511}
1512
1513static void virt_build_smbios(VirtMachineState *vms)
1514{
1515 MachineClass *mc = MACHINE_GET_CLASS(vms);
1516 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1517 uint8_t *smbios_tables, *smbios_anchor;
1518 size_t smbios_tables_len, smbios_anchor_len;
1519 const char *product = "QEMU Virtual Machine";
1520
1521 if (kvm_enabled()) {
1522 product = "KVM Virtual Machine";
1523 }
1524
1525 smbios_set_defaults("QEMU", product,
1526 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1527 true, SMBIOS_ENTRY_POINT_30);
1528
1529 smbios_get_tables(MACHINE(vms), NULL, 0,
1530 &smbios_tables, &smbios_tables_len,
1531 &smbios_anchor, &smbios_anchor_len,
1532 &error_fatal);
1533
1534 if (smbios_anchor) {
1535 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1536 smbios_tables, smbios_tables_len);
1537 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1538 smbios_anchor, smbios_anchor_len);
1539 }
1540}
1541
1542static
1543void virt_machine_done(Notifier *notifier, void *data)
1544{
1545 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1546 machine_done);
1547 MachineState *ms = MACHINE(vms);
1548 ARMCPU *cpu = ARM_CPU(first_cpu);
1549 struct arm_boot_info *info = &vms->bootinfo;
1550 AddressSpace *as = arm_boot_address_space(cpu, info);
1551
1552
1553
1554
1555
1556
1557
1558
1559 if (info->dtb_filename == NULL) {
1560 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1561 vms->memmap[VIRT_PLATFORM_BUS].base,
1562 vms->memmap[VIRT_PLATFORM_BUS].size,
1563 vms->irqmap[VIRT_PLATFORM_BUS]);
1564 }
1565 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1566 exit(1);
1567 }
1568
1569 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1570
1571 virt_acpi_setup(vms);
1572 virt_build_smbios(vms);
1573}
1574
1575static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1576{
1577 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1578 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1579
1580 if (!vmc->disallow_affinity_adjustment) {
1581
1582
1583
1584
1585
1586
1587
1588
1589 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1590 clustersz = GICV3_TARGETLIST_BITS;
1591 } else {
1592 clustersz = GIC_TARGETLIST_BITS;
1593 }
1594 }
1595 return arm_cpu_mp_affinity(idx, clustersz);
1596}
1597
1598static void virt_set_memmap(VirtMachineState *vms)
1599{
1600 MachineState *ms = MACHINE(vms);
1601 hwaddr base, device_memory_base, device_memory_size;
1602 int i;
1603
1604 vms->memmap = extended_memmap;
1605
1606 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1607 vms->memmap[i] = base_memmap[i];
1608 }
1609
1610 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1611 error_report("unsupported number of memory slots: %"PRIu64,
1612 ms->ram_slots);
1613 exit(EXIT_FAILURE);
1614 }
1615
1616
1617
1618
1619
1620
1621
1622
1623 device_memory_base =
1624 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1625 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1626
1627
1628 base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1629 if (base < device_memory_base) {
1630 error_report("maxmem/slots too huge");
1631 exit(EXIT_FAILURE);
1632 }
1633 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1634 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1635 }
1636
1637 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1638 hwaddr size = extended_memmap[i].size;
1639
1640 base = ROUND_UP(base, size);
1641 vms->memmap[i].base = base;
1642 vms->memmap[i].size = size;
1643 base += size;
1644 }
1645 vms->highest_gpa = base - 1;
1646 if (device_memory_size > 0) {
1647 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1648 ms->device_memory->base = device_memory_base;
1649 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1650 "device-memory", device_memory_size);
1651 }
1652}
1653
1654
1655
1656
1657
1658
1659
1660static void finalize_gic_version(VirtMachineState *vms)
1661{
1662 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1663
1664 if (kvm_enabled()) {
1665 int probe_bitmap;
1666
1667 if (!kvm_irqchip_in_kernel()) {
1668 switch (vms->gic_version) {
1669 case VIRT_GIC_VERSION_HOST:
1670 warn_report(
1671 "gic-version=host not relevant with kernel-irqchip=off "
1672 "as only userspace GICv2 is supported. Using v2 ...");
1673 return;
1674 case VIRT_GIC_VERSION_MAX:
1675 case VIRT_GIC_VERSION_NOSEL:
1676 vms->gic_version = VIRT_GIC_VERSION_2;
1677 return;
1678 case VIRT_GIC_VERSION_2:
1679 return;
1680 case VIRT_GIC_VERSION_3:
1681 error_report(
1682 "gic-version=3 is not supported with kernel-irqchip=off");
1683 exit(1);
1684 }
1685 }
1686
1687 probe_bitmap = kvm_arm_vgic_probe();
1688 if (!probe_bitmap) {
1689 error_report("Unable to determine GIC version supported by host");
1690 exit(1);
1691 }
1692
1693 switch (vms->gic_version) {
1694 case VIRT_GIC_VERSION_HOST:
1695 case VIRT_GIC_VERSION_MAX:
1696 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1697 vms->gic_version = VIRT_GIC_VERSION_3;
1698 } else {
1699 vms->gic_version = VIRT_GIC_VERSION_2;
1700 }
1701 return;
1702 case VIRT_GIC_VERSION_NOSEL:
1703 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
1704 vms->gic_version = VIRT_GIC_VERSION_2;
1705 } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
1706
1707
1708
1709
1710
1711 vms->gic_version = VIRT_GIC_VERSION_3;
1712 } else if (max_cpus > GIC_NCPU) {
1713 error_report("host only supports in-kernel GICv2 emulation "
1714 "but more than 8 vcpus are requested");
1715 exit(1);
1716 }
1717 break;
1718 case VIRT_GIC_VERSION_2:
1719 case VIRT_GIC_VERSION_3:
1720 break;
1721 }
1722
1723
1724 if (vms->gic_version == VIRT_GIC_VERSION_2 &&
1725 !(probe_bitmap & KVM_ARM_VGIC_V2)) {
1726 error_report("host does not support in-kernel GICv2 emulation");
1727 exit(1);
1728 } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
1729 !(probe_bitmap & KVM_ARM_VGIC_V3)) {
1730 error_report("host does not support in-kernel GICv3 emulation");
1731 exit(1);
1732 }
1733 return;
1734 }
1735
1736
1737 switch (vms->gic_version) {
1738 case VIRT_GIC_VERSION_NOSEL:
1739 vms->gic_version = VIRT_GIC_VERSION_2;
1740 break;
1741 case VIRT_GIC_VERSION_MAX:
1742 vms->gic_version = VIRT_GIC_VERSION_3;
1743 break;
1744 case VIRT_GIC_VERSION_HOST:
1745 error_report("gic-version=host requires KVM");
1746 exit(1);
1747 case VIRT_GIC_VERSION_2:
1748 case VIRT_GIC_VERSION_3:
1749 break;
1750 }
1751}
1752
1753
1754
1755
1756
1757static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
1758{
1759 int max_cpus = MACHINE(vms)->smp.max_cpus;
1760 bool aarch64, pmu, steal_time;
1761 CPUState *cpu;
1762
1763 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
1764 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
1765 steal_time = object_property_get_bool(OBJECT(first_cpu),
1766 "kvm-steal-time", NULL);
1767
1768 if (kvm_enabled()) {
1769 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1770 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1771
1772 if (steal_time) {
1773 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1774 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1775
1776
1777 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1778
1779 if (pvtime_size > pvtime_reg_size) {
1780 error_report("pvtime requires a %" HWADDR_PRId
1781 " byte memory region for %d CPUs,"
1782 " but only %" HWADDR_PRId " has been reserved",
1783 pvtime_size, max_cpus, pvtime_reg_size);
1784 exit(1);
1785 }
1786
1787 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1788 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1789 }
1790
1791 CPU_FOREACH(cpu) {
1792 if (pmu) {
1793 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1794 if (kvm_irqchip_in_kernel()) {
1795 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
1796 }
1797 kvm_arm_pmu_init(cpu);
1798 }
1799 if (steal_time) {
1800 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
1801 cpu->cpu_index * PVTIME_SIZE_PER_CPU);
1802 }
1803 }
1804 } else {
1805 if (aarch64 && vms->highmem) {
1806 int requested_pa_size = 64 - clz64(vms->highest_gpa);
1807 int pamax = arm_pamax(ARM_CPU(first_cpu));
1808
1809 if (pamax < requested_pa_size) {
1810 error_report("VCPU supports less PA bits (%d) than "
1811 "requested by the memory map (%d)",
1812 pamax, requested_pa_size);
1813 exit(1);
1814 }
1815 }
1816 }
1817}
1818
1819static void machvirt_init(MachineState *machine)
1820{
1821 VirtMachineState *vms = VIRT_MACHINE(machine);
1822 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1823 MachineClass *mc = MACHINE_GET_CLASS(machine);
1824 const CPUArchIdList *possible_cpus;
1825 MemoryRegion *sysmem = get_system_memory();
1826 MemoryRegion *secure_sysmem = NULL;
1827 MemoryRegion *tag_sysmem = NULL;
1828 MemoryRegion *secure_tag_sysmem = NULL;
1829 int n, virt_max_cpus;
1830 bool firmware_loaded;
1831 bool aarch64 = true;
1832 bool has_ged = !vmc->no_ged;
1833 unsigned int smp_cpus = machine->smp.cpus;
1834 unsigned int max_cpus = machine->smp.max_cpus;
1835
1836
1837
1838
1839
1840 if (!vms->memmap) {
1841 virt_set_memmap(vms);
1842 }
1843
1844
1845
1846
1847 finalize_gic_version(vms);
1848
1849 if (!cpu_type_valid(machine->cpu_type)) {
1850 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1851 exit(1);
1852 }
1853
1854 if (vms->secure) {
1855 if (kvm_enabled()) {
1856 error_report("mach-virt: KVM does not support Security extensions");
1857 exit(1);
1858 }
1859
1860
1861
1862
1863
1864
1865
1866 secure_sysmem = g_new(MemoryRegion, 1);
1867 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1868 UINT64_MAX);
1869 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1870 }
1871
1872 firmware_loaded = virt_firmware_init(vms, sysmem,
1873 secure_sysmem ?: sysmem);
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885 if (vms->secure && firmware_loaded) {
1886 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1887 } else if (vms->virt) {
1888 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1889 } else {
1890 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1891 }
1892
1893
1894
1895
1896 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1897 virt_max_cpus =
1898 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1899 virt_max_cpus +=
1900 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1901 } else {
1902 virt_max_cpus = GIC_NCPU;
1903 }
1904
1905 if (max_cpus > virt_max_cpus) {
1906 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1907 "supported by machine 'mach-virt' (%d)",
1908 max_cpus, virt_max_cpus);
1909 exit(1);
1910 }
1911
1912 if (vms->virt && kvm_enabled()) {
1913 error_report("mach-virt: KVM does not support providing "
1914 "Virtualization extensions to the guest CPU");
1915 exit(1);
1916 }
1917
1918 if (vms->mte && kvm_enabled()) {
1919 error_report("mach-virt: KVM does not support providing "
1920 "MTE to the guest CPU");
1921 exit(1);
1922 }
1923
1924 create_fdt(vms);
1925
1926 possible_cpus = mc->possible_cpu_arch_ids(machine);
1927 assert(possible_cpus->len == max_cpus);
1928 for (n = 0; n < possible_cpus->len; n++) {
1929 Object *cpuobj;
1930 CPUState *cs;
1931
1932 if (n >= smp_cpus) {
1933 break;
1934 }
1935
1936 cpuobj = object_new(possible_cpus->cpus[n].type);
1937 object_property_set_int(cpuobj, "mp-affinity",
1938 possible_cpus->cpus[n].arch_id, NULL);
1939
1940 cs = CPU(cpuobj);
1941 cs->cpu_index = n;
1942
1943 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1944 &error_fatal);
1945
1946 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1947
1948 if (!vms->secure) {
1949 object_property_set_bool(cpuobj, "has_el3", false, NULL);
1950 }
1951
1952 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
1953 object_property_set_bool(cpuobj, "has_el2", false, NULL);
1954 }
1955
1956 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1957 object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit,
1958 NULL);
1959
1960
1961 if (n > 0) {
1962 object_property_set_bool(cpuobj, "start-powered-off", true,
1963 NULL);
1964 }
1965 }
1966
1967 if (vmc->kvm_no_adjvtime &&
1968 object_property_find(cpuobj, "kvm-no-adjvtime")) {
1969 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
1970 }
1971
1972 if (vmc->no_kvm_steal_time &&
1973 object_property_find(cpuobj, "kvm-steal-time")) {
1974 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
1975 }
1976
1977 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
1978 object_property_set_bool(cpuobj, "pmu", false, NULL);
1979 }
1980
1981 if (object_property_find(cpuobj, "reset-cbar")) {
1982 object_property_set_int(cpuobj, "reset-cbar",
1983 vms->memmap[VIRT_CPUPERIPHS].base,
1984 &error_abort);
1985 }
1986
1987 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
1988 &error_abort);
1989 if (vms->secure) {
1990 object_property_set_link(cpuobj, "secure-memory",
1991 OBJECT(secure_sysmem), &error_abort);
1992 }
1993
1994 if (vms->mte) {
1995
1996 if (!tag_sysmem) {
1997
1998
1999
2000
2001 if (!object_property_find(cpuobj, "tag-memory")) {
2002 error_report("MTE requested, but not supported "
2003 "by the guest CPU");
2004 exit(1);
2005 }
2006
2007 tag_sysmem = g_new(MemoryRegion, 1);
2008 memory_region_init(tag_sysmem, OBJECT(machine),
2009 "tag-memory", UINT64_MAX / 32);
2010
2011 if (vms->secure) {
2012 secure_tag_sysmem = g_new(MemoryRegion, 1);
2013 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2014 "secure-tag-memory", UINT64_MAX / 32);
2015
2016
2017 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2018 tag_sysmem, -1);
2019 }
2020 }
2021
2022 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2023 &error_abort);
2024 if (vms->secure) {
2025 object_property_set_link(cpuobj, "secure-tag-memory",
2026 OBJECT(secure_tag_sysmem),
2027 &error_abort);
2028 }
2029 }
2030
2031 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2032 object_unref(cpuobj);
2033 }
2034 fdt_add_timer_nodes(vms);
2035 fdt_add_cpu_nodes(vms);
2036
2037 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2038 machine->ram);
2039 if (machine->device_memory) {
2040 memory_region_add_subregion(sysmem, machine->device_memory->base,
2041 &machine->device_memory->mr);
2042 }
2043
2044 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2045
2046 create_gic(vms);
2047
2048 virt_cpu_post_init(vms, sysmem);
2049
2050 fdt_add_pmu_nodes(vms);
2051
2052 create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
2053
2054 if (vms->secure) {
2055 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2056 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
2057 }
2058
2059 if (tag_sysmem) {
2060 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2061 machine->ram_size, "mach-virt.tag");
2062 }
2063
2064 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
2065
2066 create_rtc(vms);
2067
2068 create_pcie(vms);
2069
2070 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2071 vms->acpi_dev = create_acpi_ged(vms);
2072 } else {
2073 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2074 }
2075
2076 if (vms->secure && !vmc->no_secure_gpio) {
2077 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2078 }
2079
2080
2081 vms->powerdown_notifier.notify = virt_powerdown_req;
2082 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2083
2084
2085
2086
2087
2088 create_virtio_devices(vms);
2089
2090 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2091 rom_set_fw(vms->fw_cfg);
2092
2093 create_platform_bus(vms);
2094
2095 if (machine->nvdimms_state->is_enabled) {
2096 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2097 .space_id = AML_AS_SYSTEM_MEMORY,
2098 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2099 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2100 };
2101
2102 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2103 arm_virt_nvdimm_acpi_dsmio,
2104 vms->fw_cfg, OBJECT(vms));
2105 }
2106
2107 vms->bootinfo.ram_size = machine->ram_size;
2108 vms->bootinfo.nb_cpus = smp_cpus;
2109 vms->bootinfo.board_id = -1;
2110 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2111 vms->bootinfo.get_dtb = machvirt_dtb;
2112 vms->bootinfo.skip_dtb_autoload = true;
2113 vms->bootinfo.firmware_loaded = firmware_loaded;
2114 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2115
2116 vms->machine_done.notify = virt_machine_done;
2117 qemu_add_machine_init_done_notifier(&vms->machine_done);
2118}
2119
2120static bool virt_get_secure(Object *obj, Error **errp)
2121{
2122 VirtMachineState *vms = VIRT_MACHINE(obj);
2123
2124 return vms->secure;
2125}
2126
2127static void virt_set_secure(Object *obj, bool value, Error **errp)
2128{
2129 VirtMachineState *vms = VIRT_MACHINE(obj);
2130
2131 vms->secure = value;
2132}
2133
2134static bool virt_get_virt(Object *obj, Error **errp)
2135{
2136 VirtMachineState *vms = VIRT_MACHINE(obj);
2137
2138 return vms->virt;
2139}
2140
2141static void virt_set_virt(Object *obj, bool value, Error **errp)
2142{
2143 VirtMachineState *vms = VIRT_MACHINE(obj);
2144
2145 vms->virt = value;
2146}
2147
2148static bool virt_get_highmem(Object *obj, Error **errp)
2149{
2150 VirtMachineState *vms = VIRT_MACHINE(obj);
2151
2152 return vms->highmem;
2153}
2154
2155static void virt_set_highmem(Object *obj, bool value, Error **errp)
2156{
2157 VirtMachineState *vms = VIRT_MACHINE(obj);
2158
2159 vms->highmem = value;
2160}
2161
2162static bool virt_get_its(Object *obj, Error **errp)
2163{
2164 VirtMachineState *vms = VIRT_MACHINE(obj);
2165
2166 return vms->its;
2167}
2168
2169static void virt_set_its(Object *obj, bool value, Error **errp)
2170{
2171 VirtMachineState *vms = VIRT_MACHINE(obj);
2172
2173 vms->its = value;
2174}
2175
2176static char *virt_get_oem_id(Object *obj, Error **errp)
2177{
2178 VirtMachineState *vms = VIRT_MACHINE(obj);
2179
2180 return g_strdup(vms->oem_id);
2181}
2182
2183static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2184{
2185 VirtMachineState *vms = VIRT_MACHINE(obj);
2186 size_t len = strlen(value);
2187
2188 if (len > 6) {
2189 error_setg(errp,
2190 "User specified oem-id value is bigger than 6 bytes in size");
2191 return;
2192 }
2193
2194 strncpy(vms->oem_id, value, 6);
2195}
2196
2197static char *virt_get_oem_table_id(Object *obj, Error **errp)
2198{
2199 VirtMachineState *vms = VIRT_MACHINE(obj);
2200
2201 return g_strdup(vms->oem_table_id);
2202}
2203
2204static void virt_set_oem_table_id(Object *obj, const char *value,
2205 Error **errp)
2206{
2207 VirtMachineState *vms = VIRT_MACHINE(obj);
2208 size_t len = strlen(value);
2209
2210 if (len > 8) {
2211 error_setg(errp,
2212 "User specified oem-table-id value is bigger than 8 bytes in size");
2213 return;
2214 }
2215 strncpy(vms->oem_table_id, value, 8);
2216}
2217
2218
2219bool virt_is_acpi_enabled(VirtMachineState *vms)
2220{
2221 if (vms->acpi == ON_OFF_AUTO_OFF) {
2222 return false;
2223 }
2224 return true;
2225}
2226
2227static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2228 void *opaque, Error **errp)
2229{
2230 VirtMachineState *vms = VIRT_MACHINE(obj);
2231 OnOffAuto acpi = vms->acpi;
2232
2233 visit_type_OnOffAuto(v, name, &acpi, errp);
2234}
2235
2236static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2237 void *opaque, Error **errp)
2238{
2239 VirtMachineState *vms = VIRT_MACHINE(obj);
2240
2241 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2242}
2243
2244static bool virt_get_ras(Object *obj, Error **errp)
2245{
2246 VirtMachineState *vms = VIRT_MACHINE(obj);
2247
2248 return vms->ras;
2249}
2250
2251static void virt_set_ras(Object *obj, bool value, Error **errp)
2252{
2253 VirtMachineState *vms = VIRT_MACHINE(obj);
2254
2255 vms->ras = value;
2256}
2257
2258static bool virt_get_mte(Object *obj, Error **errp)
2259{
2260 VirtMachineState *vms = VIRT_MACHINE(obj);
2261
2262 return vms->mte;
2263}
2264
2265static void virt_set_mte(Object *obj, bool value, Error **errp)
2266{
2267 VirtMachineState *vms = VIRT_MACHINE(obj);
2268
2269 vms->mte = value;
2270}
2271
2272static char *virt_get_gic_version(Object *obj, Error **errp)
2273{
2274 VirtMachineState *vms = VIRT_MACHINE(obj);
2275 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
2276
2277 return g_strdup(val);
2278}
2279
2280static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2281{
2282 VirtMachineState *vms = VIRT_MACHINE(obj);
2283
2284 if (!strcmp(value, "3")) {
2285 vms->gic_version = VIRT_GIC_VERSION_3;
2286 } else if (!strcmp(value, "2")) {
2287 vms->gic_version = VIRT_GIC_VERSION_2;
2288 } else if (!strcmp(value, "host")) {
2289 vms->gic_version = VIRT_GIC_VERSION_HOST;
2290 } else if (!strcmp(value, "max")) {
2291 vms->gic_version = VIRT_GIC_VERSION_MAX;
2292 } else {
2293 error_setg(errp, "Invalid gic-version value");
2294 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2295 }
2296}
2297
2298static char *virt_get_iommu(Object *obj, Error **errp)
2299{
2300 VirtMachineState *vms = VIRT_MACHINE(obj);
2301
2302 switch (vms->iommu) {
2303 case VIRT_IOMMU_NONE:
2304 return g_strdup("none");
2305 case VIRT_IOMMU_SMMUV3:
2306 return g_strdup("smmuv3");
2307 default:
2308 g_assert_not_reached();
2309 }
2310}
2311
2312static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2313{
2314 VirtMachineState *vms = VIRT_MACHINE(obj);
2315
2316 if (!strcmp(value, "smmuv3")) {
2317 vms->iommu = VIRT_IOMMU_SMMUV3;
2318 } else if (!strcmp(value, "none")) {
2319 vms->iommu = VIRT_IOMMU_NONE;
2320 } else {
2321 error_setg(errp, "Invalid iommu value");
2322 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2323 }
2324}
2325
2326static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2327{
2328 VirtMachineState *vms = VIRT_MACHINE(obj);
2329
2330 return vms->default_bus_bypass_iommu;
2331}
2332
2333static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2334 Error **errp)
2335{
2336 VirtMachineState *vms = VIRT_MACHINE(obj);
2337
2338 vms->default_bus_bypass_iommu = value;
2339}
2340
2341static CpuInstanceProperties
2342virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2343{
2344 MachineClass *mc = MACHINE_GET_CLASS(ms);
2345 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2346
2347 assert(cpu_index < possible_cpus->len);
2348 return possible_cpus->cpus[cpu_index].props;
2349}
2350
2351static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2352{
2353 return idx % ms->numa_state->num_nodes;
2354}
2355
2356static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2357{
2358 int n;
2359 unsigned int max_cpus = ms->smp.max_cpus;
2360 VirtMachineState *vms = VIRT_MACHINE(ms);
2361
2362 if (ms->possible_cpus) {
2363 assert(ms->possible_cpus->len == max_cpus);
2364 return ms->possible_cpus;
2365 }
2366
2367 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2368 sizeof(CPUArchId) * max_cpus);
2369 ms->possible_cpus->len = max_cpus;
2370 for (n = 0; n < ms->possible_cpus->len; n++) {
2371 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2372 ms->possible_cpus->cpus[n].arch_id =
2373 virt_cpu_mp_affinity(vms, n);
2374 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2375 ms->possible_cpus->cpus[n].props.thread_id = n;
2376 }
2377 return ms->possible_cpus;
2378}
2379
2380static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2381 Error **errp)
2382{
2383 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2384 const MachineState *ms = MACHINE(hotplug_dev);
2385 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2386
2387 if (!vms->acpi_dev) {
2388 error_setg(errp,
2389 "memory hotplug is not enabled: missing acpi-ged device");
2390 return;
2391 }
2392
2393 if (vms->mte) {
2394 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2395 return;
2396 }
2397
2398 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2399 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2400 return;
2401 }
2402
2403 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2404}
2405
2406static void virt_memory_plug(HotplugHandler *hotplug_dev,
2407 DeviceState *dev, Error **errp)
2408{
2409 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2410 MachineState *ms = MACHINE(hotplug_dev);
2411 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2412
2413 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2414
2415 if (is_nvdimm) {
2416 nvdimm_plug(ms->nvdimms_state);
2417 }
2418
2419 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2420 dev, &error_abort);
2421}
2422
2423static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2424 DeviceState *dev, Error **errp)
2425{
2426 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2427
2428 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2429 virt_memory_pre_plug(hotplug_dev, dev, errp);
2430 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2431 hwaddr db_start = 0, db_end = 0;
2432 char *resv_prop_str;
2433
2434 switch (vms->msi_controller) {
2435 case VIRT_MSI_CTRL_NONE:
2436 return;
2437 case VIRT_MSI_CTRL_ITS:
2438
2439 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2440 db_end = base_memmap[VIRT_GIC_ITS].base +
2441 base_memmap[VIRT_GIC_ITS].size - 1;
2442 break;
2443 case VIRT_MSI_CTRL_GICV2M:
2444
2445 db_start = base_memmap[VIRT_GIC_V2M].base;
2446 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2447 break;
2448 }
2449 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2450 db_start, db_end,
2451 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2452
2453 qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
2454 qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
2455 g_free(resv_prop_str);
2456 }
2457}
2458
2459static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2460 DeviceState *dev, Error **errp)
2461{
2462 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2463
2464 if (vms->platform_bus_dev) {
2465 MachineClass *mc = MACHINE_GET_CLASS(vms);
2466
2467 if (device_is_dynamic_sysbus(mc, dev)) {
2468 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2469 SYS_BUS_DEVICE(dev));
2470 }
2471 }
2472 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2473 virt_memory_plug(hotplug_dev, dev, errp);
2474 }
2475 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2476 PCIDevice *pdev = PCI_DEVICE(dev);
2477
2478 vms->iommu = VIRT_IOMMU_VIRTIO;
2479 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2480 create_virtio_iommu_dt_bindings(vms);
2481 }
2482}
2483
2484static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2485 DeviceState *dev, Error **errp)
2486{
2487 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2488 Error *local_err = NULL;
2489
2490 if (!vms->acpi_dev) {
2491 error_setg(&local_err,
2492 "memory hotplug is not enabled: missing acpi-ged device");
2493 goto out;
2494 }
2495
2496 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2497 error_setg(&local_err,
2498 "nvdimm device hot unplug is not supported yet.");
2499 goto out;
2500 }
2501
2502 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2503 &local_err);
2504out:
2505 error_propagate(errp, local_err);
2506}
2507
2508static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2509 DeviceState *dev, Error **errp)
2510{
2511 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2512 Error *local_err = NULL;
2513
2514 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2515 if (local_err) {
2516 goto out;
2517 }
2518
2519 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2520 qdev_unrealize(dev);
2521
2522out:
2523 error_propagate(errp, local_err);
2524}
2525
2526static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2527 DeviceState *dev, Error **errp)
2528{
2529 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2530 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2531 } else {
2532 error_setg(errp, "device unplug request for unsupported device"
2533 " type: %s", object_get_typename(OBJECT(dev)));
2534 }
2535}
2536
2537static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2538 DeviceState *dev, Error **errp)
2539{
2540 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2541 virt_dimm_unplug(hotplug_dev, dev, errp);
2542 } else {
2543 error_setg(errp, "virt: device unplug for unsupported device"
2544 " type: %s", object_get_typename(OBJECT(dev)));
2545 }
2546}
2547
2548static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2549 DeviceState *dev)
2550{
2551 MachineClass *mc = MACHINE_GET_CLASS(machine);
2552
2553 if (device_is_dynamic_sysbus(mc, dev) ||
2554 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
2555 return HOTPLUG_HANDLER(machine);
2556 }
2557 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2558 VirtMachineState *vms = VIRT_MACHINE(machine);
2559
2560 if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
2561 return HOTPLUG_HANDLER(machine);
2562 }
2563 }
2564 return NULL;
2565}
2566
2567
2568
2569
2570
2571static int virt_kvm_type(MachineState *ms, const char *type_str)
2572{
2573 VirtMachineState *vms = VIRT_MACHINE(ms);
2574 int max_vm_pa_size, requested_pa_size;
2575 bool fixed_ipa;
2576
2577 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
2578
2579
2580 virt_set_memmap(vms);
2581
2582 requested_pa_size = 64 - clz64(vms->highest_gpa);
2583
2584
2585
2586
2587 if (requested_pa_size < 32) {
2588 requested_pa_size = 32;
2589 }
2590
2591 if (requested_pa_size > max_vm_pa_size) {
2592 error_report("-m and ,maxmem option values "
2593 "require an IPA range (%d bits) larger than "
2594 "the one supported by the host (%d bits)",
2595 requested_pa_size, max_vm_pa_size);
2596 exit(1);
2597 }
2598
2599
2600
2601
2602
2603 return fixed_ipa ? 0 : requested_pa_size;
2604}
2605
2606static void virt_machine_class_init(ObjectClass *oc, void *data)
2607{
2608 MachineClass *mc = MACHINE_CLASS(oc);
2609 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2610
2611 mc->init = machvirt_init;
2612
2613
2614
2615
2616 mc->max_cpus = 512;
2617 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2618 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2619 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2620 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2621#ifdef CONFIG_TPM
2622 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2623#endif
2624 mc->block_default_type = IF_VIRTIO;
2625 mc->no_cdrom = 1;
2626 mc->pci_allow_0_address = true;
2627
2628 mc->minimum_page_bits = 12;
2629 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2630 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2631 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2632 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2633 mc->kvm_type = virt_kvm_type;
2634 assert(!mc->get_hotplug_handler);
2635 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2636 hc->pre_plug = virt_machine_device_pre_plug_cb;
2637 hc->plug = virt_machine_device_plug_cb;
2638 hc->unplug_request = virt_machine_device_unplug_request_cb;
2639 hc->unplug = virt_machine_device_unplug_cb;
2640 mc->nvdimm_supported = true;
2641 mc->auto_enable_numa_with_memhp = true;
2642 mc->auto_enable_numa_with_memdev = true;
2643 mc->default_ram_id = "mach-virt.ram";
2644
2645 object_class_property_add(oc, "acpi", "OnOffAuto",
2646 virt_get_acpi, virt_set_acpi,
2647 NULL, NULL);
2648 object_class_property_set_description(oc, "acpi",
2649 "Enable ACPI");
2650 object_class_property_add_bool(oc, "secure", virt_get_secure,
2651 virt_set_secure);
2652 object_class_property_set_description(oc, "secure",
2653 "Set on/off to enable/disable the ARM "
2654 "Security Extensions (TrustZone)");
2655
2656 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
2657 virt_set_virt);
2658 object_class_property_set_description(oc, "virtualization",
2659 "Set on/off to enable/disable emulating a "
2660 "guest CPU which implements the ARM "
2661 "Virtualization Extensions");
2662
2663 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
2664 virt_set_highmem);
2665 object_class_property_set_description(oc, "highmem",
2666 "Set on/off to enable/disable using "
2667 "physical address space above 32 bits");
2668
2669 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
2670 virt_set_gic_version);
2671 object_class_property_set_description(oc, "gic-version",
2672 "Set GIC version. "
2673 "Valid values are 2, 3, host and max");
2674
2675 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
2676 object_class_property_set_description(oc, "iommu",
2677 "Set the IOMMU type. "
2678 "Valid values are none and smmuv3");
2679
2680 object_class_property_add_bool(oc, "default_bus_bypass_iommu",
2681 virt_get_default_bus_bypass_iommu,
2682 virt_set_default_bus_bypass_iommu);
2683 object_class_property_set_description(oc, "default_bus_bypass_iommu",
2684 "Set on/off to enable/disable "
2685 "bypass_iommu for default root bus");
2686
2687 object_class_property_add_bool(oc, "ras", virt_get_ras,
2688 virt_set_ras);
2689 object_class_property_set_description(oc, "ras",
2690 "Set on/off to enable/disable reporting host memory errors "
2691 "to a KVM guest using ACPI and guest external abort exceptions");
2692
2693 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
2694 object_class_property_set_description(oc, "mte",
2695 "Set on/off to enable/disable emulating a "
2696 "guest CPU which implements the ARM "
2697 "Memory Tagging Extension");
2698
2699 object_class_property_add_bool(oc, "its", virt_get_its,
2700 virt_set_its);
2701 object_class_property_set_description(oc, "its",
2702 "Set on/off to enable/disable "
2703 "ITS instantiation");
2704
2705 object_class_property_add_str(oc, "x-oem-id",
2706 virt_get_oem_id,
2707 virt_set_oem_id);
2708 object_class_property_set_description(oc, "x-oem-id",
2709 "Override the default value of field OEMID "
2710 "in ACPI table header."
2711 "The string may be up to 6 bytes in size");
2712
2713
2714 object_class_property_add_str(oc, "x-oem-table-id",
2715 virt_get_oem_table_id,
2716 virt_set_oem_table_id);
2717 object_class_property_set_description(oc, "x-oem-table-id",
2718 "Override the default value of field OEM Table ID "
2719 "in ACPI table header."
2720 "The string may be up to 8 bytes in size");
2721
2722}
2723
2724static void virt_instance_init(Object *obj)
2725{
2726 VirtMachineState *vms = VIRT_MACHINE(obj);
2727 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
2728
2729
2730
2731
2732
2733 vms->secure = false;
2734
2735
2736 vms->virt = false;
2737
2738
2739 vms->highmem = true;
2740 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
2741
2742 vms->highmem_ecam = !vmc->no_highmem_ecam;
2743
2744 if (vmc->no_its) {
2745 vms->its = false;
2746 } else {
2747
2748 vms->its = true;
2749 }
2750
2751
2752 vms->iommu = VIRT_IOMMU_NONE;
2753
2754
2755 vms->default_bus_bypass_iommu = false;
2756
2757
2758 vms->ras = false;
2759
2760
2761 vms->mte = false;
2762
2763 vms->irqmap = a15irqmap;
2764
2765 virt_flash_create(vms);
2766
2767 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
2768 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
2769}
2770
2771static const TypeInfo virt_machine_info = {
2772 .name = TYPE_VIRT_MACHINE,
2773 .parent = TYPE_MACHINE,
2774 .abstract = true,
2775 .instance_size = sizeof(VirtMachineState),
2776 .class_size = sizeof(VirtMachineClass),
2777 .class_init = virt_machine_class_init,
2778 .instance_init = virt_instance_init,
2779 .interfaces = (InterfaceInfo[]) {
2780 { TYPE_HOTPLUG_HANDLER },
2781 { }
2782 },
2783};
2784
2785static void machvirt_machine_init(void)
2786{
2787 type_register_static(&virt_machine_info);
2788}
2789type_init(machvirt_machine_init);
2790
2791static void virt_machine_6_1_options(MachineClass *mc)
2792{
2793}
2794DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
2795
2796static void virt_machine_6_0_options(MachineClass *mc)
2797{
2798 virt_machine_6_1_options(mc);
2799 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
2800}
2801DEFINE_VIRT_MACHINE(6, 0)
2802
2803static void virt_machine_5_2_options(MachineClass *mc)
2804{
2805 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2806
2807 virt_machine_6_0_options(mc);
2808 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
2809 vmc->no_secure_gpio = true;
2810}
2811DEFINE_VIRT_MACHINE(5, 2)
2812
2813static void virt_machine_5_1_options(MachineClass *mc)
2814{
2815 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2816
2817 virt_machine_5_2_options(mc);
2818 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
2819 vmc->no_kvm_steal_time = true;
2820}
2821DEFINE_VIRT_MACHINE(5, 1)
2822
2823static void virt_machine_5_0_options(MachineClass *mc)
2824{
2825 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2826
2827 virt_machine_5_1_options(mc);
2828 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
2829 mc->numa_mem_supported = true;
2830 vmc->acpi_expose_flash = true;
2831 mc->auto_enable_numa_with_memdev = false;
2832}
2833DEFINE_VIRT_MACHINE(5, 0)
2834
2835static void virt_machine_4_2_options(MachineClass *mc)
2836{
2837 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2838
2839 virt_machine_5_0_options(mc);
2840 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
2841 vmc->kvm_no_adjvtime = true;
2842}
2843DEFINE_VIRT_MACHINE(4, 2)
2844
2845static void virt_machine_4_1_options(MachineClass *mc)
2846{
2847 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2848
2849 virt_machine_4_2_options(mc);
2850 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
2851 vmc->no_ged = true;
2852 mc->auto_enable_numa_with_memhp = false;
2853}
2854DEFINE_VIRT_MACHINE(4, 1)
2855
2856static void virt_machine_4_0_options(MachineClass *mc)
2857{
2858 virt_machine_4_1_options(mc);
2859 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2860}
2861DEFINE_VIRT_MACHINE(4, 0)
2862
2863static void virt_machine_3_1_options(MachineClass *mc)
2864{
2865 virt_machine_4_0_options(mc);
2866 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2867}
2868DEFINE_VIRT_MACHINE(3, 1)
2869
2870static void virt_machine_3_0_options(MachineClass *mc)
2871{
2872 virt_machine_3_1_options(mc);
2873 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2874}
2875DEFINE_VIRT_MACHINE(3, 0)
2876
2877static void virt_machine_2_12_options(MachineClass *mc)
2878{
2879 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2880
2881 virt_machine_3_0_options(mc);
2882 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2883 vmc->no_highmem_ecam = true;
2884 mc->max_cpus = 255;
2885}
2886DEFINE_VIRT_MACHINE(2, 12)
2887
2888static void virt_machine_2_11_options(MachineClass *mc)
2889{
2890 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2891
2892 virt_machine_2_12_options(mc);
2893 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2894 vmc->smbios_old_sys_ver = true;
2895}
2896DEFINE_VIRT_MACHINE(2, 11)
2897
2898static void virt_machine_2_10_options(MachineClass *mc)
2899{
2900 virt_machine_2_11_options(mc);
2901 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2902
2903 mc->ignore_memory_transaction_failures = true;
2904}
2905DEFINE_VIRT_MACHINE(2, 10)
2906
2907static void virt_machine_2_9_options(MachineClass *mc)
2908{
2909 virt_machine_2_10_options(mc);
2910 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2911}
2912DEFINE_VIRT_MACHINE(2, 9)
2913
2914static void virt_machine_2_8_options(MachineClass *mc)
2915{
2916 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2917
2918 virt_machine_2_9_options(mc);
2919 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
2920
2921
2922
2923 vmc->claim_edge_triggered_timers = true;
2924}
2925DEFINE_VIRT_MACHINE(2, 8)
2926
2927static void virt_machine_2_7_options(MachineClass *mc)
2928{
2929 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2930
2931 virt_machine_2_8_options(mc);
2932 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2933
2934 vmc->no_its = true;
2935
2936 mc->minimum_page_bits = 0;
2937}
2938DEFINE_VIRT_MACHINE(2, 7)
2939
2940static void virt_machine_2_6_options(MachineClass *mc)
2941{
2942 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2943
2944 virt_machine_2_7_options(mc);
2945 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
2946 vmc->disallow_affinity_adjustment = true;
2947
2948 vmc->no_pmu = true;
2949}
2950DEFINE_VIRT_MACHINE(2, 6)
2951