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12#include "qemu/osdep.h"
13#include "qemu/units.h"
14#include "qapi/error.h"
15#include "qemu/module.h"
16#include "hw/sysbus.h"
17#include "net/net.h"
18#include "sysemu/sysemu.h"
19#include "sysemu/kvm.h"
20#include "hw/arm/boot.h"
21#include "kvm_arm.h"
22#include "hw/misc/unimp.h"
23#include "hw/arm/xlnx-versal.h"
24
25#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
26#define GEM_REVISION 0x40070106
27
28static void versal_create_apu_cpus(Versal *s)
29{
30 int i;
31
32 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
33 Object *obj;
34
35 object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
36 XLNX_VERSAL_ACPU_TYPE);
37 obj = OBJECT(&s->fpd.apu.cpu[i]);
38 object_property_set_int(obj, "psci-conduit", s->cfg.psci_conduit,
39 &error_abort);
40 if (i) {
41
42 object_property_set_bool(obj, "start-powered-off", true,
43 &error_abort);
44 }
45
46 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu),
47 &error_abort);
48 object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr),
49 &error_abort);
50 qdev_realize(DEVICE(obj), NULL, &error_fatal);
51 }
52}
53
54static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
55{
56 static const uint64_t addrs[] = {
57 MM_GIC_APU_DIST_MAIN,
58 MM_GIC_APU_REDIST_0
59 };
60 SysBusDevice *gicbusdev;
61 DeviceState *gicdev;
62 int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
63 int i;
64
65 object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic,
66 gicv3_class_name());
67 gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
68 gicdev = DEVICE(&s->fpd.apu.gic);
69 qdev_prop_set_uint32(gicdev, "revision", 3);
70 qdev_prop_set_uint32(gicdev, "num-cpu", nr_apu_cpus);
71 qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
72 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
73 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", nr_apu_cpus);
74 qdev_prop_set_bit(gicdev, "has-security-extensions", true);
75
76 sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal);
77
78 for (i = 0; i < ARRAY_SIZE(addrs); i++) {
79 MemoryRegion *mr;
80
81 mr = sysbus_mmio_get_region(gicbusdev, i);
82 memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
83 }
84
85 for (i = 0; i < nr_apu_cpus; i++) {
86 DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
87 int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
88 qemu_irq maint_irq;
89 int ti;
90
91
92
93 const int timer_irq[] = {
94 [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
95 [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
96 [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ,
97 [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ,
98 };
99
100 for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
101 qdev_connect_gpio_out(cpudev, ti,
102 qdev_get_gpio_in(gicdev,
103 ppibase + timer_irq[ti]));
104 }
105 maint_irq = qdev_get_gpio_in(gicdev,
106 ppibase + VERSAL_GIC_MAINT_IRQ);
107 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
108 0, maint_irq);
109 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
110 sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
111 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
112 sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
113 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
114 sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
115 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
116 }
117
118 for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
119 pic[i] = qdev_get_gpio_in(gicdev, i);
120 }
121}
122
123static void versal_create_uarts(Versal *s, qemu_irq *pic)
124{
125 int i;
126
127 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
128 static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
129 static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
130 char *name = g_strdup_printf("uart%d", i);
131 DeviceState *dev;
132 MemoryRegion *mr;
133
134 object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i],
135 TYPE_PL011);
136 dev = DEVICE(&s->lpd.iou.uart[i]);
137 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
138 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
139
140 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
141 memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
142
143 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
144 g_free(name);
145 }
146}
147
148static void versal_create_usbs(Versal *s, qemu_irq *pic)
149{
150 DeviceState *dev;
151 MemoryRegion *mr;
152
153 object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb,
154 TYPE_XILINX_VERSAL_USB2);
155 dev = DEVICE(&s->lpd.iou.usb);
156
157 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
158 &error_abort);
159 qdev_prop_set_uint32(dev, "intrs", 1);
160 qdev_prop_set_uint32(dev, "slots", 2);
161
162 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
163
164 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
165 memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr);
166
167 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]);
168
169 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
170 memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr);
171}
172
173static void versal_create_gems(Versal *s, qemu_irq *pic)
174{
175 int i;
176
177 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
178 static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
179 static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
180 char *name = g_strdup_printf("gem%d", i);
181 NICInfo *nd = &nd_table[i];
182 DeviceState *dev;
183 MemoryRegion *mr;
184
185 object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i],
186 TYPE_CADENCE_GEM);
187 dev = DEVICE(&s->lpd.iou.gem[i]);
188
189 if (nd->used) {
190 qemu_check_nic_model(nd, "cadence_gem");
191 qdev_set_nic_properties(dev, nd);
192 }
193 object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
194 object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
195 &error_abort);
196 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
197 &error_abort);
198 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
199
200 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
201 memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
202
203 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
204 g_free(name);
205 }
206}
207
208static void versal_create_admas(Versal *s, qemu_irq *pic)
209{
210 int i;
211
212 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
213 char *name = g_strdup_printf("adma%d", i);
214 DeviceState *dev;
215 MemoryRegion *mr;
216
217 object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i],
218 TYPE_XLNX_ZDMA);
219 dev = DEVICE(&s->lpd.iou.adma[i]);
220 object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort);
221 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
222
223 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
224 memory_region_add_subregion(&s->mr_ps,
225 MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
226
227 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);
228 g_free(name);
229 }
230}
231
232#define SDHCI_CAPABILITIES 0x280737ec6481
233static void versal_create_sds(Versal *s, qemu_irq *pic)
234{
235 int i;
236
237 for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
238 DeviceState *dev;
239 MemoryRegion *mr;
240
241 object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i],
242 TYPE_SYSBUS_SDHCI);
243 dev = DEVICE(&s->pmc.iou.sd[i]);
244
245 object_property_set_uint(OBJECT(dev), "sd-spec-version", 3,
246 &error_fatal);
247 object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES,
248 &error_fatal);
249 object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal);
250 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
251
252 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
253 memory_region_add_subregion(&s->mr_ps,
254 MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
255
256 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
257 pic[VERSAL_SD0_IRQ_0 + i * 2]);
258 }
259}
260
261static void versal_create_rtc(Versal *s, qemu_irq *pic)
262{
263 SysBusDevice *sbd;
264 MemoryRegion *mr;
265
266 object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc,
267 TYPE_XLNX_ZYNQMP_RTC);
268 sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
269 sysbus_realize(SYS_BUS_DEVICE(sbd), &error_fatal);
270
271 mr = sysbus_mmio_get_region(sbd, 0);
272 memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
273
274
275
276
277
278 sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
279}
280
281static void versal_create_xrams(Versal *s, qemu_irq *pic)
282{
283 int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl);
284 DeviceState *orgate;
285 int i;
286
287
288 object_initialize_child(OBJECT(s), "xram-irq-orgate",
289 &s->lpd.xram.irq_orgate, TYPE_OR_IRQ);
290 orgate = DEVICE(&s->lpd.xram.irq_orgate);
291 object_property_set_int(OBJECT(orgate),
292 "num-lines", nr_xrams, &error_fatal);
293 qdev_realize(orgate, NULL, &error_fatal);
294 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]);
295
296 for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) {
297 SysBusDevice *sbd;
298 MemoryRegion *mr;
299
300 object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i],
301 TYPE_XLNX_XRAM_CTRL);
302 sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]);
303 sysbus_realize(sbd, &error_fatal);
304
305 mr = sysbus_mmio_get_region(sbd, 0);
306 memory_region_add_subregion(&s->mr_ps,
307 MM_XRAMC + i * MM_XRAMC_SIZE, mr);
308 mr = sysbus_mmio_get_region(sbd, 1);
309 memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr);
310
311 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i));
312 }
313}
314
315
316
317
318static void versal_map_ddr(Versal *s)
319{
320 uint64_t size = memory_region_size(s->cfg.mr_ddr);
321
322 static const struct {
323 uint64_t base;
324 uint64_t size;
325 } addr_ranges[] = {
326 { MM_TOP_DDR, MM_TOP_DDR_SIZE },
327 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
328 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
329 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
330 };
331 uint64_t offset = 0;
332 int i;
333
334 assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
335 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
336 char *name;
337 uint64_t mapsize;
338
339 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
340 name = g_strdup_printf("noc-ddr-range%d", i);
341
342 memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
343 name, s->cfg.mr_ddr,
344 offset, mapsize);
345
346
347 memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
348 &s->noc.mr_ddr_ranges[i]);
349 offset += mapsize;
350 size -= mapsize;
351 g_free(name);
352 }
353}
354
355static void versal_unimp_area(Versal *s, const char *name,
356 MemoryRegion *mr,
357 hwaddr base, hwaddr size)
358{
359 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
360 MemoryRegion *mr_dev;
361
362 qdev_prop_set_string(dev, "name", name);
363 qdev_prop_set_uint64(dev, "size", size);
364 object_property_add_child(OBJECT(s), name, OBJECT(dev));
365 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
366
367 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
368 memory_region_add_subregion(mr, base, mr_dev);
369}
370
371static void versal_unimp(Versal *s)
372{
373 versal_unimp_area(s, "psm", &s->mr_ps,
374 MM_PSM_START, MM_PSM_END - MM_PSM_START);
375 versal_unimp_area(s, "crl", &s->mr_ps,
376 MM_CRL, MM_CRL_SIZE);
377 versal_unimp_area(s, "crf", &s->mr_ps,
378 MM_FPD_CRF, MM_FPD_CRF_SIZE);
379 versal_unimp_area(s, "crp", &s->mr_ps,
380 MM_PMC_CRP, MM_PMC_CRP_SIZE);
381 versal_unimp_area(s, "iou-scntr", &s->mr_ps,
382 MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
383 versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
384 MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
385}
386
387static void versal_realize(DeviceState *dev, Error **errp)
388{
389 Versal *s = XLNX_VERSAL(dev);
390 qemu_irq pic[XLNX_VERSAL_NR_IRQS];
391
392 versal_create_apu_cpus(s);
393 versal_create_apu_gic(s, pic);
394 versal_create_uarts(s, pic);
395 versal_create_usbs(s, pic);
396 versal_create_gems(s, pic);
397 versal_create_admas(s, pic);
398 versal_create_sds(s, pic);
399 versal_create_rtc(s, pic);
400 versal_create_xrams(s, pic);
401 versal_map_ddr(s);
402 versal_unimp(s);
403
404
405 memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
406 MM_OCM_SIZE, &error_fatal);
407
408 memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
409 memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
410}
411
412static void versal_init(Object *obj)
413{
414 Versal *s = XLNX_VERSAL(obj);
415
416 memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
417 memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
418}
419
420static Property versal_properties[] = {
421 DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
422 MemoryRegion *),
423 DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0),
424 DEFINE_PROP_END_OF_LIST()
425};
426
427static void versal_class_init(ObjectClass *klass, void *data)
428{
429 DeviceClass *dc = DEVICE_CLASS(klass);
430
431 dc->realize = versal_realize;
432 device_class_set_props(dc, versal_properties);
433
434}
435
436static const TypeInfo versal_info = {
437 .name = TYPE_XLNX_VERSAL,
438 .parent = TYPE_SYS_BUS_DEVICE,
439 .instance_size = sizeof(Versal),
440 .instance_init = versal_init,
441 .class_init = versal_class_init,
442};
443
444static void versal_register_types(void)
445{
446 type_register_static(&versal_info);
447}
448
449type_init(versal_register_types);
450
