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9#include "qemu/osdep.h"
10#include "qemu/host-utils.h"
11#include "qemu/log.h"
12#include "hw/gpio/aspeed_gpio.h"
13#include "hw/misc/aspeed_scu.h"
14#include "qapi/error.h"
15#include "qapi/visitor.h"
16#include "hw/irq.h"
17#include "migration/vmstate.h"
18
19#define GPIOS_PER_REG 32
20#define GPIOS_PER_SET GPIOS_PER_REG
21#define GPIO_PIN_GAP_SIZE 4
22#define GPIOS_PER_GROUP 8
23#define GPIO_GROUP_SHIFT 3
24
25
26#define ASPEED_CMD_SRC_MASK 0x01010101
27#define ASPEED_SOURCE_ARM 0
28#define ASPEED_SOURCE_LPC 1
29#define ASPEED_SOURCE_COPROCESSOR 2
30#define ASPEED_SOURCE_RESERVED 3
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44
45#define ASPEED_FALLING_EDGE 0
46#define ASPEED_RISING_EDGE 1
47#define ASPEED_LEVEL_LOW 2
48#define ASPEED_LEVEL_HIGH 3
49#define ASPEED_DUAL_EDGE 4
50
51
52#define GPIO_ABCD_DATA_VALUE (0x000 >> 2)
53#define GPIO_ABCD_DIRECTION (0x004 >> 2)
54#define GPIO_ABCD_INT_ENABLE (0x008 >> 2)
55#define GPIO_ABCD_INT_SENS_0 (0x00C >> 2)
56#define GPIO_ABCD_INT_SENS_1 (0x010 >> 2)
57#define GPIO_ABCD_INT_SENS_2 (0x014 >> 2)
58#define GPIO_ABCD_INT_STATUS (0x018 >> 2)
59#define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2)
60#define GPIO_EFGH_DATA_VALUE (0x020 >> 2)
61#define GPIO_EFGH_DIRECTION (0x024 >> 2)
62#define GPIO_EFGH_INT_ENABLE (0x028 >> 2)
63#define GPIO_EFGH_INT_SENS_0 (0x02C >> 2)
64#define GPIO_EFGH_INT_SENS_1 (0x030 >> 2)
65#define GPIO_EFGH_INT_SENS_2 (0x034 >> 2)
66#define GPIO_EFGH_INT_STATUS (0x038 >> 2)
67#define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2)
68#define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2)
69#define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2)
70#define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2)
71#define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2)
72#define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2)
73#define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2)
74#define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2)
75#define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2)
76#define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2)
77#define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2)
78#define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2)
79#define GPIO_IJKL_DATA_VALUE (0x070 >> 2)
80#define GPIO_IJKL_DIRECTION (0x074 >> 2)
81#define GPIO_MNOP_DATA_VALUE (0x078 >> 2)
82#define GPIO_MNOP_DIRECTION (0x07C >> 2)
83#define GPIO_QRST_DATA_VALUE (0x080 >> 2)
84#define GPIO_QRST_DIRECTION (0x084 >> 2)
85#define GPIO_UVWX_DATA_VALUE (0x088 >> 2)
86#define GPIO_UVWX_DIRECTION (0x08C >> 2)
87#define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2)
88#define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2)
89#define GPIO_IJKL_INT_ENABLE (0x098 >> 2)
90#define GPIO_IJKL_INT_SENS_0 (0x09C >> 2)
91#define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2)
92#define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2)
93#define GPIO_IJKL_INT_STATUS (0x0A8 >> 2)
94#define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2)
95#define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2)
96#define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2)
97#define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2)
98#define GPIO_ABCD_DATA_READ (0x0C0 >> 2)
99#define GPIO_EFGH_DATA_READ (0x0C4 >> 2)
100#define GPIO_IJKL_DATA_READ (0x0C8 >> 2)
101#define GPIO_MNOP_DATA_READ (0x0CC >> 2)
102#define GPIO_QRST_DATA_READ (0x0D0 >> 2)
103#define GPIO_UVWX_DATA_READ (0x0D4 >> 2)
104#define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2)
105#define GPIO_AC_DATA_READ (0x0DC >> 2)
106#define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2)
107#define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2)
108#define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2)
109#define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2)
110#define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2)
111#define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2)
112#define GPIO_MNOP_INT_STATUS (0x0F8 >> 2)
113#define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2)
114#define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2)
115#define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2)
116#define GPIO_MNOP_INPUT_MASK (0x108 >> 2)
117#define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2)
118#define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2)
119#define GPIO_QRST_INT_ENABLE (0x118 >> 2)
120#define GPIO_QRST_INT_SENS_0 (0x11C >> 2)
121#define GPIO_QRST_INT_SENS_1 (0x120 >> 2)
122#define GPIO_QRST_INT_SENS_2 (0x124 >> 2)
123#define GPIO_QRST_INT_STATUS (0x128 >> 2)
124#define GPIO_QRST_RESET_TOLERANT (0x12C >> 2)
125#define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2)
126#define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2)
127#define GPIO_QRST_INPUT_MASK (0x138 >> 2)
128#define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2)
129#define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2)
130#define GPIO_UVWX_INT_ENABLE (0x148 >> 2)
131#define GPIO_UVWX_INT_SENS_0 (0x14C >> 2)
132#define GPIO_UVWX_INT_SENS_1 (0x150 >> 2)
133#define GPIO_UVWX_INT_SENS_2 (0x154 >> 2)
134#define GPIO_UVWX_INT_STATUS (0x158 >> 2)
135#define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2)
136#define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2)
137#define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2)
138#define GPIO_UVWX_INPUT_MASK (0x168 >> 2)
139#define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2)
140#define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2)
141#define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2)
142#define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2)
143#define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2)
144#define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2)
145#define GPIO_YZAAAB_INT_STATUS (0x188 >> 2)
146#define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2)
147#define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2)
148#define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2)
149#define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2)
150#define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2)
151#define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2)
152#define GPIO_AC_INT_ENABLE (0x1A8 >> 2)
153#define GPIO_AC_INT_SENS_0 (0x1AC >> 2)
154#define GPIO_AC_INT_SENS_1 (0x1B0 >> 2)
155#define GPIO_AC_INT_SENS_2 (0x1B4 >> 2)
156#define GPIO_AC_INT_STATUS (0x1B8 >> 2)
157#define GPIO_AC_RESET_TOLERANT (0x1BC >> 2)
158#define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2)
159#define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2)
160#define GPIO_AC_INPUT_MASK (0x1C8 >> 2)
161#define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2)
162#define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2)
163#define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2)
164#define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2)
165#define GPIO_AC_DATA_VALUE (0x1E8 >> 2)
166#define GPIO_AC_DIRECTION (0x1EC >> 2)
167#define GPIO_3_6V_MEM_SIZE 0x1F0
168#define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2)
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174
175#define GPIO_1_8V_REG_OFFSET 0x800
176#define GPIO_1_8V_ABCD_DATA_VALUE ((0x800 - GPIO_1_8V_REG_OFFSET) >> 2)
177#define GPIO_1_8V_ABCD_DIRECTION ((0x804 - GPIO_1_8V_REG_OFFSET) >> 2)
178#define GPIO_1_8V_ABCD_INT_ENABLE ((0x808 - GPIO_1_8V_REG_OFFSET) >> 2)
179#define GPIO_1_8V_ABCD_INT_SENS_0 ((0x80C - GPIO_1_8V_REG_OFFSET) >> 2)
180#define GPIO_1_8V_ABCD_INT_SENS_1 ((0x810 - GPIO_1_8V_REG_OFFSET) >> 2)
181#define GPIO_1_8V_ABCD_INT_SENS_2 ((0x814 - GPIO_1_8V_REG_OFFSET) >> 2)
182#define GPIO_1_8V_ABCD_INT_STATUS ((0x818 - GPIO_1_8V_REG_OFFSET) >> 2)
183#define GPIO_1_8V_ABCD_RESET_TOLERANT ((0x81C - GPIO_1_8V_REG_OFFSET) >> 2)
184#define GPIO_1_8V_E_DATA_VALUE ((0x820 - GPIO_1_8V_REG_OFFSET) >> 2)
185#define GPIO_1_8V_E_DIRECTION ((0x824 - GPIO_1_8V_REG_OFFSET) >> 2)
186#define GPIO_1_8V_E_INT_ENABLE ((0x828 - GPIO_1_8V_REG_OFFSET) >> 2)
187#define GPIO_1_8V_E_INT_SENS_0 ((0x82C - GPIO_1_8V_REG_OFFSET) >> 2)
188#define GPIO_1_8V_E_INT_SENS_1 ((0x830 - GPIO_1_8V_REG_OFFSET) >> 2)
189#define GPIO_1_8V_E_INT_SENS_2 ((0x834 - GPIO_1_8V_REG_OFFSET) >> 2)
190#define GPIO_1_8V_E_INT_STATUS ((0x838 - GPIO_1_8V_REG_OFFSET) >> 2)
191#define GPIO_1_8V_E_RESET_TOLERANT ((0x83C - GPIO_1_8V_REG_OFFSET) >> 2)
192#define GPIO_1_8V_ABCD_DEBOUNCE_1 ((0x840 - GPIO_1_8V_REG_OFFSET) >> 2)
193#define GPIO_1_8V_ABCD_DEBOUNCE_2 ((0x844 - GPIO_1_8V_REG_OFFSET) >> 2)
194#define GPIO_1_8V_E_DEBOUNCE_1 ((0x848 - GPIO_1_8V_REG_OFFSET) >> 2)
195#define GPIO_1_8V_E_DEBOUNCE_2 ((0x84C - GPIO_1_8V_REG_OFFSET) >> 2)
196#define GPIO_1_8V_DEBOUNCE_TIME_1 ((0x850 - GPIO_1_8V_REG_OFFSET) >> 2)
197#define GPIO_1_8V_DEBOUNCE_TIME_2 ((0x854 - GPIO_1_8V_REG_OFFSET) >> 2)
198#define GPIO_1_8V_DEBOUNCE_TIME_3 ((0x858 - GPIO_1_8V_REG_OFFSET) >> 2)
199#define GPIO_1_8V_ABCD_COMMAND_SRC_0 ((0x860 - GPIO_1_8V_REG_OFFSET) >> 2)
200#define GPIO_1_8V_ABCD_COMMAND_SRC_1 ((0x864 - GPIO_1_8V_REG_OFFSET) >> 2)
201#define GPIO_1_8V_E_COMMAND_SRC_0 ((0x868 - GPIO_1_8V_REG_OFFSET) >> 2)
202#define GPIO_1_8V_E_COMMAND_SRC_1 ((0x86C - GPIO_1_8V_REG_OFFSET) >> 2)
203#define GPIO_1_8V_ABCD_DATA_READ ((0x8C0 - GPIO_1_8V_REG_OFFSET) >> 2)
204#define GPIO_1_8V_E_DATA_READ ((0x8C4 - GPIO_1_8V_REG_OFFSET) >> 2)
205#define GPIO_1_8V_ABCD_INPUT_MASK ((0x9D0 - GPIO_1_8V_REG_OFFSET) >> 2)
206#define GPIO_1_8V_E_INPUT_MASK ((0x9D4 - GPIO_1_8V_REG_OFFSET) >> 2)
207#define GPIO_1_8V_MEM_SIZE 0x9D8
208#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \
209 GPIO_1_8V_REG_OFFSET) >> 2)
210
211static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)
212{
213 uint32_t falling_edge = 0, rising_edge = 0;
214 uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1)
215 | extract32(regs->int_sens_1, gpio, 1) << 1
216 | extract32(regs->int_sens_2, gpio, 1) << 2;
217 uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1);
218 uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1);
219
220 if (!gpio_int_enabled) {
221 return 0;
222 }
223
224
225 if (gpio_curr_high && !gpio_prev_high) {
226 rising_edge = 1;
227 } else if (!gpio_curr_high && gpio_prev_high) {
228 falling_edge = 1;
229 }
230
231 if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) ||
232 ((int_trigger == ASPEED_RISING_EDGE) && rising_edge) ||
233 ((int_trigger == ASPEED_LEVEL_LOW) && !gpio_curr_high) ||
234 ((int_trigger == ASPEED_LEVEL_HIGH) && gpio_curr_high) ||
235 ((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge)))
236 {
237 regs->int_status = deposit32(regs->int_status, gpio, 1, 1);
238 return 1;
239 }
240 return 0;
241}
242
243#define nested_struct_index(ta, pa, m, tb, pb) \
244 (pb - ((tb *)(((char *)pa) + offsetof(ta, m))))
245
246static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s, GPIOSets *regs)
247{
248 return nested_struct_index(AspeedGPIOState, s, sets, GPIOSets, regs);
249}
250
251static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs,
252 uint32_t value)
253{
254 uint32_t input_mask = regs->input_mask;
255 uint32_t direction = regs->direction;
256 uint32_t old = regs->data_value;
257 uint32_t new = value;
258 uint32_t diff;
259 int gpio;
260
261 diff = old ^ new;
262 if (diff) {
263 for (gpio = 0; gpio < GPIOS_PER_REG; gpio++) {
264 uint32_t mask = 1 << gpio;
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266
267 if (!(diff & mask)) {
268 continue;
269 }
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271
272 if (!(direction & mask) && (input_mask & mask)) {
273 continue;
274 }
275
276
277 if (mask & new) {
278 regs->data_value |= mask;
279 } else {
280 regs->data_value &= ~mask;
281 }
282
283
284 if (direction & mask) {
285
286 ptrdiff_t set = aspeed_gpio_set_idx(s, regs);
287 size_t offset = set * GPIOS_PER_SET + gpio;
288 qemu_set_irq(s->gpios[offset], !!(new & mask));
289 } else {
290
291 if (aspeed_evaluate_irq(regs, old & mask, gpio)) {
292
293 s->pending++;
294 }
295 }
296 }
297 }
298 qemu_set_irq(s->irq, !!(s->pending));
299}
300
301static uint32_t aspeed_adjust_pin(AspeedGPIOState *s, uint32_t pin)
302{
303 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
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309 if (agc->gap && pin >= agc->gap) {
310 pin += GPIO_PIN_GAP_SIZE;
311 }
312
313 return pin;
314}
315
316static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx,
317 uint32_t pin)
318{
319 uint32_t reg_val;
320 uint32_t pin_mask = 1 << pin;
321
322 reg_val = s->sets[set_idx].data_value;
323
324 return !!(reg_val & pin_mask);
325}
326
327static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx,
328 uint32_t pin, bool level)
329{
330 uint32_t value = s->sets[set_idx].data_value;
331 uint32_t pin_mask = 1 << pin;
332
333 if (level) {
334 value |= pin_mask;
335 } else {
336 value &= !pin_mask;
337 }
338
339 aspeed_gpio_update(s, &s->sets[set_idx], value);
340}
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358
359static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value,
360 uint32_t value)
361{
362 int i;
363 int cmd_source;
364
365
366 int source = ASPEED_SOURCE_ARM;
367
368 uint32_t new_value = 0;
369
370
371 for (i = 0; i < GPIOS_PER_REG; i += GPIOS_PER_GROUP) {
372 cmd_source = extract32(regs->cmd_source_0, i, 1)
373 | (extract32(regs->cmd_source_1, i, 1) << 1);
374
375 if (source == cmd_source) {
376 new_value |= (0xff << i) & value;
377 } else {
378 new_value |= (0xff << i) & old_value;
379 }
380 }
381 return new_value;
382}
383
384static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = {
385
386 [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value },
387 [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction },
388 [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable },
389 [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 },
390 [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 },
391 [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 },
392 [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status },
393 [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant },
394 [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 },
395 [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 },
396 [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 },
397 [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 },
398 [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read },
399 [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask },
400
401 [GPIO_EFGH_DATA_VALUE] = { 1, gpio_reg_data_value },
402 [GPIO_EFGH_DIRECTION] = { 1, gpio_reg_direction },
403 [GPIO_EFGH_INT_ENABLE] = { 1, gpio_reg_int_enable },
404 [GPIO_EFGH_INT_SENS_0] = { 1, gpio_reg_int_sens_0 },
405 [GPIO_EFGH_INT_SENS_1] = { 1, gpio_reg_int_sens_1 },
406 [GPIO_EFGH_INT_SENS_2] = { 1, gpio_reg_int_sens_2 },
407 [GPIO_EFGH_INT_STATUS] = { 1, gpio_reg_int_status },
408 [GPIO_EFGH_RESET_TOLERANT] = { 1, gpio_reg_reset_tolerant },
409 [GPIO_EFGH_DEBOUNCE_1] = { 1, gpio_reg_debounce_1 },
410 [GPIO_EFGH_DEBOUNCE_2] = { 1, gpio_reg_debounce_2 },
411 [GPIO_EFGH_COMMAND_SRC_0] = { 1, gpio_reg_cmd_source_0 },
412 [GPIO_EFGH_COMMAND_SRC_1] = { 1, gpio_reg_cmd_source_1 },
413 [GPIO_EFGH_DATA_READ] = { 1, gpio_reg_data_read },
414 [GPIO_EFGH_INPUT_MASK] = { 1, gpio_reg_input_mask },
415
416 [GPIO_IJKL_DATA_VALUE] = { 2, gpio_reg_data_value },
417 [GPIO_IJKL_DIRECTION] = { 2, gpio_reg_direction },
418 [GPIO_IJKL_INT_ENABLE] = { 2, gpio_reg_int_enable },
419 [GPIO_IJKL_INT_SENS_0] = { 2, gpio_reg_int_sens_0 },
420 [GPIO_IJKL_INT_SENS_1] = { 2, gpio_reg_int_sens_1 },
421 [GPIO_IJKL_INT_SENS_2] = { 2, gpio_reg_int_sens_2 },
422 [GPIO_IJKL_INT_STATUS] = { 2, gpio_reg_int_status },
423 [GPIO_IJKL_RESET_TOLERANT] = { 2, gpio_reg_reset_tolerant },
424 [GPIO_IJKL_DEBOUNCE_1] = { 2, gpio_reg_debounce_1 },
425 [GPIO_IJKL_DEBOUNCE_2] = { 2, gpio_reg_debounce_2 },
426 [GPIO_IJKL_COMMAND_SRC_0] = { 2, gpio_reg_cmd_source_0 },
427 [GPIO_IJKL_COMMAND_SRC_1] = { 2, gpio_reg_cmd_source_1 },
428 [GPIO_IJKL_DATA_READ] = { 2, gpio_reg_data_read },
429 [GPIO_IJKL_INPUT_MASK] = { 2, gpio_reg_input_mask },
430
431 [GPIO_MNOP_DATA_VALUE] = { 3, gpio_reg_data_value },
432 [GPIO_MNOP_DIRECTION] = { 3, gpio_reg_direction },
433 [GPIO_MNOP_INT_ENABLE] = { 3, gpio_reg_int_enable },
434 [GPIO_MNOP_INT_SENS_0] = { 3, gpio_reg_int_sens_0 },
435 [GPIO_MNOP_INT_SENS_1] = { 3, gpio_reg_int_sens_1 },
436 [GPIO_MNOP_INT_SENS_2] = { 3, gpio_reg_int_sens_2 },
437 [GPIO_MNOP_INT_STATUS] = { 3, gpio_reg_int_status },
438 [GPIO_MNOP_RESET_TOLERANT] = { 3, gpio_reg_reset_tolerant },
439 [GPIO_MNOP_DEBOUNCE_1] = { 3, gpio_reg_debounce_1 },
440 [GPIO_MNOP_DEBOUNCE_2] = { 3, gpio_reg_debounce_2 },
441 [GPIO_MNOP_COMMAND_SRC_0] = { 3, gpio_reg_cmd_source_0 },
442 [GPIO_MNOP_COMMAND_SRC_1] = { 3, gpio_reg_cmd_source_1 },
443 [GPIO_MNOP_DATA_READ] = { 3, gpio_reg_data_read },
444 [GPIO_MNOP_INPUT_MASK] = { 3, gpio_reg_input_mask },
445
446 [GPIO_QRST_DATA_VALUE] = { 4, gpio_reg_data_value },
447 [GPIO_QRST_DIRECTION] = { 4, gpio_reg_direction },
448 [GPIO_QRST_INT_ENABLE] = { 4, gpio_reg_int_enable },
449 [GPIO_QRST_INT_SENS_0] = { 4, gpio_reg_int_sens_0 },
450 [GPIO_QRST_INT_SENS_1] = { 4, gpio_reg_int_sens_1 },
451 [GPIO_QRST_INT_SENS_2] = { 4, gpio_reg_int_sens_2 },
452 [GPIO_QRST_INT_STATUS] = { 4, gpio_reg_int_status },
453 [GPIO_QRST_RESET_TOLERANT] = { 4, gpio_reg_reset_tolerant },
454 [GPIO_QRST_DEBOUNCE_1] = { 4, gpio_reg_debounce_1 },
455 [GPIO_QRST_DEBOUNCE_2] = { 4, gpio_reg_debounce_2 },
456 [GPIO_QRST_COMMAND_SRC_0] = { 4, gpio_reg_cmd_source_0 },
457 [GPIO_QRST_COMMAND_SRC_1] = { 4, gpio_reg_cmd_source_1 },
458 [GPIO_QRST_DATA_READ] = { 4, gpio_reg_data_read },
459 [GPIO_QRST_INPUT_MASK] = { 4, gpio_reg_input_mask },
460
461 [GPIO_UVWX_DATA_VALUE] = { 5, gpio_reg_data_value },
462 [GPIO_UVWX_DIRECTION] = { 5, gpio_reg_direction },
463 [GPIO_UVWX_INT_ENABLE] = { 5, gpio_reg_int_enable },
464 [GPIO_UVWX_INT_SENS_0] = { 5, gpio_reg_int_sens_0 },
465 [GPIO_UVWX_INT_SENS_1] = { 5, gpio_reg_int_sens_1 },
466 [GPIO_UVWX_INT_SENS_2] = { 5, gpio_reg_int_sens_2 },
467 [GPIO_UVWX_INT_STATUS] = { 5, gpio_reg_int_status },
468 [GPIO_UVWX_RESET_TOLERANT] = { 5, gpio_reg_reset_tolerant },
469 [GPIO_UVWX_DEBOUNCE_1] = { 5, gpio_reg_debounce_1 },
470 [GPIO_UVWX_DEBOUNCE_2] = { 5, gpio_reg_debounce_2 },
471 [GPIO_UVWX_COMMAND_SRC_0] = { 5, gpio_reg_cmd_source_0 },
472 [GPIO_UVWX_COMMAND_SRC_1] = { 5, gpio_reg_cmd_source_1 },
473 [GPIO_UVWX_DATA_READ] = { 5, gpio_reg_data_read },
474 [GPIO_UVWX_INPUT_MASK] = { 5, gpio_reg_input_mask },
475
476 [GPIO_YZAAAB_DATA_VALUE] = { 6, gpio_reg_data_value },
477 [GPIO_YZAAAB_DIRECTION] = { 6, gpio_reg_direction },
478 [GPIO_YZAAAB_INT_ENABLE] = { 6, gpio_reg_int_enable },
479 [GPIO_YZAAAB_INT_SENS_0] = { 6, gpio_reg_int_sens_0 },
480 [GPIO_YZAAAB_INT_SENS_1] = { 6, gpio_reg_int_sens_1 },
481 [GPIO_YZAAAB_INT_SENS_2] = { 6, gpio_reg_int_sens_2 },
482 [GPIO_YZAAAB_INT_STATUS] = { 6, gpio_reg_int_status },
483 [GPIO_YZAAAB_RESET_TOLERANT] = { 6, gpio_reg_reset_tolerant },
484 [GPIO_YZAAAB_DEBOUNCE_1] = { 6, gpio_reg_debounce_1 },
485 [GPIO_YZAAAB_DEBOUNCE_2] = { 6, gpio_reg_debounce_2 },
486 [GPIO_YZAAAB_COMMAND_SRC_0] = { 6, gpio_reg_cmd_source_0 },
487 [GPIO_YZAAAB_COMMAND_SRC_1] = { 6, gpio_reg_cmd_source_1 },
488 [GPIO_YZAAAB_DATA_READ] = { 6, gpio_reg_data_read },
489 [GPIO_YZAAAB_INPUT_MASK] = { 6, gpio_reg_input_mask },
490
491 [GPIO_AC_DATA_VALUE] = { 7, gpio_reg_data_value },
492 [GPIO_AC_DIRECTION] = { 7, gpio_reg_direction },
493 [GPIO_AC_INT_ENABLE] = { 7, gpio_reg_int_enable },
494 [GPIO_AC_INT_SENS_0] = { 7, gpio_reg_int_sens_0 },
495 [GPIO_AC_INT_SENS_1] = { 7, gpio_reg_int_sens_1 },
496 [GPIO_AC_INT_SENS_2] = { 7, gpio_reg_int_sens_2 },
497 [GPIO_AC_INT_STATUS] = { 7, gpio_reg_int_status },
498 [GPIO_AC_RESET_TOLERANT] = { 7, gpio_reg_reset_tolerant },
499 [GPIO_AC_DEBOUNCE_1] = { 7, gpio_reg_debounce_1 },
500 [GPIO_AC_DEBOUNCE_2] = { 7, gpio_reg_debounce_2 },
501 [GPIO_AC_COMMAND_SRC_0] = { 7, gpio_reg_cmd_source_0 },
502 [GPIO_AC_COMMAND_SRC_1] = { 7, gpio_reg_cmd_source_1 },
503 [GPIO_AC_DATA_READ] = { 7, gpio_reg_data_read },
504 [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask },
505};
506
507static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = {
508
509 [GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value},
510 [GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction},
511 [GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable},
512 [GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0},
513 [GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1},
514 [GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2},
515 [GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status},
516 [GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant},
517 [GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1},
518 [GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2},
519 [GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0},
520 [GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1},
521 [GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read},
522 [GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask},
523
524 [GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value},
525 [GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction},
526 [GPIO_1_8V_E_INT_ENABLE] = {1, gpio_reg_int_enable},
527 [GPIO_1_8V_E_INT_SENS_0] = {1, gpio_reg_int_sens_0},
528 [GPIO_1_8V_E_INT_SENS_1] = {1, gpio_reg_int_sens_1},
529 [GPIO_1_8V_E_INT_SENS_2] = {1, gpio_reg_int_sens_2},
530 [GPIO_1_8V_E_INT_STATUS] = {1, gpio_reg_int_status},
531 [GPIO_1_8V_E_RESET_TOLERANT] = {1, gpio_reg_reset_tolerant},
532 [GPIO_1_8V_E_DEBOUNCE_1] = {1, gpio_reg_debounce_1},
533 [GPIO_1_8V_E_DEBOUNCE_2] = {1, gpio_reg_debounce_2},
534 [GPIO_1_8V_E_COMMAND_SRC_0] = {1, gpio_reg_cmd_source_0},
535 [GPIO_1_8V_E_COMMAND_SRC_1] = {1, gpio_reg_cmd_source_1},
536 [GPIO_1_8V_E_DATA_READ] = {1, gpio_reg_data_read},
537 [GPIO_1_8V_E_INPUT_MASK] = {1, gpio_reg_input_mask},
538};
539
540static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)
541{
542 AspeedGPIOState *s = ASPEED_GPIO(opaque);
543 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
544 uint64_t idx = -1;
545 const AspeedGPIOReg *reg;
546 GPIOSets *set;
547
548 idx = offset >> 2;
549 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) {
550 idx -= GPIO_DEBOUNCE_TIME_1;
551 return (uint64_t) s->debounce_regs[idx];
552 }
553
554 reg = &agc->reg_table[idx];
555 if (reg->set_idx >= agc->nr_gpio_sets) {
556 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"
557 HWADDR_PRIx"\n", __func__, offset);
558 return 0;
559 }
560
561 set = &s->sets[reg->set_idx];
562 switch (reg->type) {
563 case gpio_reg_data_value:
564 return set->data_value;
565 case gpio_reg_direction:
566 return set->direction;
567 case gpio_reg_int_enable:
568 return set->int_enable;
569 case gpio_reg_int_sens_0:
570 return set->int_sens_0;
571 case gpio_reg_int_sens_1:
572 return set->int_sens_1;
573 case gpio_reg_int_sens_2:
574 return set->int_sens_2;
575 case gpio_reg_int_status:
576 return set->int_status;
577 case gpio_reg_reset_tolerant:
578 return set->reset_tol;
579 case gpio_reg_debounce_1:
580 return set->debounce_1;
581 case gpio_reg_debounce_2:
582 return set->debounce_2;
583 case gpio_reg_cmd_source_0:
584 return set->cmd_source_0;
585 case gpio_reg_cmd_source_1:
586 return set->cmd_source_1;
587 case gpio_reg_data_read:
588 return set->data_read;
589 case gpio_reg_input_mask:
590 return set->input_mask;
591 default:
592 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"
593 HWADDR_PRIx"\n", __func__, offset);
594 return 0;
595 };
596}
597
598static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,
599 uint32_t size)
600{
601 AspeedGPIOState *s = ASPEED_GPIO(opaque);
602 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
603 const GPIOSetProperties *props;
604 uint64_t idx = -1;
605 const AspeedGPIOReg *reg;
606 GPIOSets *set;
607 uint32_t cleared;
608
609 idx = offset >> 2;
610 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) {
611 idx -= GPIO_DEBOUNCE_TIME_1;
612 s->debounce_regs[idx] = (uint32_t) data;
613 return;
614 }
615
616 reg = &agc->reg_table[idx];
617 if (reg->set_idx >= agc->nr_gpio_sets) {
618 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"
619 HWADDR_PRIx"\n", __func__, offset);
620 return;
621 }
622
623 set = &s->sets[reg->set_idx];
624 props = &agc->props[reg->set_idx];
625
626 switch (reg->type) {
627 case gpio_reg_data_value:
628 data &= props->output;
629 data = update_value_control_source(set, set->data_value, data);
630 set->data_read = data;
631 aspeed_gpio_update(s, set, data);
632 return;
633 case gpio_reg_direction:
634
635
636
637
638
639
640
641
642
643
644
645
646 data = (data | ~props->input) & props->output;
647 set->direction = update_value_control_source(set, set->direction, data);
648 break;
649 case gpio_reg_int_enable:
650 set->int_enable = update_value_control_source(set, set->int_enable,
651 data);
652 break;
653 case gpio_reg_int_sens_0:
654 set->int_sens_0 = update_value_control_source(set, set->int_sens_0,
655 data);
656 break;
657 case gpio_reg_int_sens_1:
658 set->int_sens_1 = update_value_control_source(set, set->int_sens_1,
659 data);
660 break;
661 case gpio_reg_int_sens_2:
662 set->int_sens_2 = update_value_control_source(set, set->int_sens_2,
663 data);
664 break;
665 case gpio_reg_int_status:
666 cleared = ctpop32(data & set->int_status);
667 if (s->pending && cleared) {
668 assert(s->pending >= cleared);
669 s->pending -= cleared;
670 }
671 set->int_status &= ~data;
672 break;
673 case gpio_reg_reset_tolerant:
674 set->reset_tol = update_value_control_source(set, set->reset_tol,
675 data);
676 return;
677 case gpio_reg_debounce_1:
678 set->debounce_1 = update_value_control_source(set, set->debounce_1,
679 data);
680 return;
681 case gpio_reg_debounce_2:
682 set->debounce_2 = update_value_control_source(set, set->debounce_2,
683 data);
684 return;
685 case gpio_reg_cmd_source_0:
686 set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK;
687 return;
688 case gpio_reg_cmd_source_1:
689 set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK;
690 return;
691 case gpio_reg_data_read:
692
693 return;
694 case gpio_reg_input_mask:
695
696
697
698
699
700 set->input_mask = data & props->input;
701 break;
702 default:
703 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"
704 HWADDR_PRIx"\n", __func__, offset);
705 return;
706 }
707 aspeed_gpio_update(s, set, set->data_value);
708 return;
709}
710
711static int get_set_idx(AspeedGPIOState *s, const char *group, int *group_idx)
712{
713 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
714 int set_idx, g_idx;
715
716 for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) {
717 const GPIOSetProperties *set_props = &agc->props[set_idx];
718 for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) {
719 if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) {
720 *group_idx = g_idx;
721 return set_idx;
722 }
723 }
724 }
725 return -1;
726}
727
728static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name,
729 void *opaque, Error **errp)
730{
731 int pin = 0xfff;
732 bool level = true;
733 char group[4];
734 AspeedGPIOState *s = ASPEED_GPIO(obj);
735 int set_idx, group_idx = 0;
736
737 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) {
738
739 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) {
740 error_setg(errp, "%s: error reading %s", __func__, name);
741 return;
742 }
743 }
744 set_idx = get_set_idx(s, group, &group_idx);
745 if (set_idx == -1) {
746 error_setg(errp, "%s: invalid group %s", __func__, group);
747 return;
748 }
749 pin = pin + group_idx * GPIOS_PER_GROUP;
750 level = aspeed_gpio_get_pin_level(s, set_idx, pin);
751 visit_type_bool(v, name, &level, errp);
752}
753
754static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name,
755 void *opaque, Error **errp)
756{
757 bool level;
758 int pin = 0xfff;
759 char group[4];
760 AspeedGPIOState *s = ASPEED_GPIO(obj);
761 int set_idx, group_idx = 0;
762
763 if (!visit_type_bool(v, name, &level, errp)) {
764 return;
765 }
766 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) {
767
768 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) {
769 error_setg(errp, "%s: error reading %s", __func__, name);
770 return;
771 }
772 }
773 set_idx = get_set_idx(s, group, &group_idx);
774 if (set_idx == -1) {
775 error_setg(errp, "%s: invalid group %s", __func__, group);
776 return;
777 }
778 pin = pin + group_idx * GPIOS_PER_GROUP;
779 aspeed_gpio_set_pin_level(s, set_idx, pin, level);
780}
781
782
783static const GPIOSetProperties ast2400_set_props[] = {
784 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
785 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
786 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
787 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} },
788 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} },
789 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} },
790 [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} },
791};
792
793static const GPIOSetProperties ast2500_set_props[] = {
794 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
795 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
796 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
797 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} },
798 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} },
799 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} },
800 [6] = {0xffffff0f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} },
801 [7] = {0x000000ff, 0x000000ff, {"AC"} },
802};
803
804static GPIOSetProperties ast2600_3_6v_set_props[] = {
805 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
806 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
807 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
808 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} },
809 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} },
810 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} },
811 [6] = {0xffff0000, 0x0fff0000, {"Y", "Z", "", ""} },
812};
813
814static GPIOSetProperties ast2600_1_8v_set_props[] = {
815 [0] = {0xffffffff, 0xffffffff, {"18A", "18B", "18C", "18D"} },
816 [1] = {0x0000000f, 0x0000000f, {"18E"} },
817};
818
819static const MemoryRegionOps aspeed_gpio_ops = {
820 .read = aspeed_gpio_read,
821 .write = aspeed_gpio_write,
822 .endianness = DEVICE_LITTLE_ENDIAN,
823 .valid.min_access_size = 4,
824 .valid.max_access_size = 4,
825};
826
827static void aspeed_gpio_reset(DeviceState *dev)
828{
829 AspeedGPIOState *s = ASPEED_GPIO(dev);
830
831
832 memset(s->sets, 0, sizeof(s->sets));
833}
834
835static void aspeed_gpio_realize(DeviceState *dev, Error **errp)
836{
837 AspeedGPIOState *s = ASPEED_GPIO(dev);
838 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
839 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
840 int pin;
841
842
843 sysbus_init_irq(sbd, &s->irq);
844
845
846 for (pin = 0; pin < agc->nr_gpio_pins; pin++) {
847 sysbus_init_irq(sbd, &s->gpios[pin]);
848 }
849
850 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s,
851 TYPE_ASPEED_GPIO, 0x800);
852
853 sysbus_init_mmio(sbd, &s->iomem);
854}
855
856static void aspeed_gpio_init(Object *obj)
857{
858 AspeedGPIOState *s = ASPEED_GPIO(obj);
859 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
860 int pin;
861
862 for (pin = 0; pin < agc->nr_gpio_pins; pin++) {
863 char *name;
864 int set_idx = pin / GPIOS_PER_SET;
865 int pin_idx = aspeed_adjust_pin(s, pin) - (set_idx * GPIOS_PER_SET);
866 int group_idx = pin_idx >> GPIO_GROUP_SHIFT;
867 const GPIOSetProperties *props = &agc->props[set_idx];
868
869 name = g_strdup_printf("gpio%s%d", props->group_label[group_idx],
870 pin_idx % GPIOS_PER_GROUP);
871 object_property_add(obj, name, "bool", aspeed_gpio_get_pin,
872 aspeed_gpio_set_pin, NULL, NULL);
873 g_free(name);
874 }
875}
876
877static const VMStateDescription vmstate_gpio_regs = {
878 .name = TYPE_ASPEED_GPIO"/regs",
879 .version_id = 1,
880 .minimum_version_id = 1,
881 .fields = (VMStateField[]) {
882 VMSTATE_UINT32(data_value, GPIOSets),
883 VMSTATE_UINT32(data_read, GPIOSets),
884 VMSTATE_UINT32(direction, GPIOSets),
885 VMSTATE_UINT32(int_enable, GPIOSets),
886 VMSTATE_UINT32(int_sens_0, GPIOSets),
887 VMSTATE_UINT32(int_sens_1, GPIOSets),
888 VMSTATE_UINT32(int_sens_2, GPIOSets),
889 VMSTATE_UINT32(int_status, GPIOSets),
890 VMSTATE_UINT32(reset_tol, GPIOSets),
891 VMSTATE_UINT32(cmd_source_0, GPIOSets),
892 VMSTATE_UINT32(cmd_source_1, GPIOSets),
893 VMSTATE_UINT32(debounce_1, GPIOSets),
894 VMSTATE_UINT32(debounce_2, GPIOSets),
895 VMSTATE_UINT32(input_mask, GPIOSets),
896 VMSTATE_END_OF_LIST(),
897 }
898};
899
900static const VMStateDescription vmstate_aspeed_gpio = {
901 .name = TYPE_ASPEED_GPIO,
902 .version_id = 1,
903 .minimum_version_id = 1,
904 .fields = (VMStateField[]) {
905 VMSTATE_STRUCT_ARRAY(sets, AspeedGPIOState, ASPEED_GPIO_MAX_NR_SETS,
906 1, vmstate_gpio_regs, GPIOSets),
907 VMSTATE_UINT32_ARRAY(debounce_regs, AspeedGPIOState,
908 ASPEED_GPIO_NR_DEBOUNCE_REGS),
909 VMSTATE_END_OF_LIST(),
910 }
911};
912
913static void aspeed_gpio_class_init(ObjectClass *klass, void *data)
914{
915 DeviceClass *dc = DEVICE_CLASS(klass);
916
917 dc->realize = aspeed_gpio_realize;
918 dc->reset = aspeed_gpio_reset;
919 dc->desc = "Aspeed GPIO Controller";
920 dc->vmsd = &vmstate_aspeed_gpio;
921}
922
923static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data)
924{
925 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass);
926
927 agc->props = ast2400_set_props;
928 agc->nr_gpio_pins = 216;
929 agc->nr_gpio_sets = 7;
930 agc->gap = 196;
931 agc->reg_table = aspeed_3_6v_gpios;
932}
933
934static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data)
935{
936 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass);
937
938 agc->props = ast2500_set_props;
939 agc->nr_gpio_pins = 228;
940 agc->nr_gpio_sets = 8;
941 agc->gap = 220;
942 agc->reg_table = aspeed_3_6v_gpios;
943}
944
945static void aspeed_gpio_ast2600_3_6v_class_init(ObjectClass *klass, void *data)
946{
947 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass);
948
949 agc->props = ast2600_3_6v_set_props;
950 agc->nr_gpio_pins = 208;
951 agc->nr_gpio_sets = 7;
952 agc->reg_table = aspeed_3_6v_gpios;
953}
954
955static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data)
956{
957 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass);
958
959 agc->props = ast2600_1_8v_set_props;
960 agc->nr_gpio_pins = 36;
961 agc->nr_gpio_sets = 2;
962 agc->reg_table = aspeed_1_8v_gpios;
963}
964
965static const TypeInfo aspeed_gpio_info = {
966 .name = TYPE_ASPEED_GPIO,
967 .parent = TYPE_SYS_BUS_DEVICE,
968 .instance_size = sizeof(AspeedGPIOState),
969 .class_size = sizeof(AspeedGPIOClass),
970 .class_init = aspeed_gpio_class_init,
971 .abstract = true,
972};
973
974static const TypeInfo aspeed_gpio_ast2400_info = {
975 .name = TYPE_ASPEED_GPIO "-ast2400",
976 .parent = TYPE_ASPEED_GPIO,
977 .class_init = aspeed_gpio_ast2400_class_init,
978 .instance_init = aspeed_gpio_init,
979};
980
981static const TypeInfo aspeed_gpio_ast2500_info = {
982 .name = TYPE_ASPEED_GPIO "-ast2500",
983 .parent = TYPE_ASPEED_GPIO,
984 .class_init = aspeed_gpio_2500_class_init,
985 .instance_init = aspeed_gpio_init,
986};
987
988static const TypeInfo aspeed_gpio_ast2600_3_6v_info = {
989 .name = TYPE_ASPEED_GPIO "-ast2600",
990 .parent = TYPE_ASPEED_GPIO,
991 .class_init = aspeed_gpio_ast2600_3_6v_class_init,
992 .instance_init = aspeed_gpio_init,
993};
994
995static const TypeInfo aspeed_gpio_ast2600_1_8v_info = {
996 .name = TYPE_ASPEED_GPIO "-ast2600-1_8v",
997 .parent = TYPE_ASPEED_GPIO,
998 .class_init = aspeed_gpio_ast2600_1_8v_class_init,
999 .instance_init = aspeed_gpio_init,
1000};
1001
1002static void aspeed_gpio_register_types(void)
1003{
1004 type_register_static(&aspeed_gpio_info);
1005 type_register_static(&aspeed_gpio_ast2400_info);
1006 type_register_static(&aspeed_gpio_ast2500_info);
1007 type_register_static(&aspeed_gpio_ast2600_3_6v_info);
1008 type_register_static(&aspeed_gpio_ast2600_1_8v_info);
1009}
1010
1011type_init(aspeed_gpio_register_types);
1012
