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21#include "qemu/osdep.h"
22#include "hw/riscv/opentitan.h"
23#include "qapi/error.h"
24#include "hw/boards.h"
25#include "hw/misc/unimp.h"
26#include "hw/riscv/boot.h"
27#include "qemu/units.h"
28#include "sysemu/sysemu.h"
29
30static const MemMapEntry ibex_memmap[] = {
31 [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
32 [IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
33 [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
34 [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
35 [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
36 [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
37 [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
38 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
39 [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
40 [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
41 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
42 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
43 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
44 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
45 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
46 [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
47 [IBEX_DEV_USBDEV] = { 0x40500000, 0x1000 },
48 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
49 [IBEX_DEV_PLIC] = { 0x41010000, 0x1000 },
50 [IBEX_DEV_AES] = { 0x41100000, 0x1000 },
51 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
52 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
53 [IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 },
54 [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
55 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
56 [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
57 [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
58 [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
59 [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
60 [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
61 [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
62 [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
63};
64
65static void opentitan_board_init(MachineState *machine)
66{
67 const MemMapEntry *memmap = ibex_memmap;
68 OpenTitanState *s = g_new0(OpenTitanState, 1);
69 MemoryRegion *sys_mem = get_system_memory();
70 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
71
72
73 object_initialize_child(OBJECT(machine), "soc", &s->soc,
74 TYPE_RISCV_IBEX_SOC);
75 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
76
77 memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
78 memmap[IBEX_DEV_RAM].size, &error_fatal);
79 memory_region_add_subregion(sys_mem,
80 memmap[IBEX_DEV_RAM].base, main_mem);
81
82 if (machine->firmware) {
83 riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
84 }
85
86 if (machine->kernel_filename) {
87 riscv_load_kernel(machine->kernel_filename,
88 memmap[IBEX_DEV_RAM].base, NULL);
89 }
90}
91
92static void opentitan_machine_init(MachineClass *mc)
93{
94 mc->desc = "RISC-V Board compatible with OpenTitan";
95 mc->init = opentitan_board_init;
96 mc->max_cpus = 1;
97 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
98}
99
100DEFINE_MACHINE("opentitan", opentitan_machine_init)
101
102static void lowrisc_ibex_soc_init(Object *obj)
103{
104 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
105
106 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
107
108 object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
109
110 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
111
112 object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
113}
114
115static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
116{
117 const MemMapEntry *memmap = ibex_memmap;
118 MachineState *ms = MACHINE(qdev_get_machine());
119 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
120 MemoryRegion *sys_mem = get_system_memory();
121
122 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
123 &error_abort);
124 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
125 &error_abort);
126 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
127 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
128
129
130 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
131 memmap[IBEX_DEV_ROM].size, &error_fatal);
132 memory_region_add_subregion(sys_mem,
133 memmap[IBEX_DEV_ROM].base, &s->rom);
134
135
136 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
137 memmap[IBEX_DEV_FLASH].size, &error_fatal);
138 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
139 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
140 memmap[IBEX_DEV_FLASH_VIRTUAL].size);
141 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
142 &s->flash_mem);
143 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
144 &s->flash_alias);
145
146
147 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
148 return;
149 }
150 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
151
152
153 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
154 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
155 return;
156 }
157 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
158 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
159 0, qdev_get_gpio_in(DEVICE(&s->plic),
160 IBEX_UART0_TX_WATERMARK_IRQ));
161 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
162 1, qdev_get_gpio_in(DEVICE(&s->plic),
163 IBEX_UART0_RX_WATERMARK_IRQ));
164 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
165 2, qdev_get_gpio_in(DEVICE(&s->plic),
166 IBEX_UART0_TX_EMPTY_IRQ));
167 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
168 3, qdev_get_gpio_in(DEVICE(&s->plic),
169 IBEX_UART0_RX_OVERFLOW_IRQ));
170
171 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
172 return;
173 }
174 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
175 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
176 0, qdev_get_gpio_in(DEVICE(&s->plic),
177 IBEX_TIMER_TIMEREXPIRED0_0));
178
179 create_unimplemented_device("riscv.lowrisc.ibex.gpio",
180 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
181 create_unimplemented_device("riscv.lowrisc.ibex.spi",
182 memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
183 create_unimplemented_device("riscv.lowrisc.ibex.i2c",
184 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
185 create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
186 memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
187 create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
188 memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
189 create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
190 memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
191 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
192 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
193 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
194 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
195 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
196 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
197 create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
198 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
199 create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
200 memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
201 create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
202 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
203 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
204 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
205 create_unimplemented_device("riscv.lowrisc.ibex.aes",
206 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
207 create_unimplemented_device("riscv.lowrisc.ibex.hmac",
208 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
209 create_unimplemented_device("riscv.lowrisc.ibex.kmac",
210 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
211 create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
212 memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
213 create_unimplemented_device("riscv.lowrisc.ibex.csrng",
214 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
215 create_unimplemented_device("riscv.lowrisc.ibex.entropy",
216 memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
217 create_unimplemented_device("riscv.lowrisc.ibex.edn0",
218 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
219 create_unimplemented_device("riscv.lowrisc.ibex.edn1",
220 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
221 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
222 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
223 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
224 memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
225 create_unimplemented_device("riscv.lowrisc.ibex.otbn",
226 memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
227 create_unimplemented_device("riscv.lowrisc.ibex.peri",
228 memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
229}
230
231static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
232{
233 DeviceClass *dc = DEVICE_CLASS(oc);
234
235 dc->realize = lowrisc_ibex_soc_realize;
236
237 dc->user_creatable = false;
238}
239
240static const TypeInfo lowrisc_ibex_soc_type_info = {
241 .name = TYPE_RISCV_IBEX_SOC,
242 .parent = TYPE_DEVICE,
243 .instance_size = sizeof(LowRISCIbexSoCState),
244 .instance_init = lowrisc_ibex_soc_init,
245 .class_init = lowrisc_ibex_soc_class_init,
246};
247
248static void lowrisc_ibex_soc_register_types(void)
249{
250 type_register_static(&lowrisc_ibex_soc_type_info);
251}
252
253type_init(lowrisc_ibex_soc_register_types)
254
