LXR qemu/include/hw/i2c/aspeed

   1/*
   2 *  ASPEED AST2400 I2C Controller
   3 *
   4 *  Copyright (C) 2016 IBM Corp.
   5 *
   6 *  This program is free software; you can redistribute it and/or modify
   7 *  it under the terms of the GNU General Public License as published by
   8 *  the Free Software Foundation; either version 2 of the License, or
   9 *  (at your option) any later version.
  10 *
  11 *  This program is distributed in the hope that it will be useful,
  12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 *  GNU General Public License for more details.
  15 *
  16 *  You should have received a copy of the GNU General Public License along
  17 *  with this program; if not, write to the Free Software Foundation, Inc.,
  18 *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19 */
  20
  21#ifndef ASPEED_I2C_H
  22#define ASPEED_I2C_H
  23
  24#include "hw/i2c/i2c.h"
  25#include "hw/sysbus.h"
  26#include "qom/object.h"
  27
  28#define TYPE_ASPEED_I2C "aspeed.i2c"
  29#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
  30#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
  31#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
  32OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
  33
  34#define ASPEED_I2C_NR_BUSSES 16
  35#define ASPEED_I2C_MAX_POOL_SIZE 0x800
  36
  37struct AspeedI2CState;
  38
  39typedef struct AspeedI2CBus {
  40    struct AspeedI2CState *controller;
  41
  42    MemoryRegion mr;
  43
  44    I2CBus *bus;
  45    uint8_t id;
  46    qemu_irq irq;
  47
  48    uint32_t ctrl;
  49    uint32_t timing[2];
  50    uint32_t intr_ctrl;
  51    uint32_t intr_status;
  52    uint32_t cmd;
  53    uint32_t buf;
  54    uint32_t pool_ctrl;
  55    uint32_t dma_addr;
  56    uint32_t dma_len;
  57} AspeedI2CBus;
  58
  59struct AspeedI2CState {
  60    SysBusDevice parent_obj;
  61
  62    MemoryRegion iomem;
  63    qemu_irq irq;
  64
  65    uint32_t intr_status;
  66    uint32_t ctrl_global;
  67    MemoryRegion pool_iomem;
  68    uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
  69
  70    AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
  71    MemoryRegion *dram_mr;
  72    AddressSpace dram_as;
  73};
  74
  75
  76struct AspeedI2CClass {
  77    SysBusDeviceClass parent_class;
  78
  79    uint8_t num_busses;
  80    uint8_t reg_size;
  81    uint8_t gap;
  82    qemu_irq (*bus_get_irq)(AspeedI2CBus *);
  83
  84    uint64_t pool_size;
  85    hwaddr pool_base;
  86    uint8_t *(*bus_pool_base)(AspeedI2CBus *);
  87    bool check_sram;
  88    bool has_dma;
  89
  90};
  91
  92I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr);
  93
  94#endif /* ASPEED_I2C_H */
  95