LXR qemu/include/hw/misc/allwinner-h3-dramc.h

   1/*
   2 * Allwinner H3 SDRAM Controller emulation
   3 *
   4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
   5 *
   6 * This program is free software: you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation, either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
  21#define HW_MISC_ALLWINNER_H3_DRAMC_H
  22
  23#include "qom/object.h"
  24#include "hw/sysbus.h"
  25#include "exec/hwaddr.h"
  26
  27/**
  28 * Constants
  29 * @{
  30 */
  31
  32/** Highest register address used by DRAMCOM module */
  33#define AW_H3_DRAMCOM_REGS_MAXADDR  (0x804)
  34
  35/** Total number of known DRAMCOM registers */
  36#define AW_H3_DRAMCOM_REGS_NUM      (AW_H3_DRAMCOM_REGS_MAXADDR / \
  37                                     sizeof(uint32_t))
  38
  39/** Highest register address used by DRAMCTL module */
  40#define AW_H3_DRAMCTL_REGS_MAXADDR  (0x88c)
  41
  42/** Total number of known DRAMCTL registers */
  43#define AW_H3_DRAMCTL_REGS_NUM      (AW_H3_DRAMCTL_REGS_MAXADDR / \
  44                                     sizeof(uint32_t))
  45
  46/** Highest register address used by DRAMPHY module */
  47#define AW_H3_DRAMPHY_REGS_MAXADDR  (0x4)
  48
  49/** Total number of known DRAMPHY registers */
  50#define AW_H3_DRAMPHY_REGS_NUM      (AW_H3_DRAMPHY_REGS_MAXADDR / \
  51                                     sizeof(uint32_t))
  52
  53/** @} */
  54
  55/**
  56 * Object model
  57 * @{
  58 */
  59
  60#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
  61OBJECT_DECLARE_SIMPLE_TYPE(AwH3DramCtlState, AW_H3_DRAMC)
  62
  63/** @} */
  64
  65/**
  66 * Allwinner H3 SDRAM Controller object instance state.
  67 */
  68struct AwH3DramCtlState {
  69    /*< private >*/
  70    SysBusDevice parent_obj;
  71    /*< public >*/
  72
  73    /** Physical base address for start of RAM */
  74    hwaddr ram_addr;
  75
  76    /** Total RAM size in megabytes */
  77    uint32_t ram_size;
  78
  79    /**
  80     * @name Memory Regions
  81     * @{
  82     */
  83
  84    MemoryRegion row_mirror;       /**< Simulates rows for RAM size detection */
  85    MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
  86    MemoryRegion dramcom_iomem;    /**< DRAMCOM module I/O registers */
  87    MemoryRegion dramctl_iomem;    /**< DRAMCTL module I/O registers */
  88    MemoryRegion dramphy_iomem;    /**< DRAMPHY module I/O registers */
  89
  90    /** @} */
  91
  92    /**
  93     * @name Hardware Registers
  94     * @{
  95     */
  96
  97    uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
  98    uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
  99    uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
 100
 101    /** @} */
 102
 103};
 104
 105#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
 106