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10#ifndef DMA_H
11#define DMA_H
12
13#include "exec/memory.h"
14#include "exec/address-spaces.h"
15#include "block/block.h"
16#include "block/accounting.h"
17
18typedef struct ScatterGatherEntry ScatterGatherEntry;
19
20typedef enum {
21 DMA_DIRECTION_TO_DEVICE = 0,
22 DMA_DIRECTION_FROM_DEVICE = 1,
23} DMADirection;
24
25struct QEMUSGList {
26 ScatterGatherEntry *sg;
27 int nsg;
28 int nalloc;
29 size_t size;
30 DeviceState *dev;
31 AddressSpace *as;
32};
33
34#ifndef CONFIG_USER_ONLY
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43typedef uint64_t dma_addr_t;
44
45#define DMA_ADDR_BITS 64
46#define DMA_ADDR_FMT "%" PRIx64
47
48static inline void dma_barrier(AddressSpace *as, DMADirection dir)
49{
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68 smp_mb();
69}
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74static inline bool dma_memory_valid(AddressSpace *as,
75 dma_addr_t addr, dma_addr_t len,
76 DMADirection dir)
77{
78 return address_space_access_valid(as, addr, len,
79 dir == DMA_DIRECTION_FROM_DEVICE,
80 MEMTXATTRS_UNSPECIFIED);
81}
82
83static inline MemTxResult dma_memory_rw_relaxed(AddressSpace *as,
84 dma_addr_t addr,
85 void *buf, dma_addr_t len,
86 DMADirection dir)
87{
88 return address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
89 buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
90}
91
92static inline MemTxResult dma_memory_read_relaxed(AddressSpace *as,
93 dma_addr_t addr,
94 void *buf, dma_addr_t len)
95{
96 return dma_memory_rw_relaxed(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
97}
98
99static inline MemTxResult dma_memory_write_relaxed(AddressSpace *as,
100 dma_addr_t addr,
101 const void *buf,
102 dma_addr_t len)
103{
104 return dma_memory_rw_relaxed(as, addr, (void *)buf, len,
105 DMA_DIRECTION_FROM_DEVICE);
106}
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121static inline MemTxResult dma_memory_rw(AddressSpace *as, dma_addr_t addr,
122 void *buf, dma_addr_t len,
123 DMADirection dir)
124{
125 dma_barrier(as, dir);
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127 return dma_memory_rw_relaxed(as, addr, buf, len, dir);
128}
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142static inline MemTxResult dma_memory_read(AddressSpace *as, dma_addr_t addr,
143 void *buf, dma_addr_t len)
144{
145 return dma_memory_rw(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
146}
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160static inline MemTxResult dma_memory_write(AddressSpace *as, dma_addr_t addr,
161 const void *buf, dma_addr_t len)
162{
163 return dma_memory_rw(as, addr, (void *)buf, len,
164 DMA_DIRECTION_FROM_DEVICE);
165}
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179MemTxResult dma_memory_set(AddressSpace *as, dma_addr_t addr,
180 uint8_t c, dma_addr_t len);
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195static inline void *dma_memory_map(AddressSpace *as,
196 dma_addr_t addr, dma_addr_t *len,
197 DMADirection dir)
198{
199 hwaddr xlen = *len;
200 void *p;
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202 p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
203 MEMTXATTRS_UNSPECIFIED);
204 *len = xlen;
205 return p;
206}
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222static inline void dma_memory_unmap(AddressSpace *as,
223 void *buffer, dma_addr_t len,
224 DMADirection dir, dma_addr_t access_len)
225{
226 address_space_unmap(as, buffer, (hwaddr)len,
227 dir == DMA_DIRECTION_FROM_DEVICE, access_len);
228}
229
230#define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \
231 static inline uint##_bits##_t ld##_lname##_##_end##_dma(AddressSpace *as, \
232 dma_addr_t addr) \
233 { \
234 uint##_bits##_t val; \
235 dma_memory_read(as, addr, &val, (_bits) / 8); \
236 return _end##_bits##_to_cpu(val); \
237 } \
238 static inline void st##_sname##_##_end##_dma(AddressSpace *as, \
239 dma_addr_t addr, \
240 uint##_bits##_t val) \
241 { \
242 val = cpu_to_##_end##_bits(val); \
243 dma_memory_write(as, addr, &val, (_bits) / 8); \
244 }
245
246static inline uint8_t ldub_dma(AddressSpace *as, dma_addr_t addr)
247{
248 uint8_t val;
249
250 dma_memory_read(as, addr, &val, 1);
251 return val;
252}
253
254static inline void stb_dma(AddressSpace *as, dma_addr_t addr, uint8_t val)
255{
256 dma_memory_write(as, addr, &val, 1);
257}
258
259DEFINE_LDST_DMA(uw, w, 16, le);
260DEFINE_LDST_DMA(l, l, 32, le);
261DEFINE_LDST_DMA(q, q, 64, le);
262DEFINE_LDST_DMA(uw, w, 16, be);
263DEFINE_LDST_DMA(l, l, 32, be);
264DEFINE_LDST_DMA(q, q, 64, be);
265
266#undef DEFINE_LDST_DMA
267
268struct ScatterGatherEntry {
269 dma_addr_t base;
270 dma_addr_t len;
271};
272
273void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
274 AddressSpace *as);
275void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len);
276void qemu_sglist_destroy(QEMUSGList *qsg);
277#endif
278
279typedef BlockAIOCB *DMAIOFunc(int64_t offset, QEMUIOVector *iov,
280 BlockCompletionFunc *cb, void *cb_opaque,
281 void *opaque);
282
283BlockAIOCB *dma_blk_io(AioContext *ctx,
284 QEMUSGList *sg, uint64_t offset, uint32_t align,
285 DMAIOFunc *io_func, void *io_func_opaque,
286 BlockCompletionFunc *cb, void *opaque, DMADirection dir);
287BlockAIOCB *dma_blk_read(BlockBackend *blk,
288 QEMUSGList *sg, uint64_t offset, uint32_t align,
289 BlockCompletionFunc *cb, void *opaque);
290BlockAIOCB *dma_blk_write(BlockBackend *blk,
291 QEMUSGList *sg, uint64_t offset, uint32_t align,
292 BlockCompletionFunc *cb, void *opaque);
293uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg);
294uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg);
295
296void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
297 QEMUSGList *sg, enum BlockAcctType type);
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308uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end,
309 int max_addr_bits);
310
311#endif
312