1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "hw/registerfields.h"
25#include "cpu-qom.h"
26#include "exec/cpu-defs.h"
27#include "qapi/qapi-types-common.h"
28
29
30#define TCG_GUEST_DEFAULT_MO (0)
31
32#ifdef TARGET_AARCH64
33#define KVM_HAVE_MCE_INJECTION 1
34#endif
35
36#define EXCP_UDEF 1
37#define EXCP_SWI 2
38#define EXCP_PREFETCH_ABORT 3
39#define EXCP_DATA_ABORT 4
40#define EXCP_IRQ 5
41#define EXCP_FIQ 6
42#define EXCP_BKPT 7
43#define EXCP_EXCEPTION_EXIT 8
44#define EXCP_KERNEL_TRAP 9
45#define EXCP_HVC 11
46#define EXCP_HYP_TRAP 12
47#define EXCP_SMC 13
48#define EXCP_VIRQ 14
49#define EXCP_VFIQ 15
50#define EXCP_SEMIHOST 16
51#define EXCP_NOCP 17
52#define EXCP_INVSTATE 18
53#define EXCP_STKOF 19
54#define EXCP_LAZYFP 20
55#define EXCP_LSERR 21
56#define EXCP_UNALIGNED 22
57
58
59#define ARMV7M_EXCP_RESET 1
60#define ARMV7M_EXCP_NMI 2
61#define ARMV7M_EXCP_HARD 3
62#define ARMV7M_EXCP_MEM 4
63#define ARMV7M_EXCP_BUS 5
64#define ARMV7M_EXCP_USAGE 6
65#define ARMV7M_EXCP_SECURE 7
66#define ARMV7M_EXCP_SVC 11
67#define ARMV7M_EXCP_DEBUG 12
68#define ARMV7M_EXCP_PENDSV 14
69#define ARMV7M_EXCP_SYSTICK 15
70
71
72
73
74
75
76
77
78
79
80enum {
81 M_REG_NS = 0,
82 M_REG_S = 1,
83 M_REG_NUM_BANKS = 2,
84};
85
86
87#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
88#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
89#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
90
91
92
93
94
95
96
97#ifdef HOST_WORDS_BIGENDIAN
98#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
99#define offsetofhigh32(S, M) offsetof(S, M)
100#else
101#define offsetoflow32(S, M) offsetof(S, M)
102#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
103#endif
104
105
106#define ARM_CPU_IRQ 0
107#define ARM_CPU_FIQ 1
108#define ARM_CPU_VIRQ 2
109#define ARM_CPU_VFIQ 3
110
111
112
113
114
115#define TARGET_INSN_START_EXTRA_WORDS 2
116
117
118
119
120
121
122#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
123#define ARM_INSN_START_WORD2_SHIFT 14
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142typedef struct DynamicGDBXMLInfo {
143 char *desc;
144 int num;
145 union {
146 struct {
147 uint32_t *keys;
148 } cpregs;
149 } data;
150} DynamicGDBXMLInfo;
151
152
153typedef struct ARMGenericTimer {
154 uint64_t cval;
155 uint64_t ctl;
156} ARMGenericTimer;
157
158#define GTIMER_PHYS 0
159#define GTIMER_VIRT 1
160#define GTIMER_HYP 2
161#define GTIMER_SEC 3
162#define GTIMER_HYPVIRT 4
163#define NUM_GTIMERS 5
164
165typedef struct {
166 uint64_t raw_tcr;
167 uint32_t mask;
168 uint32_t base_mask;
169} TCR;
170
171#define VTCR_NSW (1u << 29)
172#define VTCR_NSA (1u << 30)
173#define VSTCR_SW VTCR_NSW
174#define VSTCR_SA VTCR_NSA
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202#ifdef TARGET_AARCH64
203# define ARM_MAX_VQ 16
204void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
205void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
206#else
207# define ARM_MAX_VQ 1
208static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
209static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { }
210#endif
211
212typedef struct ARMVectorReg {
213 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
214} ARMVectorReg;
215
216#ifdef TARGET_AARCH64
217
218typedef struct ARMPredicateReg {
219 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
220} ARMPredicateReg;
221
222
223typedef struct ARMPACKey {
224 uint64_t lo, hi;
225} ARMPACKey;
226#endif
227
228
229typedef struct CPUARMTBFlags {
230 uint32_t flags;
231 target_ulong flags2;
232} CPUARMTBFlags;
233
234typedef struct CPUARMState {
235
236 uint32_t regs[16];
237
238
239
240
241
242
243 uint64_t xregs[32];
244 uint64_t pc;
245
246
247
248
249
250
251
252
253
254
255
256
257 uint32_t pstate;
258 uint32_t aarch64;
259
260
261 CPUARMTBFlags hflags;
262
263
264
265
266 uint32_t uncached_cpsr;
267 uint32_t spsr;
268
269
270 uint64_t banked_spsr[8];
271 uint32_t banked_r13[8];
272 uint32_t banked_r14[8];
273
274
275 uint32_t usr_regs[5];
276 uint32_t fiq_regs[5];
277
278
279 uint32_t CF;
280 uint32_t VF;
281 uint32_t NF;
282 uint32_t ZF;
283 uint32_t QF;
284 uint32_t GE;
285 uint32_t thumb;
286 uint32_t condexec_bits;
287 uint32_t btype;
288 uint64_t daif;
289
290 uint64_t elr_el[4];
291 uint64_t sp_el[4];
292
293
294 struct {
295 uint32_t c0_cpuid;
296 union {
297 struct {
298 uint64_t _unused_csselr0;
299 uint64_t csselr_ns;
300 uint64_t _unused_csselr1;
301 uint64_t csselr_s;
302 };
303 uint64_t csselr_el[4];
304 };
305 union {
306 struct {
307 uint64_t _unused_sctlr;
308 uint64_t sctlr_ns;
309 uint64_t hsctlr;
310 uint64_t sctlr_s;
311 };
312 uint64_t sctlr_el[4];
313 };
314 uint64_t cpacr_el1;
315 uint64_t cptr_el[4];
316 uint32_t c1_xscaleauxcr;
317 uint64_t sder;
318 uint32_t nsacr;
319 union {
320 struct {
321 uint64_t _unused_ttbr0_0;
322 uint64_t ttbr0_ns;
323 uint64_t _unused_ttbr0_1;
324 uint64_t ttbr0_s;
325 };
326 uint64_t ttbr0_el[4];
327 };
328 union {
329 struct {
330 uint64_t _unused_ttbr1_0;
331 uint64_t ttbr1_ns;
332 uint64_t _unused_ttbr1_1;
333 uint64_t ttbr1_s;
334 };
335 uint64_t ttbr1_el[4];
336 };
337 uint64_t vttbr_el2;
338 uint64_t vsttbr_el2;
339
340 TCR tcr_el[4];
341 TCR vtcr_el2;
342 TCR vstcr_el2;
343 uint32_t c2_data;
344 uint32_t c2_insn;
345 union {
346
347
348 struct {
349 uint64_t dacr_ns;
350 uint64_t dacr_s;
351 };
352 struct {
353 uint64_t dacr32_el2;
354 };
355 };
356 uint32_t pmsav5_data_ap;
357 uint32_t pmsav5_insn_ap;
358 uint64_t hcr_el2;
359 uint64_t scr_el3;
360 union {
361 struct {
362 uint64_t ifsr_ns;
363 uint64_t ifsr_s;
364 };
365 struct {
366 uint64_t ifsr32_el2;
367 };
368 };
369 union {
370 struct {
371 uint64_t _unused_dfsr;
372 uint64_t dfsr_ns;
373 uint64_t hsr;
374 uint64_t dfsr_s;
375 };
376 uint64_t esr_el[4];
377 };
378 uint32_t c6_region[8];
379 union {
380 struct {
381 uint64_t _unused_far0;
382#ifdef HOST_WORDS_BIGENDIAN
383 uint32_t ifar_ns;
384 uint32_t dfar_ns;
385 uint32_t ifar_s;
386 uint32_t dfar_s;
387#else
388 uint32_t dfar_ns;
389 uint32_t ifar_ns;
390 uint32_t dfar_s;
391 uint32_t ifar_s;
392#endif
393 uint64_t _unused_far3;
394 };
395 uint64_t far_el[4];
396 };
397 uint64_t hpfar_el2;
398 uint64_t hstr_el2;
399 union {
400 struct {
401 uint64_t _unused_par_0;
402 uint64_t par_ns;
403 uint64_t _unused_par_1;
404 uint64_t par_s;
405 };
406 uint64_t par_el[4];
407 };
408
409 uint32_t c9_insn;
410 uint32_t c9_data;
411 uint64_t c9_pmcr;
412 uint64_t c9_pmcnten;
413 uint64_t c9_pmovsr;
414 uint64_t c9_pmuserenr;
415 uint64_t c9_pmselr;
416 uint64_t c9_pminten;
417 union {
418 struct {
419#ifdef HOST_WORDS_BIGENDIAN
420 uint64_t _unused_mair_0;
421 uint32_t mair1_ns;
422 uint32_t mair0_ns;
423 uint64_t _unused_mair_1;
424 uint32_t mair1_s;
425 uint32_t mair0_s;
426#else
427 uint64_t _unused_mair_0;
428 uint32_t mair0_ns;
429 uint32_t mair1_ns;
430 uint64_t _unused_mair_1;
431 uint32_t mair0_s;
432 uint32_t mair1_s;
433#endif
434 };
435 uint64_t mair_el[4];
436 };
437 union {
438 struct {
439 uint64_t _unused_vbar;
440 uint64_t vbar_ns;
441 uint64_t hvbar;
442 uint64_t vbar_s;
443 };
444 uint64_t vbar_el[4];
445 };
446 uint32_t mvbar;
447 struct {
448 uint32_t fcseidr_ns;
449 uint32_t fcseidr_s;
450 };
451 union {
452 struct {
453 uint64_t _unused_contextidr_0;
454 uint64_t contextidr_ns;
455 uint64_t _unused_contextidr_1;
456 uint64_t contextidr_s;
457 };
458 uint64_t contextidr_el[4];
459 };
460 union {
461 struct {
462 uint64_t tpidrurw_ns;
463 uint64_t tpidrprw_ns;
464 uint64_t htpidr;
465 uint64_t _tpidr_el3;
466 };
467 uint64_t tpidr_el[4];
468 };
469
470 uint64_t tpidrurw_s;
471 uint64_t tpidrprw_s;
472 uint64_t tpidruro_s;
473
474 union {
475 uint64_t tpidruro_ns;
476 uint64_t tpidrro_el[1];
477 };
478 uint64_t c14_cntfrq;
479 uint64_t c14_cntkctl;
480 uint32_t cnthctl_el2;
481 uint64_t cntvoff_el2;
482 ARMGenericTimer c14_timer[NUM_GTIMERS];
483 uint32_t c15_cpar;
484 uint32_t c15_ticonfig;
485 uint32_t c15_i_max;
486 uint32_t c15_i_min;
487 uint32_t c15_threadid;
488 uint32_t c15_config_base_address;
489 uint32_t c15_diagnostic;
490 uint32_t c15_power_diagnostic;
491 uint32_t c15_power_control;
492 uint64_t dbgbvr[16];
493 uint64_t dbgbcr[16];
494 uint64_t dbgwvr[16];
495 uint64_t dbgwcr[16];
496 uint64_t mdscr_el1;
497 uint64_t oslsr_el1;
498 uint64_t mdcr_el2;
499 uint64_t mdcr_el3;
500
501
502
503
504
505 uint64_t c15_ccnt;
506
507
508
509
510
511
512
513 uint64_t c15_ccnt_delta;
514 uint64_t c14_pmevcntr[31];
515 uint64_t c14_pmevcntr_delta[31];
516 uint64_t c14_pmevtyper[31];
517 uint64_t pmccfiltr_el0;
518 uint64_t vpidr_el2;
519 uint64_t vmpidr_el2;
520 uint64_t tfsr_el[4];
521 uint64_t gcr_el1;
522 uint64_t rgsr_el1;
523 } cp15;
524
525 struct {
526
527
528
529
530
531
532
533
534
535
536
537 uint32_t other_sp;
538 uint32_t other_ss_msp;
539 uint32_t other_ss_psp;
540 uint32_t vecbase[M_REG_NUM_BANKS];
541 uint32_t basepri[M_REG_NUM_BANKS];
542 uint32_t control[M_REG_NUM_BANKS];
543 uint32_t ccr[M_REG_NUM_BANKS];
544 uint32_t cfsr[M_REG_NUM_BANKS];
545 uint32_t hfsr;
546 uint32_t dfsr;
547 uint32_t sfsr;
548 uint32_t mmfar[M_REG_NUM_BANKS];
549 uint32_t bfar;
550 uint32_t sfar;
551 unsigned mpu_ctrl[M_REG_NUM_BANKS];
552 int exception;
553 uint32_t primask[M_REG_NUM_BANKS];
554 uint32_t faultmask[M_REG_NUM_BANKS];
555 uint32_t aircr;
556 uint32_t secure;
557 uint32_t csselr[M_REG_NUM_BANKS];
558 uint32_t scr[M_REG_NUM_BANKS];
559 uint32_t msplim[M_REG_NUM_BANKS];
560 uint32_t psplim[M_REG_NUM_BANKS];
561 uint32_t fpcar[M_REG_NUM_BANKS];
562 uint32_t fpccr[M_REG_NUM_BANKS];
563 uint32_t fpdscr[M_REG_NUM_BANKS];
564 uint32_t cpacr[M_REG_NUM_BANKS];
565 uint32_t nsacr;
566 uint32_t ltpsize;
567 uint32_t vpr;
568 } v7m;
569
570
571
572
573
574
575
576 struct {
577 uint32_t syndrome;
578 uint32_t fsr;
579 uint64_t vaddress;
580 uint32_t target_el;
581
582
583
584 } exception;
585
586
587 struct {
588 uint8_t pending;
589 uint8_t has_esr;
590 uint64_t esr;
591 } serror;
592
593 uint8_t ext_dabt_raised;
594
595
596 uint32_t irq_line_state;
597
598
599 uint32_t teecr;
600 uint32_t teehbr;
601
602
603 struct {
604 ARMVectorReg zregs[32];
605
606#ifdef TARGET_AARCH64
607
608#define FFR_PRED_NUM 16
609 ARMPredicateReg pregs[17];
610
611 ARMPredicateReg preg_tmp;
612#endif
613
614
615 uint32_t qc[4] QEMU_ALIGNED(16);
616 int vec_len;
617 int vec_stride;
618
619 uint32_t xregs[16];
620
621
622 uint32_t scratch[8];
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651 float_status fp_status;
652 float_status fp_status_f16;
653 float_status standard_fp_status;
654 float_status standard_fp_status_f16;
655
656
657 uint64_t zcr_el[4];
658 } vfp;
659 uint64_t exclusive_addr;
660 uint64_t exclusive_val;
661 uint64_t exclusive_high;
662
663
664 struct {
665 uint64_t regs[16];
666 uint64_t val;
667
668 uint32_t cregs[16];
669 } iwmmxt;
670
671#ifdef TARGET_AARCH64
672 struct {
673 ARMPACKey apia;
674 ARMPACKey apib;
675 ARMPACKey apda;
676 ARMPACKey apdb;
677 ARMPACKey apga;
678 } keys;
679#endif
680
681#if defined(CONFIG_USER_ONLY)
682
683 int eabi;
684#endif
685
686 struct CPUBreakpoint *cpu_breakpoint[16];
687 struct CPUWatchpoint *cpu_watchpoint[16];
688
689
690 struct {} end_reset_fields;
691
692
693
694
695 uint64_t features;
696
697
698 struct {
699 uint32_t *drbar;
700 uint32_t *drsr;
701 uint32_t *dracr;
702 uint32_t rnr[M_REG_NUM_BANKS];
703 } pmsav7;
704
705
706 struct {
707
708
709
710
711
712 uint32_t *rbar[M_REG_NUM_BANKS];
713 uint32_t *rlar[M_REG_NUM_BANKS];
714 uint32_t mair0[M_REG_NUM_BANKS];
715 uint32_t mair1[M_REG_NUM_BANKS];
716 } pmsav8;
717
718
719 struct {
720 uint32_t *rbar;
721 uint32_t *rlar;
722 uint32_t rnr;
723 uint32_t ctrl;
724 } sau;
725
726 void *nvic;
727 const struct arm_boot_info *boot_info;
728
729 void *gicv3state;
730
731#ifdef TARGET_TAGGED_ADDRESSES
732
733 bool tagged_addr_enable;
734#endif
735} CPUARMState;
736
737static inline void set_feature(CPUARMState *env, int feature)
738{
739 env->features |= 1ULL << feature;
740}
741
742static inline void unset_feature(CPUARMState *env, int feature)
743{
744 env->features &= ~(1ULL << feature);
745}
746
747
748
749
750
751
752typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
753typedef struct ARMELChangeHook ARMELChangeHook;
754struct ARMELChangeHook {
755 ARMELChangeHookFn *hook;
756 void *opaque;
757 QLIST_ENTRY(ARMELChangeHook) node;
758};
759
760
761
762typedef enum ARMPSCIState {
763 PSCI_ON = 0,
764 PSCI_OFF = 1,
765 PSCI_ON_PENDING = 2
766} ARMPSCIState;
767
768typedef struct ARMISARegisters ARMISARegisters;
769
770
771
772
773
774
775
776struct ARMCPU {
777
778 CPUState parent_obj;
779
780
781 CPUNegativeOffsetState neg;
782 CPUARMState env;
783
784
785 GHashTable *cp_regs;
786
787
788
789
790
791
792
793 uint64_t *cpreg_indexes;
794
795 uint64_t *cpreg_values;
796
797 int32_t cpreg_array_len;
798
799
800
801
802 uint64_t *cpreg_vmstate_indexes;
803 uint64_t *cpreg_vmstate_values;
804 int32_t cpreg_vmstate_array_len;
805
806 DynamicGDBXMLInfo dyn_sysreg_xml;
807 DynamicGDBXMLInfo dyn_svereg_xml;
808
809
810 QEMUTimer *gt_timer[NUM_GTIMERS];
811
812
813
814
815 QEMUTimer *pmu_timer;
816
817 qemu_irq gt_timer_outputs[NUM_GTIMERS];
818
819 qemu_irq gicv3_maintenance_interrupt;
820
821 qemu_irq pmu_interrupt;
822
823
824 MemoryRegion *secure_memory;
825
826
827 MemoryRegion *tag_memory;
828 MemoryRegion *secure_tag_memory;
829
830
831 Object *idau;
832
833
834 const char *dtb_compatible;
835
836
837
838
839
840 uint32_t psci_version;
841
842
843 ARMPSCIState power_state;
844
845
846 bool has_el2;
847
848 bool has_el3;
849
850 bool has_pmu;
851
852 bool has_vfp;
853
854 bool has_neon;
855
856 bool has_dsp;
857
858
859 bool has_mpu;
860
861 uint32_t pmsav7_dregion;
862
863 uint32_t sau_sregion;
864
865
866
867
868 uint32_t psci_conduit;
869
870
871 uint32_t init_svtor;
872
873 uint32_t init_nsvtor;
874
875
876
877
878 uint32_t kvm_target;
879
880
881 uint32_t kvm_init_features[7];
882
883
884
885
886 bool kvm_adjvtime;
887 bool kvm_vtime_dirty;
888 uint64_t kvm_vtime;
889
890
891 OnOffAuto kvm_steal_time;
892
893
894 bool mp_is_up;
895
896
897
898
899 bool host_cpu_probe_failed;
900
901
902
903
904 int32_t core_count;
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923 struct ARMISARegisters {
924 uint32_t id_isar0;
925 uint32_t id_isar1;
926 uint32_t id_isar2;
927 uint32_t id_isar3;
928 uint32_t id_isar4;
929 uint32_t id_isar5;
930 uint32_t id_isar6;
931 uint32_t id_mmfr0;
932 uint32_t id_mmfr1;
933 uint32_t id_mmfr2;
934 uint32_t id_mmfr3;
935 uint32_t id_mmfr4;
936 uint32_t id_pfr0;
937 uint32_t id_pfr1;
938 uint32_t id_pfr2;
939 uint32_t mvfr0;
940 uint32_t mvfr1;
941 uint32_t mvfr2;
942 uint32_t id_dfr0;
943 uint32_t dbgdidr;
944 uint64_t id_aa64isar0;
945 uint64_t id_aa64isar1;
946 uint64_t id_aa64pfr0;
947 uint64_t id_aa64pfr1;
948 uint64_t id_aa64mmfr0;
949 uint64_t id_aa64mmfr1;
950 uint64_t id_aa64mmfr2;
951 uint64_t id_aa64dfr0;
952 uint64_t id_aa64dfr1;
953 uint64_t id_aa64zfr0;
954 } isar;
955 uint64_t midr;
956 uint32_t revidr;
957 uint32_t reset_fpsid;
958 uint64_t ctr;
959 uint32_t reset_sctlr;
960 uint64_t pmceid0;
961 uint64_t pmceid1;
962 uint32_t id_afr0;
963 uint64_t id_aa64afr0;
964 uint64_t id_aa64afr1;
965 uint64_t clidr;
966 uint64_t mp_affinity;
967
968
969
970 uint64_t ccsidr[16];
971 uint64_t reset_cbar;
972 uint32_t reset_auxcr;
973 bool reset_hivecs;
974
975
976
977
978
979 bool prop_pauth;
980 bool prop_pauth_impdef;
981
982
983 uint32_t dcz_blocksize;
984 uint64_t rvbar;
985
986
987 int gic_num_lrs;
988 int gic_vpribits;
989 int gic_vprebits;
990
991
992
993
994
995
996 bool cfgend;
997
998 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
999 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1000
1001 int32_t node_id;
1002
1003
1004 uint8_t device_irq_level;
1005
1006
1007 uint32_t sve_max_vq;
1008
1009#ifdef CONFIG_USER_ONLY
1010
1011 uint32_t sve_default_vq;
1012#endif
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
1024 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
1025
1026
1027 uint64_t gt_cntfrq_hz;
1028};
1029
1030unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1031
1032void arm_cpu_post_init(Object *obj);
1033
1034uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
1035
1036#ifndef CONFIG_USER_ONLY
1037extern const VMStateDescription vmstate_arm_cpu;
1038#endif
1039
1040void arm_cpu_do_interrupt(CPUState *cpu);
1041void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1042bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
1043
1044hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1045 MemTxAttrs *attrs);
1046
1047int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1048int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1049
1050
1051
1052
1053
1054int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1055int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1056
1057
1058
1059
1060
1061const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1062
1063int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1064 int cpuid, void *opaque);
1065int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1066 int cpuid, void *opaque);
1067
1068#ifdef TARGET_AARCH64
1069int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1070int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1071void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1072void aarch64_sve_change_el(CPUARMState *env, int old_el,
1073 int new_el, bool el0_a64);
1074void aarch64_add_sve_properties(Object *obj);
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1086{
1087#ifdef HOST_WORDS_BIGENDIAN
1088 int i;
1089
1090 for (i = 0; i < nr; ++i) {
1091 dst[i] = bswap64(src[i]);
1092 }
1093
1094 return dst;
1095#else
1096 return src;
1097#endif
1098}
1099
1100#else
1101static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1102static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1103 int n, bool a)
1104{ }
1105static inline void aarch64_add_sve_properties(Object *obj) { }
1106#endif
1107
1108void aarch64_sync_32_to_64(CPUARMState *env);
1109void aarch64_sync_64_to_32(CPUARMState *env);
1110
1111int fp_exception_el(CPUARMState *env, int cur_el);
1112int sve_exception_el(CPUARMState *env, int cur_el);
1113uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1114
1115static inline bool is_a64(CPUARMState *env)
1116{
1117 return env->aarch64;
1118}
1119
1120
1121
1122
1123int cpu_arm_signal_handler(int host_signum, void *pinfo,
1124 void *puc);
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134void pmu_op_start(CPUARMState *env);
1135void pmu_op_finish(CPUARMState *env);
1136
1137
1138
1139
1140void arm_pmu_timer_cb(void *opaque);
1141
1142
1143
1144
1145void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1146void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1147
1148
1149
1150
1151
1152
1153
1154
1155void pmu_init(ARMCPU *cpu);
1156
1157
1158
1159
1160
1161
1162
1163#define SCTLR_M (1U << 0)
1164#define SCTLR_A (1U << 1)
1165#define SCTLR_C (1U << 2)
1166#define SCTLR_W (1U << 3)
1167#define SCTLR_nTLSMD_32 (1U << 3)
1168#define SCTLR_SA (1U << 3)
1169#define SCTLR_P (1U << 4)
1170#define SCTLR_LSMAOE_32 (1U << 4)
1171#define SCTLR_SA0 (1U << 4)
1172#define SCTLR_D (1U << 5)
1173#define SCTLR_CP15BEN (1U << 5)
1174#define SCTLR_L (1U << 6)
1175#define SCTLR_nAA (1U << 6)
1176#define SCTLR_B (1U << 7)
1177#define SCTLR_ITD (1U << 7)
1178#define SCTLR_S (1U << 8)
1179#define SCTLR_SED (1U << 8)
1180#define SCTLR_R (1U << 9)
1181#define SCTLR_UMA (1U << 9)
1182#define SCTLR_F (1U << 10)
1183#define SCTLR_SW (1U << 10)
1184#define SCTLR_EnRCTX (1U << 10)
1185#define SCTLR_Z (1U << 11)
1186#define SCTLR_EOS (1U << 11)
1187#define SCTLR_I (1U << 12)
1188#define SCTLR_V (1U << 13)
1189#define SCTLR_EnDB (1U << 13)
1190#define SCTLR_RR (1U << 14)
1191#define SCTLR_DZE (1U << 14)
1192#define SCTLR_L4 (1U << 15)
1193#define SCTLR_UCT (1U << 15)
1194#define SCTLR_DT (1U << 16)
1195#define SCTLR_nTWI (1U << 16)
1196#define SCTLR_HA (1U << 17)
1197#define SCTLR_BR (1U << 17)
1198#define SCTLR_IT (1U << 18)
1199#define SCTLR_nTWE (1U << 18)
1200#define SCTLR_WXN (1U << 19)
1201#define SCTLR_ST (1U << 20)
1202#define SCTLR_UWXN (1U << 20)
1203#define SCTLR_FI (1U << 21)
1204#define SCTLR_IESB (1U << 21)
1205#define SCTLR_U (1U << 22)
1206#define SCTLR_EIS (1U << 22)
1207#define SCTLR_XP (1U << 23)
1208#define SCTLR_SPAN (1U << 23)
1209#define SCTLR_VE (1U << 24)
1210#define SCTLR_E0E (1U << 24)
1211#define SCTLR_EE (1U << 25)
1212#define SCTLR_L2 (1U << 26)
1213#define SCTLR_UCI (1U << 26)
1214#define SCTLR_NMFI (1U << 27)
1215#define SCTLR_EnDA (1U << 27)
1216#define SCTLR_TRE (1U << 28)
1217#define SCTLR_nTLSMD_64 (1U << 28)
1218#define SCTLR_AFE (1U << 29)
1219#define SCTLR_LSMAOE_64 (1U << 29)
1220#define SCTLR_TE (1U << 30)
1221#define SCTLR_EnIB (1U << 30)
1222#define SCTLR_EnIA (1U << 31)
1223#define SCTLR_DSSBS_32 (1U << 31)
1224#define SCTLR_BT0 (1ULL << 35)
1225#define SCTLR_BT1 (1ULL << 36)
1226#define SCTLR_ITFSB (1ULL << 37)
1227#define SCTLR_TCF0 (3ULL << 38)
1228#define SCTLR_TCF (3ULL << 40)
1229#define SCTLR_ATA0 (1ULL << 42)
1230#define SCTLR_ATA (1ULL << 43)
1231#define SCTLR_DSSBS_64 (1ULL << 44)
1232
1233#define CPTR_TCPAC (1U << 31)
1234#define CPTR_TTA (1U << 20)
1235#define CPTR_TFP (1U << 10)
1236#define CPTR_TZ (1U << 8)
1237#define CPTR_EZ (1U << 8)
1238
1239#define MDCR_EPMAD (1U << 21)
1240#define MDCR_EDAD (1U << 20)
1241#define MDCR_SPME (1U << 17)
1242#define MDCR_HPMD (1U << 17)
1243#define MDCR_SDD (1U << 16)
1244#define MDCR_SPD (3U << 14)
1245#define MDCR_TDRA (1U << 11)
1246#define MDCR_TDOSA (1U << 10)
1247#define MDCR_TDA (1U << 9)
1248#define MDCR_TDE (1U << 8)
1249#define MDCR_HPME (1U << 7)
1250#define MDCR_TPM (1U << 6)
1251#define MDCR_TPMCR (1U << 5)
1252#define MDCR_HPMN (0x1fU)
1253
1254
1255#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1256
1257#define CPSR_M (0x1fU)
1258#define CPSR_T (1U << 5)
1259#define CPSR_F (1U << 6)
1260#define CPSR_I (1U << 7)
1261#define CPSR_A (1U << 8)
1262#define CPSR_E (1U << 9)
1263#define CPSR_IT_2_7 (0xfc00U)
1264#define CPSR_GE (0xfU << 16)
1265#define CPSR_IL (1U << 20)
1266#define CPSR_DIT (1U << 21)
1267#define CPSR_PAN (1U << 22)
1268#define CPSR_SSBS (1U << 23)
1269#define CPSR_J (1U << 24)
1270#define CPSR_IT_0_1 (3U << 25)
1271#define CPSR_Q (1U << 27)
1272#define CPSR_V (1U << 28)
1273#define CPSR_C (1U << 29)
1274#define CPSR_Z (1U << 30)
1275#define CPSR_N (1U << 31)
1276#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1277#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1278
1279#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1280#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1281 | CPSR_NZCV)
1282
1283#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1284
1285#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1286
1287
1288#define XPSR_EXCP 0x1ffU
1289#define XPSR_SPREALIGN (1U << 9)
1290#define XPSR_IT_2_7 CPSR_IT_2_7
1291#define XPSR_GE CPSR_GE
1292#define XPSR_SFPA (1U << 20)
1293#define XPSR_T (1U << 24)
1294#define XPSR_IT_0_1 CPSR_IT_0_1
1295#define XPSR_Q CPSR_Q
1296#define XPSR_V CPSR_V
1297#define XPSR_C CPSR_C
1298#define XPSR_Z CPSR_Z
1299#define XPSR_N CPSR_N
1300#define XPSR_NZCV CPSR_NZCV
1301#define XPSR_IT CPSR_IT
1302
1303#define TTBCR_N (7U << 0)
1304#define TTBCR_T0SZ (7U << 0)
1305#define TTBCR_PD0 (1U << 4)
1306#define TTBCR_PD1 (1U << 5)
1307#define TTBCR_EPD0 (1U << 7)
1308#define TTBCR_IRGN0 (3U << 8)
1309#define TTBCR_ORGN0 (3U << 10)
1310#define TTBCR_SH0 (3U << 12)
1311#define TTBCR_T1SZ (3U << 16)
1312#define TTBCR_A1 (1U << 22)
1313#define TTBCR_EPD1 (1U << 23)
1314#define TTBCR_IRGN1 (3U << 24)
1315#define TTBCR_ORGN1 (3U << 26)
1316#define TTBCR_SH1 (1U << 28)
1317#define TTBCR_EAE (1U << 31)
1318
1319
1320
1321
1322
1323#define PSTATE_SP (1U)
1324#define PSTATE_M (0xFU)
1325#define PSTATE_nRW (1U << 4)
1326#define PSTATE_F (1U << 6)
1327#define PSTATE_I (1U << 7)
1328#define PSTATE_A (1U << 8)
1329#define PSTATE_D (1U << 9)
1330#define PSTATE_BTYPE (3U << 10)
1331#define PSTATE_SSBS (1U << 12)
1332#define PSTATE_IL (1U << 20)
1333#define PSTATE_SS (1U << 21)
1334#define PSTATE_PAN (1U << 22)
1335#define PSTATE_UAO (1U << 23)
1336#define PSTATE_DIT (1U << 24)
1337#define PSTATE_TCO (1U << 25)
1338#define PSTATE_V (1U << 28)
1339#define PSTATE_C (1U << 29)
1340#define PSTATE_Z (1U << 30)
1341#define PSTATE_N (1U << 31)
1342#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1343#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1344#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1345
1346#define PSTATE_MODE_EL3h 13
1347#define PSTATE_MODE_EL3t 12
1348#define PSTATE_MODE_EL2h 9
1349#define PSTATE_MODE_EL2t 8
1350#define PSTATE_MODE_EL1h 5
1351#define PSTATE_MODE_EL1t 4
1352#define PSTATE_MODE_EL0t 0
1353
1354
1355
1356
1357void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1358
1359
1360static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1361{
1362 return (el << 2) | handler;
1363}
1364
1365
1366
1367
1368
1369static inline uint32_t pstate_read(CPUARMState *env)
1370{
1371 int ZF;
1372
1373 ZF = (env->ZF == 0);
1374 return (env->NF & 0x80000000) | (ZF << 30)
1375 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1376 | env->pstate | env->daif | (env->btype << 10);
1377}
1378
1379static inline void pstate_write(CPUARMState *env, uint32_t val)
1380{
1381 env->ZF = (~val) & PSTATE_Z;
1382 env->NF = val;
1383 env->CF = (val >> 29) & 1;
1384 env->VF = (val << 3) & 0x80000000;
1385 env->daif = val & PSTATE_DAIF;
1386 env->btype = (val >> 10) & 3;
1387 env->pstate = val & ~CACHED_PSTATE_BITS;
1388}
1389
1390
1391uint32_t cpsr_read(CPUARMState *env);
1392
1393typedef enum CPSRWriteType {
1394 CPSRWriteByInstr = 0,
1395 CPSRWriteExceptionReturn = 1,
1396 CPSRWriteRaw = 2,
1397 CPSRWriteByGDBStub = 3,
1398} CPSRWriteType;
1399
1400
1401void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1402 CPSRWriteType write_type);
1403
1404
1405static inline uint32_t xpsr_read(CPUARMState *env)
1406{
1407 int ZF;
1408 ZF = (env->ZF == 0);
1409 return (env->NF & 0x80000000) | (ZF << 30)
1410 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1411 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1412 | ((env->condexec_bits & 0xfc) << 8)
1413 | (env->GE << 16)
1414 | env->v7m.exception;
1415}
1416
1417
1418static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1419{
1420 if (mask & XPSR_NZCV) {
1421 env->ZF = (~val) & XPSR_Z;
1422 env->NF = val;
1423 env->CF = (val >> 29) & 1;
1424 env->VF = (val << 3) & 0x80000000;
1425 }
1426 if (mask & XPSR_Q) {
1427 env->QF = ((val & XPSR_Q) != 0);
1428 }
1429 if (mask & XPSR_GE) {
1430 env->GE = (val & XPSR_GE) >> 16;
1431 }
1432#ifndef CONFIG_USER_ONLY
1433 if (mask & XPSR_T) {
1434 env->thumb = ((val & XPSR_T) != 0);
1435 }
1436 if (mask & XPSR_IT_0_1) {
1437 env->condexec_bits &= ~3;
1438 env->condexec_bits |= (val >> 25) & 3;
1439 }
1440 if (mask & XPSR_IT_2_7) {
1441 env->condexec_bits &= 3;
1442 env->condexec_bits |= (val >> 8) & 0xfc;
1443 }
1444 if (mask & XPSR_EXCP) {
1445
1446 write_v7m_exception(env, val & XPSR_EXCP);
1447 }
1448#endif
1449}
1450
1451#define HCR_VM (1ULL << 0)
1452#define HCR_SWIO (1ULL << 1)
1453#define HCR_PTW (1ULL << 2)
1454#define HCR_FMO (1ULL << 3)
1455#define HCR_IMO (1ULL << 4)
1456#define HCR_AMO (1ULL << 5)
1457#define HCR_VF (1ULL << 6)
1458#define HCR_VI (1ULL << 7)
1459#define HCR_VSE (1ULL << 8)
1460#define HCR_FB (1ULL << 9)
1461#define HCR_BSU_MASK (3ULL << 10)
1462#define HCR_DC (1ULL << 12)
1463#define HCR_TWI (1ULL << 13)
1464#define HCR_TWE (1ULL << 14)
1465#define HCR_TID0 (1ULL << 15)
1466#define HCR_TID1 (1ULL << 16)
1467#define HCR_TID2 (1ULL << 17)
1468#define HCR_TID3 (1ULL << 18)
1469#define HCR_TSC (1ULL << 19)
1470#define HCR_TIDCP (1ULL << 20)
1471#define HCR_TACR (1ULL << 21)
1472#define HCR_TSW (1ULL << 22)
1473#define HCR_TPCP (1ULL << 23)
1474#define HCR_TPU (1ULL << 24)
1475#define HCR_TTLB (1ULL << 25)
1476#define HCR_TVM (1ULL << 26)
1477#define HCR_TGE (1ULL << 27)
1478#define HCR_TDZ (1ULL << 28)
1479#define HCR_HCD (1ULL << 29)
1480#define HCR_TRVM (1ULL << 30)
1481#define HCR_RW (1ULL << 31)
1482#define HCR_CD (1ULL << 32)
1483#define HCR_ID (1ULL << 33)
1484#define HCR_E2H (1ULL << 34)
1485#define HCR_TLOR (1ULL << 35)
1486#define HCR_TERR (1ULL << 36)
1487#define HCR_TEA (1ULL << 37)
1488#define HCR_MIOCNCE (1ULL << 38)
1489
1490#define HCR_APK (1ULL << 40)
1491#define HCR_API (1ULL << 41)
1492#define HCR_NV (1ULL << 42)
1493#define HCR_NV1 (1ULL << 43)
1494#define HCR_AT (1ULL << 44)
1495#define HCR_NV2 (1ULL << 45)
1496#define HCR_FWB (1ULL << 46)
1497#define HCR_FIEN (1ULL << 47)
1498
1499#define HCR_TID4 (1ULL << 49)
1500#define HCR_TICAB (1ULL << 50)
1501#define HCR_AMVOFFEN (1ULL << 51)
1502#define HCR_TOCU (1ULL << 52)
1503#define HCR_ENSCXT (1ULL << 53)
1504#define HCR_TTLBIS (1ULL << 54)
1505#define HCR_TTLBOS (1ULL << 55)
1506#define HCR_ATA (1ULL << 56)
1507#define HCR_DCT (1ULL << 57)
1508#define HCR_TID5 (1ULL << 58)
1509#define HCR_TWEDEN (1ULL << 59)
1510#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1511
1512#define HPFAR_NS (1ULL << 63)
1513
1514#define SCR_NS (1U << 0)
1515#define SCR_IRQ (1U << 1)
1516#define SCR_FIQ (1U << 2)
1517#define SCR_EA (1U << 3)
1518#define SCR_FW (1U << 4)
1519#define SCR_AW (1U << 5)
1520#define SCR_NET (1U << 6)
1521#define SCR_SMD (1U << 7)
1522#define SCR_HCE (1U << 8)
1523#define SCR_SIF (1U << 9)
1524#define SCR_RW (1U << 10)
1525#define SCR_ST (1U << 11)
1526#define SCR_TWI (1U << 12)
1527#define SCR_TWE (1U << 13)
1528#define SCR_TLOR (1U << 14)
1529#define SCR_TERR (1U << 15)
1530#define SCR_APK (1U << 16)
1531#define SCR_API (1U << 17)
1532#define SCR_EEL2 (1U << 18)
1533#define SCR_EASE (1U << 19)
1534#define SCR_NMEA (1U << 20)
1535#define SCR_FIEN (1U << 21)
1536#define SCR_ENSCXT (1U << 25)
1537#define SCR_ATA (1U << 26)
1538
1539
1540uint32_t vfp_get_fpscr(CPUARMState *env);
1541void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1542
1543
1544
1545
1546
1547
1548
1549
1550#define FPSR_MASK 0xf800009f
1551#define FPCR_MASK 0x07ff9f00
1552
1553#define FPCR_IOE (1 << 8)
1554#define FPCR_DZE (1 << 9)
1555#define FPCR_OFE (1 << 10)
1556#define FPCR_UFE (1 << 11)
1557#define FPCR_IXE (1 << 12)
1558#define FPCR_IDE (1 << 15)
1559#define FPCR_FZ16 (1 << 19)
1560#define FPCR_RMODE_MASK (3 << 22)
1561#define FPCR_FZ (1 << 24)
1562#define FPCR_DN (1 << 25)
1563#define FPCR_AHP (1 << 26)
1564#define FPCR_QC (1 << 27)
1565#define FPCR_V (1 << 28)
1566#define FPCR_C (1 << 29)
1567#define FPCR_Z (1 << 30)
1568#define FPCR_N (1 << 31)
1569
1570#define FPCR_LTPSIZE_SHIFT 16
1571#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1572#define FPCR_LTPSIZE_LENGTH 3
1573
1574#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1575#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1576
1577static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1578{
1579 return vfp_get_fpscr(env) & FPSR_MASK;
1580}
1581
1582static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1583{
1584 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1585 vfp_set_fpscr(env, new_fpscr);
1586}
1587
1588static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1589{
1590 return vfp_get_fpscr(env) & FPCR_MASK;
1591}
1592
1593static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1594{
1595 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1596 vfp_set_fpscr(env, new_fpscr);
1597}
1598
1599enum arm_cpu_mode {
1600 ARM_CPU_MODE_USR = 0x10,
1601 ARM_CPU_MODE_FIQ = 0x11,
1602 ARM_CPU_MODE_IRQ = 0x12,
1603 ARM_CPU_MODE_SVC = 0x13,
1604 ARM_CPU_MODE_MON = 0x16,
1605 ARM_CPU_MODE_ABT = 0x17,
1606 ARM_CPU_MODE_HYP = 0x1a,
1607 ARM_CPU_MODE_UND = 0x1b,
1608 ARM_CPU_MODE_SYS = 0x1f
1609};
1610
1611
1612#define ARM_VFP_FPSID 0
1613#define ARM_VFP_FPSCR 1
1614#define ARM_VFP_MVFR2 5
1615#define ARM_VFP_MVFR1 6
1616#define ARM_VFP_MVFR0 7
1617#define ARM_VFP_FPEXC 8
1618#define ARM_VFP_FPINST 9
1619#define ARM_VFP_FPINST2 10
1620
1621#define ARM_VFP_FPSCR_NZCVQC 2
1622#define ARM_VFP_VPR 12
1623#define ARM_VFP_P0 13
1624#define ARM_VFP_FPCXT_NS 14
1625#define ARM_VFP_FPCXT_S 15
1626
1627
1628#define QEMU_VFP_FPSCR_NZCV 0xffff
1629
1630
1631#define ARM_IWMMXT_wCID 0
1632#define ARM_IWMMXT_wCon 1
1633#define ARM_IWMMXT_wCSSF 2
1634#define ARM_IWMMXT_wCASF 3
1635#define ARM_IWMMXT_wCGR0 8
1636#define ARM_IWMMXT_wCGR1 9
1637#define ARM_IWMMXT_wCGR2 10
1638#define ARM_IWMMXT_wCGR3 11
1639
1640
1641FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1642FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1643FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1644FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1645FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1646FIELD(V7M_CCR, STKALIGN, 9, 1)
1647FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1648FIELD(V7M_CCR, DC, 16, 1)
1649FIELD(V7M_CCR, IC, 17, 1)
1650FIELD(V7M_CCR, BP, 18, 1)
1651FIELD(V7M_CCR, LOB, 19, 1)
1652FIELD(V7M_CCR, TRD, 20, 1)
1653
1654
1655FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1656FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1657FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1658FIELD(V7M_SCR, SEVONPEND, 4, 1)
1659
1660
1661FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1662FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1663FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1664FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1665FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1666FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1667FIELD(V7M_AIRCR, PRIS, 14, 1)
1668FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1669FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1670
1671
1672FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1673FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1674FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1675FIELD(V7M_CFSR, MSTKERR, 4, 1)
1676FIELD(V7M_CFSR, MLSPERR, 5, 1)
1677FIELD(V7M_CFSR, MMARVALID, 7, 1)
1678
1679
1680FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1681FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1682FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1683FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1684FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1685FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1686FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1687
1688
1689FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1690FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1691FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1692FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1693FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1694FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1695FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1696
1697
1698FIELD(V7M_CFSR, MMFSR, 0, 8)
1699FIELD(V7M_CFSR, BFSR, 8, 8)
1700FIELD(V7M_CFSR, UFSR, 16, 16)
1701
1702
1703FIELD(V7M_HFSR, VECTTBL, 1, 1)
1704FIELD(V7M_HFSR, FORCED, 30, 1)
1705FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1706
1707
1708FIELD(V7M_DFSR, HALTED, 0, 1)
1709FIELD(V7M_DFSR, BKPT, 1, 1)
1710FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1711FIELD(V7M_DFSR, VCATCH, 3, 1)
1712FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1713
1714
1715FIELD(V7M_SFSR, INVEP, 0, 1)
1716FIELD(V7M_SFSR, INVIS, 1, 1)
1717FIELD(V7M_SFSR, INVER, 2, 1)
1718FIELD(V7M_SFSR, AUVIOL, 3, 1)
1719FIELD(V7M_SFSR, INVTRAN, 4, 1)
1720FIELD(V7M_SFSR, LSPERR, 5, 1)
1721FIELD(V7M_SFSR, SFARVALID, 6, 1)
1722FIELD(V7M_SFSR, LSERR, 7, 1)
1723
1724
1725FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1726FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1727FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1728
1729
1730FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1731FIELD(V7M_CLIDR, LOUIS, 21, 3)
1732FIELD(V7M_CLIDR, LOC, 24, 3)
1733FIELD(V7M_CLIDR, LOUU, 27, 3)
1734FIELD(V7M_CLIDR, ICB, 30, 2)
1735
1736FIELD(V7M_CSSELR, IND, 0, 1)
1737FIELD(V7M_CSSELR, LEVEL, 1, 3)
1738
1739
1740
1741
1742FIELD(V7M_CSSELR, INDEX, 0, 4)
1743
1744
1745FIELD(V7M_FPCCR, LSPACT, 0, 1)
1746FIELD(V7M_FPCCR, USER, 1, 1)
1747FIELD(V7M_FPCCR, S, 2, 1)
1748FIELD(V7M_FPCCR, THREAD, 3, 1)
1749FIELD(V7M_FPCCR, HFRDY, 4, 1)
1750FIELD(V7M_FPCCR, MMRDY, 5, 1)
1751FIELD(V7M_FPCCR, BFRDY, 6, 1)
1752FIELD(V7M_FPCCR, SFRDY, 7, 1)
1753FIELD(V7M_FPCCR, MONRDY, 8, 1)
1754FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1755FIELD(V7M_FPCCR, UFRDY, 10, 1)
1756FIELD(V7M_FPCCR, RES0, 11, 15)
1757FIELD(V7M_FPCCR, TS, 26, 1)
1758FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1759FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1760FIELD(V7M_FPCCR, LSPENS, 29, 1)
1761FIELD(V7M_FPCCR, LSPEN, 30, 1)
1762FIELD(V7M_FPCCR, ASPEN, 31, 1)
1763
1764#define R_V7M_FPCCR_BANKED_MASK \
1765 (R_V7M_FPCCR_LSPACT_MASK | \
1766 R_V7M_FPCCR_USER_MASK | \
1767 R_V7M_FPCCR_THREAD_MASK | \
1768 R_V7M_FPCCR_MMRDY_MASK | \
1769 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1770 R_V7M_FPCCR_UFRDY_MASK | \
1771 R_V7M_FPCCR_ASPEN_MASK)
1772
1773
1774FIELD(V7M_VPR, P0, 0, 16)
1775FIELD(V7M_VPR, MASK01, 16, 4)
1776FIELD(V7M_VPR, MASK23, 20, 4)
1777
1778
1779
1780
1781FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1782FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1783FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1784FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1785FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1786FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1787FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1788FIELD(CLIDR_EL1, LOUIS, 21, 3)
1789FIELD(CLIDR_EL1, LOC, 24, 3)
1790FIELD(CLIDR_EL1, LOUU, 27, 3)
1791FIELD(CLIDR_EL1, ICB, 30, 3)
1792
1793
1794FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
1795FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
1796FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
1797
1798
1799FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
1800FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
1801FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
1802
1803FIELD(CTR_EL0, IMINLINE, 0, 4)
1804FIELD(CTR_EL0, L1IP, 14, 2)
1805FIELD(CTR_EL0, DMINLINE, 16, 4)
1806FIELD(CTR_EL0, ERG, 20, 4)
1807FIELD(CTR_EL0, CWG, 24, 4)
1808FIELD(CTR_EL0, IDC, 28, 1)
1809FIELD(CTR_EL0, DIC, 29, 1)
1810FIELD(CTR_EL0, TMINLINE, 32, 6)
1811
1812FIELD(MIDR_EL1, REVISION, 0, 4)
1813FIELD(MIDR_EL1, PARTNUM, 4, 12)
1814FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1815FIELD(MIDR_EL1, VARIANT, 20, 4)
1816FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1817
1818FIELD(ID_ISAR0, SWAP, 0, 4)
1819FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1820FIELD(ID_ISAR0, BITFIELD, 8, 4)
1821FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1822FIELD(ID_ISAR0, COPROC, 16, 4)
1823FIELD(ID_ISAR0, DEBUG, 20, 4)
1824FIELD(ID_ISAR0, DIVIDE, 24, 4)
1825
1826FIELD(ID_ISAR1, ENDIAN, 0, 4)
1827FIELD(ID_ISAR1, EXCEPT, 4, 4)
1828FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1829FIELD(ID_ISAR1, EXTEND, 12, 4)
1830FIELD(ID_ISAR1, IFTHEN, 16, 4)
1831FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1832FIELD(ID_ISAR1, INTERWORK, 24, 4)
1833FIELD(ID_ISAR1, JAZELLE, 28, 4)
1834
1835FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1836FIELD(ID_ISAR2, MEMHINT, 4, 4)
1837FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1838FIELD(ID_ISAR2, MULT, 12, 4)
1839FIELD(ID_ISAR2, MULTS, 16, 4)
1840FIELD(ID_ISAR2, MULTU, 20, 4)
1841FIELD(ID_ISAR2, PSR_AR, 24, 4)
1842FIELD(ID_ISAR2, REVERSAL, 28, 4)
1843
1844FIELD(ID_ISAR3, SATURATE, 0, 4)
1845FIELD(ID_ISAR3, SIMD, 4, 4)
1846FIELD(ID_ISAR3, SVC, 8, 4)
1847FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1848FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1849FIELD(ID_ISAR3, T32COPY, 20, 4)
1850FIELD(ID_ISAR3, TRUENOP, 24, 4)
1851FIELD(ID_ISAR3, T32EE, 28, 4)
1852
1853FIELD(ID_ISAR4, UNPRIV, 0, 4)
1854FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1855FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1856FIELD(ID_ISAR4, SMC, 12, 4)
1857FIELD(ID_ISAR4, BARRIER, 16, 4)
1858FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1859FIELD(ID_ISAR4, PSR_M, 24, 4)
1860FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1861
1862FIELD(ID_ISAR5, SEVL, 0, 4)
1863FIELD(ID_ISAR5, AES, 4, 4)
1864FIELD(ID_ISAR5, SHA1, 8, 4)
1865FIELD(ID_ISAR5, SHA2, 12, 4)
1866FIELD(ID_ISAR5, CRC32, 16, 4)
1867FIELD(ID_ISAR5, RDM, 24, 4)
1868FIELD(ID_ISAR5, VCMA, 28, 4)
1869
1870FIELD(ID_ISAR6, JSCVT, 0, 4)
1871FIELD(ID_ISAR6, DP, 4, 4)
1872FIELD(ID_ISAR6, FHM, 8, 4)
1873FIELD(ID_ISAR6, SB, 12, 4)
1874FIELD(ID_ISAR6, SPECRES, 16, 4)
1875FIELD(ID_ISAR6, BF16, 20, 4)
1876FIELD(ID_ISAR6, I8MM, 24, 4)
1877
1878FIELD(ID_MMFR0, VMSA, 0, 4)
1879FIELD(ID_MMFR0, PMSA, 4, 4)
1880FIELD(ID_MMFR0, OUTERSHR, 8, 4)
1881FIELD(ID_MMFR0, SHARELVL, 12, 4)
1882FIELD(ID_MMFR0, TCM, 16, 4)
1883FIELD(ID_MMFR0, AUXREG, 20, 4)
1884FIELD(ID_MMFR0, FCSE, 24, 4)
1885FIELD(ID_MMFR0, INNERSHR, 28, 4)
1886
1887FIELD(ID_MMFR1, L1HVDVA, 0, 4)
1888FIELD(ID_MMFR1, L1UNIVA, 4, 4)
1889FIELD(ID_MMFR1, L1HVDSW, 8, 4)
1890FIELD(ID_MMFR1, L1UNISW, 12, 4)
1891FIELD(ID_MMFR1, L1HVD, 16, 4)
1892FIELD(ID_MMFR1, L1UNI, 20, 4)
1893FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
1894FIELD(ID_MMFR1, BPRED, 28, 4)
1895
1896FIELD(ID_MMFR2, L1HVDFG, 0, 4)
1897FIELD(ID_MMFR2, L1HVDBG, 4, 4)
1898FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
1899FIELD(ID_MMFR2, HVDTLB, 12, 4)
1900FIELD(ID_MMFR2, UNITLB, 16, 4)
1901FIELD(ID_MMFR2, MEMBARR, 20, 4)
1902FIELD(ID_MMFR2, WFISTALL, 24, 4)
1903FIELD(ID_MMFR2, HWACCFLG, 28, 4)
1904
1905FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1906FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1907FIELD(ID_MMFR3, BPMAINT, 8, 4)
1908FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1909FIELD(ID_MMFR3, PAN, 16, 4)
1910FIELD(ID_MMFR3, COHWALK, 20, 4)
1911FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1912FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1913
1914FIELD(ID_MMFR4, SPECSEI, 0, 4)
1915FIELD(ID_MMFR4, AC2, 4, 4)
1916FIELD(ID_MMFR4, XNX, 8, 4)
1917FIELD(ID_MMFR4, CNP, 12, 4)
1918FIELD(ID_MMFR4, HPDS, 16, 4)
1919FIELD(ID_MMFR4, LSM, 20, 4)
1920FIELD(ID_MMFR4, CCIDX, 24, 4)
1921FIELD(ID_MMFR4, EVT, 28, 4)
1922
1923FIELD(ID_MMFR5, ETS, 0, 4)
1924
1925FIELD(ID_PFR0, STATE0, 0, 4)
1926FIELD(ID_PFR0, STATE1, 4, 4)
1927FIELD(ID_PFR0, STATE2, 8, 4)
1928FIELD(ID_PFR0, STATE3, 12, 4)
1929FIELD(ID_PFR0, CSV2, 16, 4)
1930FIELD(ID_PFR0, AMU, 20, 4)
1931FIELD(ID_PFR0, DIT, 24, 4)
1932FIELD(ID_PFR0, RAS, 28, 4)
1933
1934FIELD(ID_PFR1, PROGMOD, 0, 4)
1935FIELD(ID_PFR1, SECURITY, 4, 4)
1936FIELD(ID_PFR1, MPROGMOD, 8, 4)
1937FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
1938FIELD(ID_PFR1, GENTIMER, 16, 4)
1939FIELD(ID_PFR1, SEC_FRAC, 20, 4)
1940FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
1941FIELD(ID_PFR1, GIC, 28, 4)
1942
1943FIELD(ID_PFR2, CSV3, 0, 4)
1944FIELD(ID_PFR2, SSBS, 4, 4)
1945FIELD(ID_PFR2, RAS_FRAC, 8, 4)
1946
1947FIELD(ID_AA64ISAR0, AES, 4, 4)
1948FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1949FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1950FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1951FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1952FIELD(ID_AA64ISAR0, RDM, 28, 4)
1953FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1954FIELD(ID_AA64ISAR0, SM3, 36, 4)
1955FIELD(ID_AA64ISAR0, SM4, 40, 4)
1956FIELD(ID_AA64ISAR0, DP, 44, 4)
1957FIELD(ID_AA64ISAR0, FHM, 48, 4)
1958FIELD(ID_AA64ISAR0, TS, 52, 4)
1959FIELD(ID_AA64ISAR0, TLB, 56, 4)
1960FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1961
1962FIELD(ID_AA64ISAR1, DPB, 0, 4)
1963FIELD(ID_AA64ISAR1, APA, 4, 4)
1964FIELD(ID_AA64ISAR1, API, 8, 4)
1965FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1966FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1967FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1968FIELD(ID_AA64ISAR1, GPA, 24, 4)
1969FIELD(ID_AA64ISAR1, GPI, 28, 4)
1970FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1971FIELD(ID_AA64ISAR1, SB, 36, 4)
1972FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1973FIELD(ID_AA64ISAR1, BF16, 44, 4)
1974FIELD(ID_AA64ISAR1, DGH, 48, 4)
1975FIELD(ID_AA64ISAR1, I8MM, 52, 4)
1976
1977FIELD(ID_AA64PFR0, EL0, 0, 4)
1978FIELD(ID_AA64PFR0, EL1, 4, 4)
1979FIELD(ID_AA64PFR0, EL2, 8, 4)
1980FIELD(ID_AA64PFR0, EL3, 12, 4)
1981FIELD(ID_AA64PFR0, FP, 16, 4)
1982FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1983FIELD(ID_AA64PFR0, GIC, 24, 4)
1984FIELD(ID_AA64PFR0, RAS, 28, 4)
1985FIELD(ID_AA64PFR0, SVE, 32, 4)
1986FIELD(ID_AA64PFR0, SEL2, 36, 4)
1987FIELD(ID_AA64PFR0, MPAM, 40, 4)
1988FIELD(ID_AA64PFR0, AMU, 44, 4)
1989FIELD(ID_AA64PFR0, DIT, 48, 4)
1990FIELD(ID_AA64PFR0, CSV2, 56, 4)
1991FIELD(ID_AA64PFR0, CSV3, 60, 4)
1992
1993FIELD(ID_AA64PFR1, BT, 0, 4)
1994FIELD(ID_AA64PFR1, SSBS, 4, 4)
1995FIELD(ID_AA64PFR1, MTE, 8, 4)
1996FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1997FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
1998
1999FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2000FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2001FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2002FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2003FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2004FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2005FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2006FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2007FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2008FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2009FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2010FIELD(ID_AA64MMFR0, EXS, 44, 4)
2011FIELD(ID_AA64MMFR0, FGT, 56, 4)
2012FIELD(ID_AA64MMFR0, ECV, 60, 4)
2013
2014FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2015FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2016FIELD(ID_AA64MMFR1, VH, 8, 4)
2017FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2018FIELD(ID_AA64MMFR1, LO, 16, 4)
2019FIELD(ID_AA64MMFR1, PAN, 20, 4)
2020FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2021FIELD(ID_AA64MMFR1, XNX, 28, 4)
2022FIELD(ID_AA64MMFR1, TWED, 32, 4)
2023FIELD(ID_AA64MMFR1, ETS, 36, 4)
2024
2025FIELD(ID_AA64MMFR2, CNP, 0, 4)
2026FIELD(ID_AA64MMFR2, UAO, 4, 4)
2027FIELD(ID_AA64MMFR2, LSM, 8, 4)
2028FIELD(ID_AA64MMFR2, IESB, 12, 4)
2029FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2030FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2031FIELD(ID_AA64MMFR2, NV, 24, 4)
2032FIELD(ID_AA64MMFR2, ST, 28, 4)
2033FIELD(ID_AA64MMFR2, AT, 32, 4)
2034FIELD(ID_AA64MMFR2, IDS, 36, 4)
2035FIELD(ID_AA64MMFR2, FWB, 40, 4)
2036FIELD(ID_AA64MMFR2, TTL, 48, 4)
2037FIELD(ID_AA64MMFR2, BBM, 52, 4)
2038FIELD(ID_AA64MMFR2, EVT, 56, 4)
2039FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2040
2041FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2042FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2043FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2044FIELD(ID_AA64DFR0, BRPS, 12, 4)
2045FIELD(ID_AA64DFR0, WRPS, 20, 4)
2046FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2047FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2048FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2049FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2050FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2051
2052FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2053FIELD(ID_AA64ZFR0, AES, 4, 4)
2054FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2055FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2056FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2057FIELD(ID_AA64ZFR0, SM4, 40, 4)
2058FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2059FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2060FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2061
2062FIELD(ID_DFR0, COPDBG, 0, 4)
2063FIELD(ID_DFR0, COPSDBG, 4, 4)
2064FIELD(ID_DFR0, MMAPDBG, 8, 4)
2065FIELD(ID_DFR0, COPTRC, 12, 4)
2066FIELD(ID_DFR0, MMAPTRC, 16, 4)
2067FIELD(ID_DFR0, MPROFDBG, 20, 4)
2068FIELD(ID_DFR0, PERFMON, 24, 4)
2069FIELD(ID_DFR0, TRACEFILT, 28, 4)
2070
2071FIELD(ID_DFR1, MTPMU, 0, 4)
2072
2073FIELD(DBGDIDR, SE_IMP, 12, 1)
2074FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2075FIELD(DBGDIDR, VERSION, 16, 4)
2076FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2077FIELD(DBGDIDR, BRPS, 24, 4)
2078FIELD(DBGDIDR, WRPS, 28, 4)
2079
2080FIELD(MVFR0, SIMDREG, 0, 4)
2081FIELD(MVFR0, FPSP, 4, 4)
2082FIELD(MVFR0, FPDP, 8, 4)
2083FIELD(MVFR0, FPTRAP, 12, 4)
2084FIELD(MVFR0, FPDIVIDE, 16, 4)
2085FIELD(MVFR0, FPSQRT, 20, 4)
2086FIELD(MVFR0, FPSHVEC, 24, 4)
2087FIELD(MVFR0, FPROUND, 28, 4)
2088
2089FIELD(MVFR1, FPFTZ, 0, 4)
2090FIELD(MVFR1, FPDNAN, 4, 4)
2091FIELD(MVFR1, SIMDLS, 8, 4)
2092FIELD(MVFR1, SIMDINT, 12, 4)
2093FIELD(MVFR1, SIMDSP, 16, 4)
2094FIELD(MVFR1, SIMDHP, 20, 4)
2095FIELD(MVFR1, MVE, 8, 4)
2096FIELD(MVFR1, FP16, 20, 4)
2097FIELD(MVFR1, FPHP, 24, 4)
2098FIELD(MVFR1, SIMDFMAC, 28, 4)
2099
2100FIELD(MVFR2, SIMDMISC, 0, 4)
2101FIELD(MVFR2, FPMISC, 4, 4)
2102
2103QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2104
2105
2106
2107
2108
2109enum arm_features {
2110 ARM_FEATURE_AUXCR,
2111 ARM_FEATURE_XSCALE,
2112 ARM_FEATURE_IWMMXT,
2113 ARM_FEATURE_V6,
2114 ARM_FEATURE_V6K,
2115 ARM_FEATURE_V7,
2116 ARM_FEATURE_THUMB2,
2117 ARM_FEATURE_PMSA,
2118 ARM_FEATURE_NEON,
2119 ARM_FEATURE_M,
2120 ARM_FEATURE_OMAPCP,
2121 ARM_FEATURE_THUMB2EE,
2122 ARM_FEATURE_V7MP,
2123 ARM_FEATURE_V7VE,
2124 ARM_FEATURE_V4T,
2125 ARM_FEATURE_V5,
2126 ARM_FEATURE_STRONGARM,
2127 ARM_FEATURE_VAPA,
2128 ARM_FEATURE_GENERIC_TIMER,
2129 ARM_FEATURE_MVFR,
2130 ARM_FEATURE_DUMMY_C15_REGS,
2131 ARM_FEATURE_CACHE_TEST_CLEAN,
2132 ARM_FEATURE_CACHE_DIRTY_REG,
2133 ARM_FEATURE_CACHE_BLOCK_OPS,
2134 ARM_FEATURE_MPIDR,
2135 ARM_FEATURE_LPAE,
2136 ARM_FEATURE_V8,
2137 ARM_FEATURE_AARCH64,
2138 ARM_FEATURE_CBAR,
2139 ARM_FEATURE_CBAR_RO,
2140 ARM_FEATURE_EL2,
2141 ARM_FEATURE_EL3,
2142 ARM_FEATURE_THUMB_DSP,
2143 ARM_FEATURE_PMU,
2144 ARM_FEATURE_VBAR,
2145 ARM_FEATURE_M_SECURITY,
2146 ARM_FEATURE_M_MAIN,
2147 ARM_FEATURE_V8_1M,
2148};
2149
2150static inline int arm_feature(CPUARMState *env, int feature)
2151{
2152 return (env->features & (1ULL << feature)) != 0;
2153}
2154
2155void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2156
2157#if !defined(CONFIG_USER_ONLY)
2158
2159
2160
2161
2162
2163
2164static inline bool arm_is_secure_below_el3(CPUARMState *env)
2165{
2166 if (arm_feature(env, ARM_FEATURE_EL3)) {
2167 return !(env->cp15.scr_el3 & SCR_NS);
2168 } else {
2169
2170
2171
2172 return false;
2173 }
2174}
2175
2176
2177static inline bool arm_is_el3_or_mon(CPUARMState *env)
2178{
2179 if (arm_feature(env, ARM_FEATURE_EL3)) {
2180 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2181
2182 return true;
2183 } else if (!is_a64(env) &&
2184 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2185
2186 return true;
2187 }
2188 }
2189 return false;
2190}
2191
2192
2193static inline bool arm_is_secure(CPUARMState *env)
2194{
2195 if (arm_is_el3_or_mon(env)) {
2196 return true;
2197 }
2198 return arm_is_secure_below_el3(env);
2199}
2200
2201
2202
2203
2204
2205static inline bool arm_is_el2_enabled(CPUARMState *env)
2206{
2207 if (arm_feature(env, ARM_FEATURE_EL2)) {
2208 if (arm_is_secure_below_el3(env)) {
2209 return (env->cp15.scr_el3 & SCR_EEL2) != 0;
2210 }
2211 return true;
2212 }
2213 return false;
2214}
2215
2216#else
2217static inline bool arm_is_secure_below_el3(CPUARMState *env)
2218{
2219 return false;
2220}
2221
2222static inline bool arm_is_secure(CPUARMState *env)
2223{
2224 return false;
2225}
2226
2227static inline bool arm_is_el2_enabled(CPUARMState *env)
2228{
2229 return false;
2230}
2231#endif
2232
2233
2234
2235
2236
2237
2238
2239uint64_t arm_hcr_el2_eff(CPUARMState *env);
2240
2241
2242static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2243{
2244
2245
2246
2247 assert(el >= 1 && el <= 3);
2248 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2249
2250
2251
2252
2253
2254 if (el == 3) {
2255 return aa64;
2256 }
2257
2258 if (arm_feature(env, ARM_FEATURE_EL3) &&
2259 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
2260 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2261 }
2262
2263 if (el == 2) {
2264 return aa64;
2265 }
2266
2267 if (arm_is_el2_enabled(env)) {
2268 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2269 }
2270
2271 return aa64;
2272}
2273
2274
2275
2276
2277
2278
2279
2280
2281static inline bool access_secure_reg(CPUARMState *env)
2282{
2283 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2284 !arm_el_is_aa64(env, 3) &&
2285 !(env->cp15.scr_el3 & SCR_NS));
2286
2287 return ret;
2288}
2289
2290
2291#define A32_BANKED_REG_GET(_env, _regname, _secure) \
2292 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2293
2294#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2295 do { \
2296 if (_secure) { \
2297 (_env)->cp15._regname##_s = (_val); \
2298 } else { \
2299 (_env)->cp15._regname##_ns = (_val); \
2300 } \
2301 } while (0)
2302
2303
2304
2305
2306
2307
2308#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2309 A32_BANKED_REG_GET((_env), _regname, \
2310 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2311
2312#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2313 A32_BANKED_REG_SET((_env), _regname, \
2314 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2315 (_val))
2316
2317void arm_cpu_list(void);
2318uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2319 uint32_t cur_el, bool secure);
2320
2321
2322#ifndef CONFIG_USER_ONLY
2323bool armv7m_nvic_can_take_pending_exception(void *opaque);
2324#else
2325static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2326{
2327 return true;
2328}
2329#endif
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2382 bool *ptargets_secure);
2383
2384
2385
2386
2387
2388
2389
2390
2391void armv7m_nvic_acknowledge_irq(void *opaque);
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427int armv7m_nvic_raw_execution_priority(void *opaque);
2428
2429
2430
2431
2432
2433
2434
2435#ifndef CONFIG_USER_ONLY
2436bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2437#else
2438static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2439{
2440 return false;
2441}
2442#endif
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470#define CP_REG_AA64_SHIFT 28
2471#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2472
2473
2474
2475
2476
2477#define CP_REG_NS_SHIFT 29
2478#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2479
2480#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2481 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2482 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2483
2484#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2485 (CP_REG_AA64_MASK | \
2486 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2487 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2488 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2489 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2490 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2491 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2492
2493
2494
2495
2496static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2497{
2498 uint32_t cpregid = kvmid;
2499 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2500 cpregid |= CP_REG_AA64_MASK;
2501 } else {
2502 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2503 cpregid |= (1 << 15);
2504 }
2505
2506
2507
2508
2509 cpregid |= 1 << CP_REG_NS_SHIFT;
2510 }
2511 return cpregid;
2512}
2513
2514
2515
2516
2517static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2518{
2519 uint64_t kvmid;
2520
2521 if (cpregid & CP_REG_AA64_MASK) {
2522 kvmid = cpregid & ~CP_REG_AA64_MASK;
2523 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2524 } else {
2525 kvmid = cpregid & ~(1 << 15);
2526 if (cpregid & (1 << 15)) {
2527 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2528 } else {
2529 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2530 }
2531 }
2532 return kvmid;
2533}
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563#define ARM_CP_SPECIAL 0x0001
2564#define ARM_CP_CONST 0x0002
2565#define ARM_CP_64BIT 0x0004
2566#define ARM_CP_SUPPRESS_TB_END 0x0008
2567#define ARM_CP_OVERRIDE 0x0010
2568#define ARM_CP_ALIAS 0x0020
2569#define ARM_CP_IO 0x0040
2570#define ARM_CP_NO_RAW 0x0080
2571#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2572#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2573#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2574#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2575#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2576#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600)
2577#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700)
2578#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA
2579#define ARM_CP_FPU 0x1000
2580#define ARM_CP_SVE 0x2000
2581#define ARM_CP_NO_GDB 0x4000
2582#define ARM_CP_RAISES_EXC 0x8000
2583#define ARM_CP_NEWEL 0x10000
2584
2585#define ARM_CP_SENTINEL 0xfffff
2586
2587#define ARM_CP_FLAG_MASK 0x1f0ff
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598enum {
2599 ARM_CP_STATE_AA32 = 0,
2600 ARM_CP_STATE_AA64 = 1,
2601 ARM_CP_STATE_BOTH = 2,
2602};
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614enum {
2615 ARM_CP_SECSTATE_S = (1 << 0),
2616 ARM_CP_SECSTATE_NS = (1 << 1),
2617};
2618
2619
2620
2621
2622
2623static inline bool cptype_valid(int cptype)
2624{
2625 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2626 || ((cptype & ARM_CP_SPECIAL) &&
2627 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2628}
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647#define PL3_R 0x80
2648#define PL3_W 0x40
2649#define PL2_R (0x20 | PL3_R)
2650#define PL2_W (0x10 | PL3_W)
2651#define PL1_R (0x08 | PL2_R)
2652#define PL1_W (0x04 | PL2_W)
2653#define PL0_R (0x02 | PL1_R)
2654#define PL0_W (0x01 | PL1_W)
2655
2656
2657
2658
2659
2660
2661
2662#ifdef CONFIG_USER_ONLY
2663#define PL0U_R PL0_R
2664#else
2665#define PL0U_R PL1_R
2666#endif
2667
2668#define PL3_RW (PL3_R | PL3_W)
2669#define PL2_RW (PL2_R | PL2_W)
2670#define PL1_RW (PL1_R | PL1_W)
2671#define PL0_RW (PL0_R | PL0_W)
2672
2673
2674static inline int arm_highest_el(CPUARMState *env)
2675{
2676 if (arm_feature(env, ARM_FEATURE_EL3)) {
2677 return 3;
2678 }
2679 if (arm_feature(env, ARM_FEATURE_EL2)) {
2680 return 2;
2681 }
2682 return 1;
2683}
2684
2685
2686static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2687{
2688 return env->v7m.exception != 0;
2689}
2690
2691
2692
2693
2694static inline int arm_current_el(CPUARMState *env)
2695{
2696 if (arm_feature(env, ARM_FEATURE_M)) {
2697 return arm_v7m_is_handler_mode(env) ||
2698 !(env->v7m.control[env->v7m.secure] & 1);
2699 }
2700
2701 if (is_a64(env)) {
2702 return extract32(env->pstate, 2, 2);
2703 }
2704
2705 switch (env->uncached_cpsr & 0x1f) {
2706 case ARM_CPU_MODE_USR:
2707 return 0;
2708 case ARM_CPU_MODE_HYP:
2709 return 2;
2710 case ARM_CPU_MODE_MON:
2711 return 3;
2712 default:
2713 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2714
2715
2716
2717 return 3;
2718 }
2719
2720 return 1;
2721 }
2722}
2723
2724typedef struct ARMCPRegInfo ARMCPRegInfo;
2725
2726typedef enum CPAccessResult {
2727
2728 CP_ACCESS_OK = 0,
2729
2730
2731
2732
2733
2734
2735 CP_ACCESS_TRAP = 1,
2736
2737
2738
2739
2740 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2741
2742 CP_ACCESS_TRAP_EL2 = 3,
2743 CP_ACCESS_TRAP_EL3 = 4,
2744
2745 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2746 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2747
2748
2749
2750 CP_ACCESS_TRAP_FP_EL2 = 7,
2751 CP_ACCESS_TRAP_FP_EL3 = 8,
2752} CPAccessResult;
2753
2754
2755
2756
2757typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2758typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2759 uint64_t value);
2760
2761typedef CPAccessResult CPAccessFn(CPUARMState *env,
2762 const ARMCPRegInfo *opaque,
2763 bool isread);
2764
2765typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2766
2767#define CP_ANY 0xff
2768
2769
2770struct ARMCPRegInfo {
2771
2772 const char *name;
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790 uint8_t cp;
2791 uint8_t crn;
2792 uint8_t crm;
2793 uint8_t opc0;
2794 uint8_t opc1;
2795 uint8_t opc2;
2796
2797 int state;
2798
2799 int type;
2800
2801 int access;
2802
2803 int secure;
2804
2805
2806
2807
2808 void *opaque;
2809
2810
2811
2812 uint64_t resetvalue;
2813
2814
2815
2816
2817
2818
2819 ptrdiff_t fieldoffset;
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832 ptrdiff_t bank_fieldoffsets[2];
2833
2834
2835
2836
2837
2838
2839 CPAccessFn *accessfn;
2840
2841
2842
2843
2844 CPReadFn *readfn;
2845
2846
2847
2848
2849 CPWriteFn *writefn;
2850
2851
2852
2853
2854
2855 CPReadFn *raw_readfn;
2856
2857
2858
2859
2860
2861
2862 CPWriteFn *raw_writefn;
2863
2864
2865
2866
2867 CPResetFn *resetfn;
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879 CPReadFn *orig_readfn;
2880 CPWriteFn *orig_writefn;
2881};
2882
2883
2884
2885
2886#define CPREG_FIELD32(env, ri) \
2887 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2888#define CPREG_FIELD64(env, ri) \
2889 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2890
2891#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2892
2893void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2894 const ARMCPRegInfo *regs, void *opaque);
2895void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2896 const ARMCPRegInfo *regs, void *opaque);
2897static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2898{
2899 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2900}
2901static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2902{
2903 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2904}
2905const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2906
2907
2908
2909
2910
2911
2912
2913typedef struct ARMCPRegUserSpaceInfo {
2914
2915 const char *name;
2916
2917
2918 bool is_glob;
2919
2920
2921 uint64_t exported_bits;
2922
2923
2924 uint64_t fixed_bits;
2925} ARMCPRegUserSpaceInfo;
2926
2927#define REGUSERINFO_SENTINEL { .name = NULL }
2928
2929void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2930
2931
2932void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2933 uint64_t value);
2934
2935uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2936
2937
2938
2939
2940void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2941
2942
2943
2944
2945static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2946{
2947 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2948}
2949
2950static inline bool cp_access_ok(int current_el,
2951 const ARMCPRegInfo *ri, int isread)
2952{
2953 return (ri->access >> ((current_el * 2) + isread)) & 1;
2954}
2955
2956
2957uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973bool write_list_to_cpustate(ARMCPU *cpu);
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2997
2998#define ARM_CPUID_TI915T 0x54029152
2999#define ARM_CPUID_TI925T 0x54029252
3000
3001#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
3002#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
3003#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
3004
3005#define cpu_signal_handler cpu_arm_signal_handler
3006#define cpu_list arm_cpu_list
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102#define ARM_MMU_IDX_A 0x10
3103#define ARM_MMU_IDX_NOTLB 0x20
3104#define ARM_MMU_IDX_M 0x40
3105
3106
3107#define ARM_MMU_IDX_A_NS 0x8
3108
3109
3110#define ARM_MMU_IDX_M_PRIV 0x1
3111#define ARM_MMU_IDX_M_NEGPRI 0x2
3112#define ARM_MMU_IDX_M_S 0x4
3113
3114#define ARM_MMU_IDX_TYPE_MASK \
3115 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
3116#define ARM_MMU_IDX_COREIDX_MASK 0xf
3117
3118typedef enum ARMMMUIdx {
3119
3120
3121
3122 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A,
3123 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A,
3124 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A,
3125 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A,
3126 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A,
3127 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A,
3128 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A,
3129 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A,
3130
3131 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS,
3132 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS,
3133 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS,
3134 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS,
3135 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS,
3136 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS,
3137 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS,
3138
3139
3140
3141
3142
3143 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
3144 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
3145 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
3146 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB,
3147 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB,
3148 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB,
3149
3150
3151
3152
3153
3154
3155
3156 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB,
3157 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB,
3158
3159
3160
3161
3162 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
3163 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
3164 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
3165 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
3166 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
3167 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
3168 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
3169 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
3170} ARMMMUIdx;
3171
3172
3173
3174
3175
3176#define TO_CORE_BIT(NAME) \
3177 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
3178
3179typedef enum ARMMMUIdxBit {
3180 TO_CORE_BIT(E10_0),
3181 TO_CORE_BIT(E20_0),
3182 TO_CORE_BIT(E10_1),
3183 TO_CORE_BIT(E10_1_PAN),
3184 TO_CORE_BIT(E2),
3185 TO_CORE_BIT(E20_2),
3186 TO_CORE_BIT(E20_2_PAN),
3187 TO_CORE_BIT(SE10_0),
3188 TO_CORE_BIT(SE20_0),
3189 TO_CORE_BIT(SE10_1),
3190 TO_CORE_BIT(SE20_2),
3191 TO_CORE_BIT(SE10_1_PAN),
3192 TO_CORE_BIT(SE20_2_PAN),
3193 TO_CORE_BIT(SE2),
3194 TO_CORE_BIT(SE3),
3195
3196 TO_CORE_BIT(MUser),
3197 TO_CORE_BIT(MPriv),
3198 TO_CORE_BIT(MUserNegPri),
3199 TO_CORE_BIT(MPrivNegPri),
3200 TO_CORE_BIT(MSUser),
3201 TO_CORE_BIT(MSPriv),
3202 TO_CORE_BIT(MSUserNegPri),
3203 TO_CORE_BIT(MSPrivNegPri),
3204} ARMMMUIdxBit;
3205
3206#undef TO_CORE_BIT
3207
3208#define MMU_USER_IDX 0
3209
3210
3211typedef enum ARMASIdx {
3212 ARMASIdx_NS = 0,
3213 ARMASIdx_S = 1,
3214 ARMASIdx_TagNS = 2,
3215 ARMASIdx_TagS = 3,
3216} ARMASIdx;
3217
3218
3219static inline int arm_debug_target_el(CPUARMState *env)
3220{
3221 bool secure = arm_is_secure(env);
3222 bool route_to_el2 = false;
3223
3224 if (arm_is_el2_enabled(env)) {
3225 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
3226 env->cp15.mdcr_el2 & MDCR_TDE;
3227 }
3228
3229 if (route_to_el2) {
3230 return 2;
3231 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
3232 !arm_el_is_aa64(env, 3) && secure) {
3233 return 3;
3234 } else {
3235 return 1;
3236 }
3237}
3238
3239static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3240{
3241
3242
3243
3244 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3245}
3246
3247
3248static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
3249{
3250 int cur_el = arm_current_el(env);
3251 int debug_el;
3252
3253 if (cur_el == 3) {
3254 return false;
3255 }
3256
3257
3258 if (arm_is_secure_below_el3(env)
3259 && extract32(env->cp15.mdcr_el3, 16, 1)) {
3260 return false;
3261 }
3262
3263
3264
3265
3266
3267 debug_el = arm_debug_target_el(env);
3268
3269 if (cur_el == debug_el) {
3270 return extract32(env->cp15.mdscr_el1, 13, 1)
3271 && !(env->daif & PSTATE_D);
3272 }
3273
3274
3275 return debug_el > cur_el;
3276}
3277
3278static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3279{
3280 int el = arm_current_el(env);
3281
3282 if (el == 0 && arm_el_is_aa64(env, 1)) {
3283 return aa64_generate_debug_exceptions(env);
3284 }
3285
3286 if (arm_is_secure(env)) {
3287 int spd;
3288
3289 if (el == 0 && (env->cp15.sder & 1)) {
3290
3291
3292
3293
3294 return true;
3295 }
3296
3297 spd = extract32(env->cp15.mdcr_el3, 14, 2);
3298 switch (spd) {
3299 case 1:
3300
3301 case 0:
3302
3303
3304
3305
3306
3307 return true;
3308 case 2:
3309 return false;
3310 case 3:
3311 return true;
3312 }
3313 }
3314
3315 return el != 2;
3316}
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3330{
3331 if (env->aarch64) {
3332 return aa64_generate_debug_exceptions(env);
3333 } else {
3334 return aa32_generate_debug_exceptions(env);
3335 }
3336}
3337
3338
3339
3340
3341static inline bool arm_singlestep_active(CPUARMState *env)
3342{
3343 return extract32(env->cp15.mdscr_el1, 0, 1)
3344 && arm_el_is_aa64(env, arm_debug_target_el(env))
3345 && arm_generate_debug_exceptions(env);
3346}
3347
3348static inline bool arm_sctlr_b(CPUARMState *env)
3349{
3350 return
3351
3352
3353
3354
3355#ifndef CONFIG_USER_ONLY
3356 !arm_feature(env, ARM_FEATURE_V7) &&
3357#endif
3358 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3359}
3360
3361uint64_t arm_sctlr(CPUARMState *env, int el);
3362
3363static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3364 bool sctlr_b)
3365{
3366#ifdef CONFIG_USER_ONLY
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379 if (sctlr_b) {
3380 return true;
3381 }
3382#endif
3383
3384 return env->uncached_cpsr & CPSR_E;
3385}
3386
3387static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3388{
3389 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3390}
3391
3392
3393static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3394{
3395 if (!is_a64(env)) {
3396 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3397 } else {
3398 int cur_el = arm_current_el(env);
3399 uint64_t sctlr = arm_sctlr(env, cur_el);
3400 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3401 }
3402}
3403
3404typedef CPUARMState CPUArchState;
3405typedef ARMCPU ArchCPU;
3406
3407#include "exec/cpu-all.h"
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
3434FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
3435FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1)
3436FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
3437FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
3438
3439FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
3440
3441FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
3442
3443FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1)
3444
3445
3446
3447
3448FIELD(TBFLAG_AM32, CONDEXEC, 24, 8)
3449FIELD(TBFLAG_AM32, THUMB, 23, 1)
3450
3451
3452
3453
3454FIELD(TBFLAG_A32, VECLEN, 0, 3)
3455FIELD(TBFLAG_A32, VECSTRIDE, 3, 2)
3456
3457
3458
3459
3460
3461
3462FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
3463FIELD(TBFLAG_A32, VFPEN, 7, 1)
3464FIELD(TBFLAG_A32, SCTLR__B, 8, 1)
3465FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
3466
3467
3468
3469
3470
3471FIELD(TBFLAG_A32, NS, 10, 1)
3472
3473
3474
3475
3476
3477FIELD(TBFLAG_M32, HANDLER, 0, 1)
3478
3479FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3480
3481FIELD(TBFLAG_M32, LSPACT, 2, 1)
3482
3483FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)
3484
3485FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)
3486
3487
3488
3489
3490FIELD(TBFLAG_A64, TBII, 0, 2)
3491FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3492FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3493FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3494FIELD(TBFLAG_A64, BT, 9, 1)
3495FIELD(TBFLAG_A64, BTYPE, 10, 2)
3496FIELD(TBFLAG_A64, TBID, 12, 2)
3497FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3498FIELD(TBFLAG_A64, ATA, 15, 1)
3499FIELD(TBFLAG_A64, TCMA, 16, 2)
3500FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3501FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3502
3503
3504
3505
3506#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
3507 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3508#define DP_TBFLAG_A64(DST, WHICH, VAL) \
3509 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
3510#define DP_TBFLAG_A32(DST, WHICH, VAL) \
3511 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3512#define DP_TBFLAG_M32(DST, WHICH, VAL) \
3513 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3514#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
3515 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
3516
3517#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
3518#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
3519#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3520#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3521#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3532{
3533 return EX_TBFLAG_ANY(env->hflags, MMUIDX);
3534}
3535
3536static inline bool bswap_code(bool sctlr_b)
3537{
3538#ifdef CONFIG_USER_ONLY
3539
3540
3541
3542
3543 return
3544#ifdef TARGET_WORDS_BIGENDIAN
3545 1 ^
3546#endif
3547 sctlr_b;
3548#else
3549
3550
3551
3552 return 0;
3553#endif
3554}
3555
3556#ifdef CONFIG_USER_ONLY
3557static inline bool arm_cpu_bswap_data(CPUARMState *env)
3558{
3559 return
3560#ifdef TARGET_WORDS_BIGENDIAN
3561 1 ^
3562#endif
3563 arm_cpu_data_is_big_endian(env);
3564}
3565#endif
3566
3567void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3568 target_ulong *cs_base, uint32_t *flags);
3569
3570enum {
3571 QEMU_PSCI_CONDUIT_DISABLED = 0,
3572 QEMU_PSCI_CONDUIT_SMC = 1,
3573 QEMU_PSCI_CONDUIT_HVC = 2,
3574};
3575
3576#ifndef CONFIG_USER_ONLY
3577
3578static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3579{
3580 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3581}
3582
3583
3584
3585
3586
3587static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3588{
3589 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3590}
3591#endif
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3604 void *opaque);
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3616 *opaque);
3617
3618
3619
3620
3621
3622void arm_rebuild_hflags(CPUARMState *env);
3623
3624
3625
3626
3627
3628static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3629{
3630 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3631}
3632
3633
3634
3635
3636
3637static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3638{
3639 return &env->vfp.zregs[regno].d[0];
3640}
3641
3642
3643
3644
3645
3646static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3647{
3648 return &env->vfp.zregs[regno].d[0];
3649}
3650
3651
3652extern const uint64_t pred_esz_masks[4];
3653
3654
3655static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
3656{
3657 return x;
3658}
3659
3660
3661
3662
3663
3664
3665#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
3666#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
3667
3668
3669
3670
3671#define PAGE_BTI PAGE_TARGET_1
3672#define PAGE_MTE PAGE_TARGET_2
3673
3674#ifdef TARGET_TAGGED_ADDRESSES
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
3687{
3688 ARMCPU *cpu = ARM_CPU(cs);
3689 if (cpu->env.tagged_addr_enable) {
3690
3691
3692
3693
3694 x &= sextract64(x, 0, 56);
3695 }
3696 return x;
3697}
3698#endif
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3720{
3721 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3722}
3723
3724static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3725{
3726 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3727}
3728
3729static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
3730{
3731
3732 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
3733}
3734
3735static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3736{
3737 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3738}
3739
3740static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3741{
3742 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3743}
3744
3745static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3746{
3747 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3748}
3749
3750static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3751{
3752 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3753}
3754
3755static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3756{
3757 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3758}
3759
3760static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3761{
3762 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3763}
3764
3765static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3766{
3767 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3768}
3769
3770static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3771{
3772 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3773}
3774
3775static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3776{
3777 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3778}
3779
3780static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3781{
3782 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3783}
3784
3785static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3786{
3787 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3788}
3789
3790static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3791{
3792 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3793}
3794
3795static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3796{
3797 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3798}
3799
3800static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
3801{
3802 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
3803}
3804
3805static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
3806{
3807 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
3808}
3809
3810static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
3811{
3812 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
3813}
3814
3815static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
3816{
3817 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
3818}
3819
3820static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
3821{
3822
3823
3824
3825
3826 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
3827}
3828
3829static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3830{
3831
3832 if (isar_feature_aa32_mprofile(id)) {
3833 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
3834 } else {
3835 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
3836 }
3837}
3838
3839static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
3840{
3841
3842
3843
3844
3845
3846 return isar_feature_aa32_mprofile(id) &&
3847 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
3848}
3849
3850static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
3851{
3852
3853
3854
3855
3856
3857 return isar_feature_aa32_mprofile(id) &&
3858 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
3859}
3860
3861static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3862{
3863
3864
3865
3866
3867 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3868}
3869
3870static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3871{
3872
3873 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3874}
3875
3876static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3877{
3878 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3879}
3880
3881static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3882{
3883
3884 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3885}
3886
3887static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3888{
3889
3890 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3891}
3892
3893static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3894{
3895
3896 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3897}
3898
3899static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3900{
3901
3902 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3903}
3904
3905static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3906{
3907 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3908}
3909
3910
3911
3912
3913
3914
3915static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3916{
3917 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3918}
3919
3920static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3921{
3922 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3923}
3924
3925
3926
3927
3928
3929
3930
3931
3932static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3933{
3934 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3935}
3936
3937static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3938{
3939 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3940}
3941
3942static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3943{
3944 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3945}
3946
3947static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3948{
3949 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3950}
3951
3952static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3953{
3954 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3955}
3956
3957static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
3958{
3959 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
3960}
3961
3962static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3963{
3964 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3965}
3966
3967static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3968{
3969 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3970}
3971
3972static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
3973{
3974
3975 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3976 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3977}
3978
3979static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
3980{
3981
3982 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3983 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3984}
3985
3986static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3987{
3988 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
3989}
3990
3991static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
3992{
3993 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
3994}
3995
3996static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
3997{
3998 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
3999}
4000
4001static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
4002{
4003 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
4004}
4005
4006static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
4007{
4008 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
4009}
4010
4011static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
4012{
4013 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
4014}
4015
4016
4017
4018
4019static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
4020{
4021 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
4022}
4023
4024static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
4025{
4026 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
4027}
4028
4029static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
4030{
4031 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
4032}
4033
4034static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
4035{
4036 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
4037}
4038
4039static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
4040{
4041 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
4042}
4043
4044static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
4045{
4046 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
4047}
4048
4049static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
4050{
4051 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
4052}
4053
4054static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
4055{
4056 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
4057}
4058
4059static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
4060{
4061 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
4062}
4063
4064static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
4065{
4066 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
4067}
4068
4069static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
4070{
4071 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
4072}
4073
4074static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
4075{
4076 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
4077}
4078
4079static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
4080{
4081 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
4082}
4083
4084static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
4085{
4086 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
4087}
4088
4089static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
4090{
4091 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
4092}
4093
4094static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
4095{
4096 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
4097}
4098
4099static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
4100{
4101 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
4102}
4103
4104static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
4105{
4106 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
4107}
4108
4109static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
4110{
4111
4112
4113
4114
4115 return (id->id_aa64isar1 &
4116 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
4117 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
4118 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
4119 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
4120}
4121
4122static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
4123{
4124
4125
4126
4127
4128 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
4129}
4130
4131static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
4132{
4133 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
4134}
4135
4136static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
4137{
4138 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
4139}
4140
4141static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
4142{
4143 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
4144}
4145
4146static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
4147{
4148 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
4149}
4150
4151static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
4152{
4153 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
4154}
4155
4156static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
4157{
4158 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
4159}
4160
4161static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
4162{
4163 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
4164}
4165
4166static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
4167{
4168 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
4169}
4170
4171static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
4172{
4173
4174 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
4175}
4176
4177static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
4178{
4179
4180 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
4181}
4182
4183static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
4184{
4185 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
4186}
4187
4188static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
4189{
4190 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
4191}
4192
4193static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
4194{
4195 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
4196}
4197
4198static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
4199{
4200 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
4201}
4202
4203static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
4204{
4205 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
4206}
4207
4208static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
4209{
4210 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
4211}
4212
4213static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
4214{
4215 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
4216}
4217
4218static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
4219{
4220 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
4221}
4222
4223static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
4224{
4225 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
4226}
4227
4228static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
4229{
4230 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
4231}
4232
4233static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
4234{
4235 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
4236}
4237
4238static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
4239{
4240 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
4241}
4242
4243static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
4244{
4245 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
4246}
4247
4248static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
4249{
4250 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
4251 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4252}
4253
4254static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
4255{
4256 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
4257 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4258}
4259
4260static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
4261{
4262 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
4263}
4264
4265static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
4266{
4267 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
4268}
4269
4270static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
4271{
4272 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
4273}
4274
4275static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
4276{
4277 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
4278}
4279
4280static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
4281{
4282 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
4283}
4284
4285static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
4286{
4287 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
4288}
4289
4290static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
4291{
4292 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
4293}
4294
4295static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
4296{
4297 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
4298}
4299
4300static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
4301{
4302 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
4303}
4304
4305static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
4306{
4307 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
4308}
4309
4310static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
4311{
4312 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
4313}
4314
4315static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
4316{
4317 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
4318}
4319
4320static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
4321{
4322 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
4323}
4324
4325static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
4326{
4327 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
4328}
4329
4330static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
4331{
4332 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
4333}
4334
4335static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
4336{
4337 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
4338}
4339
4340static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
4341{
4342 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
4343}
4344
4345
4346
4347
4348static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
4349{
4350 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
4351}
4352
4353static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
4354{
4355 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
4356}
4357
4358static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
4359{
4360 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
4361}
4362
4363static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
4364{
4365 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
4366}
4367
4368static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
4369{
4370 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
4371}
4372
4373static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
4374{
4375 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
4376}
4377
4378
4379
4380
4381#define cpu_isar_feature(name, cpu) \
4382 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
4383
4384#endif
4385