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21#ifndef QEMU_AVR_CPU_H
22#define QEMU_AVR_CPU_H
23
24#include "cpu-qom.h"
25#include "exec/cpu-defs.h"
26
27#ifdef CONFIG_USER_ONLY
28#error "AVR 8-bit does not support user mode"
29#endif
30
31#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
32#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
33#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
34
35#define TCG_GUEST_DEFAULT_MO 0
36
37
38
39
40
41
42
43#define MMU_CODE_IDX 0
44#define MMU_DATA_IDX 1
45
46#define EXCP_RESET 1
47#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
48
49
50#define NUMBER_OF_CPU_REGISTERS 32
51
52#define NUMBER_OF_IO_REGISTERS 64
53
54
55
56
57
58
59
60
61
62
63
64#define OFFSET_CODE 0x00000000
65
66#define OFFSET_DATA 0x00800000
67
68#define OFFSET_CPU_REGISTERS OFFSET_DATA
69
70
71
72
73#define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS)
74
75typedef enum AVRFeature {
76 AVR_FEATURE_SRAM,
77
78 AVR_FEATURE_1_BYTE_PC,
79 AVR_FEATURE_2_BYTE_PC,
80 AVR_FEATURE_3_BYTE_PC,
81
82 AVR_FEATURE_1_BYTE_SP,
83 AVR_FEATURE_2_BYTE_SP,
84
85 AVR_FEATURE_BREAK,
86 AVR_FEATURE_DES,
87 AVR_FEATURE_RMW,
88
89 AVR_FEATURE_EIJMP_EICALL,
90 AVR_FEATURE_IJMP_ICALL,
91 AVR_FEATURE_JMP_CALL,
92
93 AVR_FEATURE_ADIW_SBIW,
94
95 AVR_FEATURE_SPM,
96 AVR_FEATURE_SPMX,
97
98 AVR_FEATURE_ELPMX,
99 AVR_FEATURE_ELPM,
100 AVR_FEATURE_LPMX,
101 AVR_FEATURE_LPM,
102
103 AVR_FEATURE_MOVW,
104 AVR_FEATURE_MUL,
105 AVR_FEATURE_RAMPD,
106 AVR_FEATURE_RAMPX,
107 AVR_FEATURE_RAMPY,
108 AVR_FEATURE_RAMPZ,
109} AVRFeature;
110
111typedef struct CPUAVRState CPUAVRState;
112
113struct CPUAVRState {
114 uint32_t pc_w;
115
116 uint32_t sregC;
117 uint32_t sregZ;
118 uint32_t sregN;
119 uint32_t sregV;
120 uint32_t sregS;
121 uint32_t sregH;
122 uint32_t sregT;
123 uint32_t sregI;
124
125 uint32_t rampD;
126 uint32_t rampX;
127 uint32_t rampY;
128 uint32_t rampZ;
129 uint32_t eind;
130
131 uint32_t r[NUMBER_OF_CPU_REGISTERS];
132 uint32_t sp;
133
134 uint32_t skip;
135
136 uint64_t intsrc;
137 bool fullacc;
138
139 uint64_t features;
140};
141
142
143
144
145
146
147
148typedef struct AVRCPU {
149
150 CPUState parent_obj;
151
152
153 CPUNegativeOffsetState neg;
154 CPUAVRState env;
155} AVRCPU;
156
157extern const struct VMStateDescription vms_avr_cpu;
158
159void avr_cpu_do_interrupt(CPUState *cpu);
160bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
161hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
162int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
163int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
164int avr_print_insn(bfd_vma addr, disassemble_info *info);
165vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr);
166
167static inline int avr_feature(CPUAVRState *env, AVRFeature feature)
168{
169 return (env->features & (1U << feature)) != 0;
170}
171
172static inline void set_avr_feature(CPUAVRState *env, int feature)
173{
174 env->features |= (1U << feature);
175}
176
177#define cpu_list avr_cpu_list
178#define cpu_signal_handler cpu_avr_signal_handler
179#define cpu_mmu_index avr_cpu_mmu_index
180
181static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
182{
183 return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
184}
185
186void avr_cpu_tcg_init(void);
187
188void avr_cpu_list(void);
189int cpu_avr_exec(CPUState *cpu);
190int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc);
191int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf,
192 int len, bool is_write);
193
194enum {
195 TB_FLAGS_FULL_ACCESS = 1,
196 TB_FLAGS_SKIP = 2,
197};
198
199static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulong *pc,
200 target_ulong *cs_base, uint32_t *pflags)
201{
202 uint32_t flags = 0;
203
204 *pc = env->pc_w * 2;
205 *cs_base = 0;
206
207 if (env->fullacc) {
208 flags |= TB_FLAGS_FULL_ACCESS;
209 }
210 if (env->skip) {
211 flags |= TB_FLAGS_SKIP;
212 }
213
214 *pflags = flags;
215}
216
217static inline int cpu_interrupts_enabled(CPUAVRState *env)
218{
219 return env->sregI != 0;
220}
221
222static inline uint8_t cpu_get_sreg(CPUAVRState *env)
223{
224 uint8_t sreg;
225 sreg = (env->sregC) << 0
226 | (env->sregZ) << 1
227 | (env->sregN) << 2
228 | (env->sregV) << 3
229 | (env->sregS) << 4
230 | (env->sregH) << 5
231 | (env->sregT) << 6
232 | (env->sregI) << 7;
233 return sreg;
234}
235
236static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg)
237{
238 env->sregC = (sreg >> 0) & 0x01;
239 env->sregZ = (sreg >> 1) & 0x01;
240 env->sregN = (sreg >> 2) & 0x01;
241 env->sregV = (sreg >> 3) & 0x01;
242 env->sregS = (sreg >> 4) & 0x01;
243 env->sregH = (sreg >> 5) & 0x01;
244 env->sregT = (sreg >> 6) & 0x01;
245 env->sregI = (sreg >> 7) & 0x01;
246}
247
248bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
249 MMUAccessType access_type, int mmu_idx,
250 bool probe, uintptr_t retaddr);
251
252typedef CPUAVRState CPUArchState;
253typedef AVRCPU ArchCPU;
254
255#include "exec/cpu-all.h"
256
257#endif
258