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13#include "qemu/osdep.h"
14#include "qemu-common.h"
15#include "cpu.h"
16#include "hw/i386/apic_internal.h"
17#include "hw/i386/apic-msidef.h"
18#include "hw/pci/msi.h"
19#include "sysemu/hw_accel.h"
20#include "sysemu/whpx.h"
21#include "whpx-internal.h"
22
23struct whpx_lapic_state {
24 struct {
25 uint32_t data;
26 uint32_t padding[3];
27 } fields[256];
28};
29
30static void whpx_put_apic_state(APICCommonState *s,
31 struct whpx_lapic_state *kapic)
32{
33 int i;
34
35 memset(kapic, 0, sizeof(*kapic));
36 kapic->fields[0x2].data = s->id << 24;
37 kapic->fields[0x3].data = s->version | ((APIC_LVT_NB - 1) << 16);
38 kapic->fields[0x8].data = s->tpr;
39 kapic->fields[0xd].data = s->log_dest << 24;
40 kapic->fields[0xe].data = s->dest_mode << 28 | 0x0fffffff;
41 kapic->fields[0xf].data = s->spurious_vec;
42 for (i = 0; i < 8; i++) {
43 kapic->fields[0x10 + i].data = s->isr[i];
44 kapic->fields[0x18 + i].data = s->tmr[i];
45 kapic->fields[0x20 + i].data = s->irr[i];
46 }
47
48 kapic->fields[0x28].data = s->esr;
49 kapic->fields[0x30].data = s->icr[0];
50 kapic->fields[0x31].data = s->icr[1];
51 for (i = 0; i < APIC_LVT_NB; i++) {
52 kapic->fields[0x32 + i].data = s->lvt[i];
53 }
54
55 kapic->fields[0x38].data = s->initial_count;
56 kapic->fields[0x3e].data = s->divide_conf;
57}
58
59static void whpx_get_apic_state(APICCommonState *s,
60 struct whpx_lapic_state *kapic)
61{
62 int i, v;
63
64 s->id = kapic->fields[0x2].data >> 24;
65 s->tpr = kapic->fields[0x8].data;
66 s->arb_id = kapic->fields[0x9].data;
67 s->log_dest = kapic->fields[0xd].data >> 24;
68 s->dest_mode = kapic->fields[0xe].data >> 28;
69 s->spurious_vec = kapic->fields[0xf].data;
70 for (i = 0; i < 8; i++) {
71 s->isr[i] = kapic->fields[0x10 + i].data;
72 s->tmr[i] = kapic->fields[0x18 + i].data;
73 s->irr[i] = kapic->fields[0x20 + i].data;
74 }
75
76 s->esr = kapic->fields[0x28].data;
77 s->icr[0] = kapic->fields[0x30].data;
78 s->icr[1] = kapic->fields[0x31].data;
79 for (i = 0; i < APIC_LVT_NB; i++) {
80 s->lvt[i] = kapic->fields[0x32 + i].data;
81 }
82
83 s->initial_count = kapic->fields[0x38].data;
84 s->divide_conf = kapic->fields[0x3e].data;
85
86 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
87 s->count_shift = (v + 1) & 7;
88
89 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
90 apic_next_timer(s, s->initial_count_load_time);
91}
92
93static void whpx_apic_set_base(APICCommonState *s, uint64_t val)
94{
95 s->apicbase = val;
96}
97
98static void whpx_put_apic_base(CPUState *cpu, uint64_t val)
99{
100 HRESULT hr;
101 WHV_REGISTER_VALUE reg_value = {.Reg64 = val};
102 WHV_REGISTER_NAME reg_name = WHvX64RegisterApicBase;
103
104 hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
105 whpx_global.partition,
106 cpu->cpu_index,
107 ®_name, 1,
108 ®_value);
109
110 if (FAILED(hr)) {
111 error_report("WHPX: Failed to set MSR APIC base, hr=%08lx", hr);
112 }
113}
114
115static void whpx_apic_set_tpr(APICCommonState *s, uint8_t val)
116{
117 s->tpr = val;
118}
119
120static uint8_t whpx_apic_get_tpr(APICCommonState *s)
121{
122 return s->tpr;
123}
124
125static void whpx_apic_vapic_base_update(APICCommonState *s)
126{
127
128}
129
130static void whpx_apic_put(CPUState *cs, run_on_cpu_data data)
131{
132 APICCommonState *s = data.host_ptr;
133 struct whpx_lapic_state kapic;
134 HRESULT hr;
135
136 whpx_put_apic_base(CPU(s->cpu), s->apicbase);
137 whpx_put_apic_state(s, &kapic);
138
139 hr = whp_dispatch.WHvSetVirtualProcessorInterruptControllerState2(
140 whpx_global.partition,
141 cs->cpu_index,
142 &kapic,
143 sizeof(kapic));
144 if (FAILED(hr)) {
145 fprintf(stderr,
146 "WHvSetVirtualProcessorInterruptControllerState failed: %08lx\n",
147 hr);
148
149 abort();
150 }
151}
152
153void whpx_apic_get(DeviceState *dev)
154{
155 APICCommonState *s = APIC_COMMON(dev);
156 CPUState *cpu = CPU(s->cpu);
157 struct whpx_lapic_state kapic;
158
159 HRESULT hr = whp_dispatch.WHvGetVirtualProcessorInterruptControllerState2(
160 whpx_global.partition,
161 cpu->cpu_index,
162 &kapic,
163 sizeof(kapic),
164 NULL);
165 if (FAILED(hr)) {
166 fprintf(stderr,
167 "WHvSetVirtualProcessorInterruptControllerState failed: %08lx\n",
168 hr);
169
170 abort();
171 }
172
173 whpx_get_apic_state(s, &kapic);
174}
175
176static void whpx_apic_post_load(APICCommonState *s)
177{
178 run_on_cpu(CPU(s->cpu), whpx_apic_put, RUN_ON_CPU_HOST_PTR(s));
179}
180
181static void whpx_apic_external_nmi(APICCommonState *s)
182{
183}
184
185static void whpx_send_msi(MSIMessage *msg)
186{
187 uint64_t addr = msg->address;
188 uint32_t data = msg->data;
189 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
190 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
191 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
192 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
193 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
194
195 WHV_INTERRUPT_CONTROL interrupt = {
196
197 .Type = delivery,
198 .DestinationMode = dest_mode ?
199 WHvX64InterruptDestinationModeLogical :
200 WHvX64InterruptDestinationModePhysical,
201
202 .TriggerMode = trigger_mode ?
203 WHvX64InterruptTriggerModeLevel : WHvX64InterruptTriggerModeEdge,
204 .Reserved = 0,
205 .Vector = vector,
206 .Destination = dest,
207 };
208 HRESULT hr = whp_dispatch.WHvRequestInterrupt(whpx_global.partition,
209 &interrupt, sizeof(interrupt));
210 if (FAILED(hr)) {
211 fprintf(stderr, "whpx: injection failed, MSI (%llx, %x) delivery: %d, "
212 "dest_mode: %d, trigger mode: %d, vector: %d, lost (%08lx)\n",
213 addr, data, delivery, dest_mode, trigger_mode, vector, hr);
214 }
215}
216
217static uint64_t whpx_apic_mem_read(void *opaque, hwaddr addr,
218 unsigned size)
219{
220 return ~(uint64_t)0;
221}
222
223static void whpx_apic_mem_write(void *opaque, hwaddr addr,
224 uint64_t data, unsigned size)
225{
226 MSIMessage msg = { .address = addr, .data = data };
227 whpx_send_msi(&msg);
228}
229
230static const MemoryRegionOps whpx_apic_io_ops = {
231 .read = whpx_apic_mem_read,
232 .write = whpx_apic_mem_write,
233 .endianness = DEVICE_NATIVE_ENDIAN,
234};
235
236static void whpx_apic_reset(APICCommonState *s)
237{
238
239 s->wait_for_sipi = 0;
240
241 run_on_cpu(CPU(s->cpu), whpx_apic_put, RUN_ON_CPU_HOST_PTR(s));
242}
243
244static void whpx_apic_realize(DeviceState *dev, Error **errp)
245{
246 APICCommonState *s = APIC_COMMON(dev);
247
248 memory_region_init_io(&s->io_memory, OBJECT(s), &whpx_apic_io_ops, s,
249 "whpx-apic-msi", APIC_SPACE_SIZE);
250
251 msi_nonbroken = true;
252}
253
254static void whpx_apic_class_init(ObjectClass *klass, void *data)
255{
256 APICCommonClass *k = APIC_COMMON_CLASS(klass);
257
258 k->realize = whpx_apic_realize;
259 k->reset = whpx_apic_reset;
260 k->set_base = whpx_apic_set_base;
261 k->set_tpr = whpx_apic_set_tpr;
262 k->get_tpr = whpx_apic_get_tpr;
263 k->post_load = whpx_apic_post_load;
264 k->vapic_base_update = whpx_apic_vapic_base_update;
265 k->external_nmi = whpx_apic_external_nmi;
266 k->send_msi = whpx_send_msi;
267}
268
269static const TypeInfo whpx_apic_info = {
270 .name = "whpx-apic",
271 .parent = TYPE_APIC_COMMON,
272 .instance_size = sizeof(APICCommonState),
273 .class_init = whpx_apic_class_init,
274};
275
276static void whpx_apic_register_types(void)
277{
278 type_register_static(&whpx_apic_info);
279}
280
281type_init(whpx_apic_register_types)
282
