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21#ifndef M68K_CPU_H
22#define M68K_CPU_H
23
24#include "exec/cpu-defs.h"
25#include "cpu-qom.h"
26
27#define OS_BYTE 0
28#define OS_WORD 1
29#define OS_LONG 2
30#define OS_SINGLE 3
31#define OS_DOUBLE 4
32#define OS_EXTENDED 5
33#define OS_PACKED 6
34#define OS_UNSIZED 7
35
36#define EXCP_ACCESS 2
37#define EXCP_ADDRESS 3
38#define EXCP_ILLEGAL 4
39#define EXCP_DIV0 5
40#define EXCP_CHK 6
41#define EXCP_TRAPCC 7
42#define EXCP_PRIVILEGE 8
43#define EXCP_TRACE 9
44#define EXCP_LINEA 10
45#define EXCP_LINEF 11
46#define EXCP_DEBUGNBP 12
47#define EXCP_DEBEGBP 13
48#define EXCP_FORMAT 14
49#define EXCP_UNINITIALIZED 15
50#define EXCP_SPURIOUS 24
51#define EXCP_INT_LEVEL_1 25
52#define EXCP_INT_LEVEL_7 31
53#define EXCP_TRAP0 32
54#define EXCP_TRAP15 47
55#define EXCP_FP_BSUN 48
56#define EXCP_FP_INEX 49
57#define EXCP_FP_DZ 50
58#define EXCP_FP_UNFL 51
59#define EXCP_FP_OPERR 52
60#define EXCP_FP_OVFL 53
61#define EXCP_FP_SNAN 54
62#define EXCP_FP_UNIMP 55
63#define EXCP_MMU_CONF 56
64#define EXCP_MMU_ILLEGAL 57
65#define EXCP_MMU_ACCESS 58
66
67#define EXCP_RTE 0x100
68#define EXCP_HALT_INSN 0x101
69
70#define M68K_DTTR0 0
71#define M68K_DTTR1 1
72#define M68K_ITTR0 2
73#define M68K_ITTR1 3
74
75#define M68K_MAX_TTR 2
76#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
77
78#define TARGET_INSN_START_EXTRA_WORDS 1
79
80typedef CPU_LDoubleU FPReg;
81
82typedef struct CPUM68KState {
83 uint32_t dregs[8];
84 uint32_t aregs[8];
85 uint32_t pc;
86 uint32_t sr;
87
88
89
90
91
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93
94
95 int current_sp;
96 uint32_t sp[3];
97
98
99 uint32_t cc_op;
100 uint32_t cc_x;
101 uint32_t cc_n;
102 uint32_t cc_v;
103 uint32_t cc_c;
104 uint32_t cc_z;
105
106 FPReg fregs[8];
107 FPReg fp_result;
108 uint32_t fpcr;
109 uint32_t fpsr;
110 float_status fp_status;
111
112 uint64_t mactmp;
113
114
115
116
117
118 uint64_t macc[4];
119 uint32_t macsr;
120 uint32_t mac_mask;
121
122
123 struct {
124 uint32_t ar;
125 uint32_t ssw;
126
127 uint16_t tcr;
128 uint32_t urp;
129 uint32_t srp;
130 bool fault;
131 uint32_t ttr[4];
132 uint32_t mmusr;
133 } mmu;
134
135
136 uint32_t vbr;
137 uint32_t mbar;
138 uint32_t rambar0;
139 uint32_t cacr;
140 uint32_t sfc;
141 uint32_t dfc;
142
143 int pending_vector;
144 int pending_level;
145
146
147 struct {} end_reset_fields;
148
149
150 uint32_t features;
151} CPUM68KState;
152
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157
158
159struct M68kCPU {
160
161 CPUState parent_obj;
162
163
164 CPUNegativeOffsetState neg;
165 CPUM68KState env;
166};
167
168
169void m68k_cpu_do_interrupt(CPUState *cpu);
170bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
171void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
172hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
173int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
174int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
175
176void m68k_tcg_init(void);
177void m68k_cpu_init_gdb(M68kCPU *cpu);
178
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182
183int cpu_m68k_signal_handler(int host_signum, void *pinfo,
184 void *puc);
185uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
186void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
187void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
188void cpu_m68k_restore_fp_status(CPUM68KState *env);
189void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
190
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198
199
200typedef enum {
201
202 CC_OP_DYNAMIC,
203
204
205 CC_OP_FLAGS,
206
207
208 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
209 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
210
211
212 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
213
214
215 CC_OP_LOGIC,
216
217 CC_OP_NB
218} CCOp;
219
220#define CCF_C 0x01
221#define CCF_V 0x02
222#define CCF_Z 0x04
223#define CCF_N 0x08
224#define CCF_X 0x10
225
226#define SR_I_SHIFT 8
227#define SR_I 0x0700
228#define SR_M 0x1000
229#define SR_S 0x2000
230#define SR_T_SHIFT 14
231#define SR_T 0xc000
232
233#define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT)
234#define M68K_SR_TRACE_ANY_INS 0x2
235
236#define M68K_SSP 0
237#define M68K_USP 1
238#define M68K_ISP 2
239
240
241#define M68K_CP_040 0x8000
242#define M68K_CU_040 0x4000
243#define M68K_CT_040 0x2000
244#define M68K_CM_040 0x1000
245#define M68K_MA_040 0x0800
246#define M68K_ATC_040 0x0400
247#define M68K_LK_040 0x0200
248#define M68K_RW_040 0x0100
249#define M68K_SIZ_040 0x0060
250#define M68K_TT_040 0x0018
251#define M68K_TM_040 0x0007
252
253#define M68K_TM_040_DATA 0x0001
254#define M68K_TM_040_CODE 0x0002
255#define M68K_TM_040_SUPER 0x0004
256
257
258#define M68K_WBV_040 0x80
259#define M68K_WBSIZ_040 0x60
260#define M68K_WBBYT_040 0x20
261#define M68K_WBWRD_040 0x40
262#define M68K_WBLNG_040 0x00
263#define M68K_WBTT_040 0x18
264#define M68K_WBTM_040 0x07
265
266
267#define M68K_BA_SIZE_MASK 0x60
268#define M68K_BA_SIZE_BYTE 0x20
269#define M68K_BA_SIZE_WORD 0x40
270#define M68K_BA_SIZE_LONG 0x00
271#define M68K_BA_SIZE_LINE 0x60
272
273
274#define M68K_BA_TT_MOVE16 0x08
275
276
277#define M68K_MMU_B_040 0x0800
278#define M68K_MMU_G_040 0x0400
279#define M68K_MMU_U1_040 0x0200
280#define M68K_MMU_U0_040 0x0100
281#define M68K_MMU_S_040 0x0080
282#define M68K_MMU_CM_040 0x0060
283#define M68K_MMU_M_040 0x0010
284#define M68K_MMU_WP_040 0x0004
285#define M68K_MMU_T_040 0x0002
286#define M68K_MMU_R_040 0x0001
287
288#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \
289 M68K_MMU_U0_040 | M68K_MMU_S_040 | \
290 M68K_MMU_CM_040 | M68K_MMU_M_040 | \
291 M68K_MMU_WP_040)
292
293
294#define M68K_TCR_ENABLED 0x8000
295#define M68K_TCR_PAGE_8K 0x4000
296
297
298#define M68K_DESC_WRITEPROT 0x00000004
299#define M68K_DESC_USED 0x00000008
300#define M68K_DESC_MODIFIED 0x00000010
301#define M68K_DESC_CACHEMODE 0x00000060
302#define M68K_DESC_CM_WRTHRU 0x00000000
303#define M68K_DESC_CM_COPYBK 0x00000020
304#define M68K_DESC_CM_SERIAL 0x00000040
305#define M68K_DESC_CM_NCACHE 0x00000060
306#define M68K_DESC_SUPERONLY 0x00000080
307#define M68K_DESC_USERATTR 0x00000300
308#define M68K_DESC_USERATTR_SHIFT 8
309#define M68K_DESC_GLOBAL 0x00000400
310#define M68K_DESC_URESERVED 0x00000800
311
312#define M68K_ROOT_POINTER_ENTRIES 128
313#define M68K_4K_PAGE_MASK (~0xff)
314#define M68K_POINTER_BASE(entry) (entry & ~0x1ff)
315#define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc)
316#define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc)
317#define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK)
318#define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc)
319#define M68K_8K_PAGE_MASK (~0x7f)
320#define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK)
321#define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c)
322#define M68K_UDT_VALID(entry) (entry & 2)
323#define M68K_PDT_VALID(entry) (entry & 3)
324#define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2)
325#define M68K_INDIRECT_POINTER(addr) (addr & ~3)
326#define M68K_TTS_POINTER_SHIFT 18
327#define M68K_TTS_ROOT_SHIFT 25
328
329
330#define M68K_TTR_ADDR_BASE 0xff000000
331#define M68K_TTR_ADDR_MASK 0x00ff0000
332#define M68K_TTR_ADDR_MASK_SHIFT 8
333#define M68K_TTR_ENABLED 0x00008000
334#define M68K_TTR_SFIELD 0x00006000
335#define M68K_TTR_SFIELD_USER 0x0000
336#define M68K_TTR_SFIELD_SUPER 0x2000
337
338
339
340
341
342#define M68K_CR_ASID 0x003
343#define M68K_CR_ACR0 0x004
344#define M68K_CR_ACR1 0x005
345#define M68K_CR_ACR2 0x006
346#define M68K_CR_ACR3 0x007
347#define M68K_CR_MMUBAR 0x008
348
349
350#define M68K_CR_PC 0x80F
351
352
353#define M68K_CR_ROMBAR0 0xC00
354#define M68K_CR_ROMBAR1 0xC01
355#define M68K_CR_RAMBAR0 0xC04
356#define M68K_CR_RAMBAR1 0xC05
357#define M68K_CR_MPCR 0xC0C
358#define M68K_CR_EDRAMBAR 0xC0D
359#define M68K_CR_SECMBAR 0xC0E
360#define M68K_CR_MBAR 0xC0F
361
362
363#define M68K_CR_PCR1U0 0xD02
364#define M68K_CR_PCR1L0 0xD03
365#define M68K_CR_PCR2U0 0xD04
366#define M68K_CR_PCR2L0 0xD05
367#define M68K_CR_PCR3U0 0xD06
368#define M68K_CR_PCR3L0 0xD07
369#define M68K_CR_PCR1U1 0xD0A
370#define M68K_CR_PCR1L1 0xD0B
371#define M68K_CR_PCR2U1 0xD0C
372#define M68K_CR_PCR2L1 0xD0D
373#define M68K_CR_PCR3U1 0xD0E
374#define M68K_CR_PCR3L1 0xD0F
375
376
377
378#define M68K_CR_SFC 0x000
379#define M68K_CR_DFC 0x001
380#define M68K_CR_USP 0x800
381#define M68K_CR_VBR 0x801
382
383
384#define M68K_CR_CACR 0x002
385#define M68K_CR_CAAR 0x802
386#define M68K_CR_MSP 0x803
387#define M68K_CR_ISP 0x804
388
389
390#define M68K_CR_TC 0x003
391#define M68K_CR_ITT0 0x004
392#define M68K_CR_ITT1 0x005
393#define M68K_CR_DTT0 0x006
394#define M68K_CR_DTT1 0x007
395#define M68K_CR_MMUSR 0x805
396#define M68K_CR_URP 0x806
397#define M68K_CR_SRP 0x807
398
399
400#define M68K_CR_IACR0 0x004
401#define M68K_CR_IACR1 0x005
402#define M68K_CR_DACR0 0x006
403#define M68K_CR_DACR1 0x007
404
405
406#define M68K_CR_BUSCR 0x008
407#define M68K_CR_PCR 0x808
408
409#define M68K_FPIAR_SHIFT 0
410#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)
411#define M68K_FPSR_SHIFT 1
412#define M68K_FPSR (1 << M68K_FPSR_SHIFT)
413#define M68K_FPCR_SHIFT 2
414#define M68K_FPCR (1 << M68K_FPCR_SHIFT)
415
416
417
418
419#define FPSR_CC_MASK 0x0f000000
420#define FPSR_CC_A 0x01000000
421#define FPSR_CC_I 0x02000000
422#define FPSR_CC_Z 0x04000000
423#define FPSR_CC_N 0x08000000
424
425
426
427#define FPSR_QT_MASK 0x00ff0000
428#define FPSR_QT_SHIFT 16
429
430
431
432#define FPCR_RND_MASK 0x0030
433#define FPCR_RND_N 0x0000
434#define FPCR_RND_Z 0x0010
435#define FPCR_RND_M 0x0020
436#define FPCR_RND_P 0x0030
437
438
439#define FPCR_PREC_MASK 0x00c0
440#define FPCR_PREC_X 0x0000
441#define FPCR_PREC_S 0x0040
442#define FPCR_PREC_D 0x0080
443#define FPCR_PREC_U 0x00c0
444
445#define FPCR_EXCP_MASK 0xff00
446
447
448#define M68K_CACR_EUSP 0x10
449
450#define MACSR_PAV0 0x100
451#define MACSR_OMC 0x080
452#define MACSR_SU 0x040
453#define MACSR_FI 0x020
454#define MACSR_RT 0x010
455#define MACSR_N 0x008
456#define MACSR_Z 0x004
457#define MACSR_V 0x002
458#define MACSR_EV 0x001
459
460void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
461void m68k_switch_sp(CPUM68KState *env);
462
463void do_m68k_semihosting(CPUM68KState *env, int nr);
464
465
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477
478
479
480enum m68k_features {
481
482 M68K_FEATURE_M68000,
483 M68K_FEATURE_M68010,
484 M68K_FEATURE_M68020,
485 M68K_FEATURE_M68030,
486 M68K_FEATURE_M68040,
487 M68K_FEATURE_M68060,
488
489 M68K_FEATURE_CF_ISA_A,
490
491 M68K_FEATURE_CF_ISA_B,
492
493 M68K_FEATURE_CF_ISA_APLUSC,
494
495 M68K_FEATURE_BRAL,
496 M68K_FEATURE_CF_FPU,
497 M68K_FEATURE_CF_MAC,
498 M68K_FEATURE_CF_EMAC,
499
500 M68K_FEATURE_CF_EMAC_B,
501
502 M68K_FEATURE_USP,
503
504 M68K_FEATURE_MSP,
505
506 M68K_FEATURE_EXT_FULL,
507
508 M68K_FEATURE_WORD_INDEX,
509
510 M68K_FEATURE_SCALED_INDEX,
511
512 M68K_FEATURE_LONG_MULDIV,
513
514 M68K_FEATURE_QUAD_MULDIV,
515
516 M68K_FEATURE_BCCL,
517
518 M68K_FEATURE_BITFIELD,
519
520 M68K_FEATURE_FPU,
521
522 M68K_FEATURE_CAS,
523
524 M68K_FEATURE_BKPT,
525
526 M68K_FEATURE_RTD,
527
528 M68K_FEATURE_CHK2,
529
530 M68K_FEATURE_MOVEP,
531
532 M68K_FEATURE_MOVEC,
533
534 M68K_FEATURE_UNALIGNED_DATA,
535};
536
537static inline int m68k_feature(CPUM68KState *env, int feature)
538{
539 return (env->features & (1u << feature)) != 0;
540}
541
542void m68k_cpu_list(void);
543
544void register_m68k_insns (CPUM68KState *env);
545
546enum {
547
548 ACCESS_SUPER = 0x01,
549
550 ACCESS_STORE = 0x02,
551
552 ACCESS_DEBUG = 0x04,
553
554 ACCESS_PTEST = 0x08,
555
556 ACCESS_CODE = 0x10,
557 ACCESS_DATA = 0x20,
558};
559
560#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
561#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
562#define CPU_RESOLVING_TYPE TYPE_M68K_CPU
563
564#define cpu_signal_handler cpu_m68k_signal_handler
565#define cpu_list m68k_cpu_list
566
567
568#define MMU_KERNEL_IDX 0
569#define MMU_USER_IDX 1
570static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
571{
572 return (env->sr & SR_S) == 0 ? 1 : 0;
573}
574
575bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
576 MMUAccessType access_type, int mmu_idx,
577 bool probe, uintptr_t retaddr);
578void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
579 unsigned size, MMUAccessType access_type,
580 int mmu_idx, MemTxAttrs attrs,
581 MemTxResult response, uintptr_t retaddr);
582
583typedef CPUM68KState CPUArchState;
584typedef M68kCPU ArchCPU;
585
586#include "exec/cpu-all.h"
587
588
589#define TB_FLAGS_MACSR 0x0f
590#define TB_FLAGS_MSR_S_BIT 13
591#define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT)
592#define TB_FLAGS_SFC_S_BIT 14
593#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)
594#define TB_FLAGS_DFC_S_BIT 15
595#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)
596#define TB_FLAGS_TRACE 16
597#define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE)
598
599static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
600 target_ulong *cs_base, uint32_t *flags)
601{
602 *pc = env->pc;
603 *cs_base = 0;
604 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
605 if (env->sr & SR_S) {
606 *flags |= TB_FLAGS_MSR_S;
607 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
608 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
609 }
610 if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
611 *flags |= TB_FLAGS_TRACE;
612 }
613}
614
615void dump_mmu(CPUM68KState *env);
616
617#endif
618