LXR qemu/target/mips/tcg/tcg-internal.h

   1/*
   2 * MIPS internal definitions and helpers (TCG accelerator)
   3 *
   4 * SPDX-License-Identifier: GPL-2.0-or-later
   5 *
   6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7 * See the COPYING file in the top-level directory.
   8 */
   9
  10#ifndef MIPS_TCG_INTERNAL_H
  11#define MIPS_TCG_INTERNAL_H
  12
  13#include "tcg/tcg.h"
  14#include "exec/memattrs.h"
  15#include "hw/core/cpu.h"
  16#include "cpu.h"
  17
  18void mips_tcg_init(void);
  19
  20void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
  21void mips_cpu_do_interrupt(CPUState *cpu);
  22bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
  23bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
  24                       MMUAccessType access_type, int mmu_idx,
  25                       bool probe, uintptr_t retaddr);
  26void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
  27                                  MMUAccessType access_type,
  28                                  int mmu_idx, uintptr_t retaddr);
  29
  30const char *mips_exception_name(int32_t exception);
  31
  32void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  33                                          int error_code, uintptr_t pc);
  34
  35static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  36                                                    uint32_t exception,
  37                                                    uintptr_t pc)
  38{
  39    do_raise_exception_err(env, exception, 0, pc);
  40}
  41
  42#if !defined(CONFIG_USER_ONLY)
  43
  44void mmu_init(CPUMIPSState *env, const mips_def_t *def);
  45
  46void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
  47
  48void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
  49uint32_t cpu_mips_get_random(CPUMIPSState *env);
  50
  51bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb);
  52
  53hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
  54                                  MMUAccessType access_type, uintptr_t retaddr);
  55void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
  56                                    vaddr addr, unsigned size,
  57                                    MMUAccessType access_type,
  58                                    int mmu_idx, MemTxAttrs attrs,
  59                                    MemTxResult response, uintptr_t retaddr);
  60void cpu_mips_tlb_flush(CPUMIPSState *env);
  61
  62#endif /* !CONFIG_USER_ONLY */
  63
  64#endif
  65