LXR qemu/target/ppc/cpu

   1/*
   2 *  PowerPC CPU initialization for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *  Copyright 2011 Freescale Semiconductor, Inc.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2.1 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "disas/dis-asm.h"
  23#include "exec/gdbstub.h"
  24#include "kvm_ppc.h"
  25#include "sysemu/arch_init.h"
  26#include "sysemu/cpus.h"
  27#include "sysemu/hw_accel.h"
  28#include "sysemu/tcg.h"
  29#include "cpu-models.h"
  30#include "mmu-hash32.h"
  31#include "mmu-hash64.h"
  32#include "qemu/error-report.h"
  33#include "qemu/module.h"
  34#include "qemu/qemu-print.h"
  35#include "qapi/error.h"
  36#include "qapi/qmp/qnull.h"
  37#include "qapi/visitor.h"
  38#include "hw/qdev-properties.h"
  39#include "hw/ppc/ppc.h"
  40#include "mmu-book3s-v3.h"
  41#include "qemu/cutils.h"
  42#include "disas/capstone.h"
  43#include "fpu/softfloat.h"
  44#include "qapi/qapi-commands-machine-target.h"
  45
  46#include "helper_regs.h"
  47#include "internal.h"
  48#include "spr_tcg.h"
  49
  50/* #define PPC_DEBUG_SPR */
  51/* #define USE_APPLE_GDB */
  52
  53static inline void vscr_init(CPUPPCState *env, uint32_t val)
  54{
  55    /* Altivec always uses round-to-nearest */
  56    set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
  57    ppc_store_vscr(env, val);
  58}
  59
  60/**
  61 * _spr_register
  62 *
  63 * Register an SPR with all the callbacks required for tcg,
  64 * and the ID number for KVM.
  65 *
  66 * The reason for the conditional compilation is that the tcg functions
  67 * may be compiled out, and the system kvm header may not be available
  68 * for supplying the ID numbers.  This is ugly, but the best we can do.
  69 */
  70
  71#ifdef CONFIG_TCG
  72# define USR_ARG(X)    X,
  73# ifdef CONFIG_USER_ONLY
  74#  define SYS_ARG(X)
  75# else
  76#  define SYS_ARG(X)   X,
  77# endif
  78#else
  79# define USR_ARG(X)
  80# define SYS_ARG(X)
  81#endif
  82#ifdef CONFIG_KVM
  83# define KVM_ARG(X)    X,
  84#else
  85# define KVM_ARG(X)
  86#endif
  87
  88typedef void spr_callback(DisasContext *, int, int);
  89
  90static void _spr_register(CPUPPCState *env, int num, const char *name,
  91                          USR_ARG(spr_callback *uea_read)
  92                          USR_ARG(spr_callback *uea_write)
  93                          SYS_ARG(spr_callback *oea_read)
  94                          SYS_ARG(spr_callback *oea_write)
  95                          SYS_ARG(spr_callback *hea_read)
  96                          SYS_ARG(spr_callback *hea_write)
  97                          KVM_ARG(uint64_t one_reg_id)
  98                          target_ulong initial_value)
  99{
 100    ppc_spr_t *spr = &env->spr_cb[num];
 101
 102    /* No SPR should be registered twice. */
 103    assert(spr->name == NULL);
 104    assert(name != NULL);
 105
 106    spr->name = name;
 107    spr->default_value = initial_value;
 108    env->spr[num] = initial_value;
 109
 110#ifdef CONFIG_TCG
 111    spr->uea_read = uea_read;
 112    spr->uea_write = uea_write;
 113# ifndef CONFIG_USER_ONLY
 114    spr->oea_read = oea_read;
 115    spr->oea_write = oea_write;
 116    spr->hea_read = hea_read;
 117    spr->hea_write = hea_write;
 118# endif
 119#endif
 120#ifdef CONFIG_KVM
 121    spr->one_reg_id = one_reg_id;
 122#endif
 123}
 124
 125/* spr_register_kvm_hv passes all required arguments. */
 126#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,             \
 127                            oea_read, oea_write, hea_read, hea_write,        \
 128                            one_reg_id, initial_value)                       \
 129    _spr_register(env, num, name,                                            \
 130                  USR_ARG(uea_read) USR_ARG(uea_write)                       \
 131                  SYS_ARG(oea_read) SYS_ARG(oea_write)                       \
 132                  SYS_ARG(hea_read) SYS_ARG(hea_write)                       \
 133                  KVM_ARG(one_reg_id) initial_value)
 134
 135/* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
 136#define spr_register_kvm(env, num, name, uea_read, uea_write,                \
 137                         oea_read, oea_write, one_reg_id, ival)              \
 138    spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read,       \
 139                        oea_write, oea_read, oea_write, one_reg_id, ival)
 140
 141/* spr_register_hv and spr_register are similar, except there is no kvm id. */
 142#define spr_register_hv(env, num, name, uea_read, uea_write,                 \
 143                        oea_read, oea_write, hea_read, hea_write, ival)      \
 144    spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read,       \
 145                        oea_write, hea_read, hea_write, 0, ival)
 146
 147#define spr_register(env, num, name, uea_read, uea_write,                    \
 148                     oea_read, oea_write, ival)                              \
 149    spr_register_kvm(env, num, name, uea_read, uea_write,                    \
 150                     oea_read, oea_write, 0, ival)
 151
 152/* Generic PowerPC SPRs */
 153static void register_generic_sprs(CPUPPCState *env)
 154{
 155    /* Integer processing */
 156    spr_register(env, SPR_XER, "XER",
 157                 &spr_read_xer, &spr_write_xer,
 158                 &spr_read_xer, &spr_write_xer,
 159                 0x00000000);
 160    /* Branch control */
 161    spr_register(env, SPR_LR, "LR",
 162                 &spr_read_lr, &spr_write_lr,
 163                 &spr_read_lr, &spr_write_lr,
 164                 0x00000000);
 165    spr_register(env, SPR_CTR, "CTR",
 166                 &spr_read_ctr, &spr_write_ctr,
 167                 &spr_read_ctr, &spr_write_ctr,
 168                 0x00000000);
 169    /* Interrupt processing */
 170    spr_register(env, SPR_SRR0, "SRR0",
 171                 SPR_NOACCESS, SPR_NOACCESS,
 172                 &spr_read_generic, &spr_write_generic,
 173                 0x00000000);
 174    spr_register(env, SPR_SRR1, "SRR1",
 175                 SPR_NOACCESS, SPR_NOACCESS,
 176                 &spr_read_generic, &spr_write_generic,
 177                 0x00000000);
 178    /* Processor control */
 179    spr_register(env, SPR_SPRG0, "SPRG0",
 180                 SPR_NOACCESS, SPR_NOACCESS,
 181                 &spr_read_generic, &spr_write_generic,
 182                 0x00000000);
 183    spr_register(env, SPR_SPRG1, "SPRG1",
 184                 SPR_NOACCESS, SPR_NOACCESS,
 185                 &spr_read_generic, &spr_write_generic,
 186                 0x00000000);
 187    spr_register(env, SPR_SPRG2, "SPRG2",
 188                 SPR_NOACCESS, SPR_NOACCESS,
 189                 &spr_read_generic, &spr_write_generic,
 190                 0x00000000);
 191    spr_register(env, SPR_SPRG3, "SPRG3",
 192                 SPR_NOACCESS, SPR_NOACCESS,
 193                 &spr_read_generic, &spr_write_generic,
 194                 0x00000000);
 195}
 196
 197/* SPR common to all non-embedded PowerPC, including 601 */
 198static void register_ne_601_sprs(CPUPPCState *env)
 199{
 200    /* Exception processing */
 201    spr_register_kvm(env, SPR_DSISR, "DSISR",
 202                     SPR_NOACCESS, SPR_NOACCESS,
 203                     &spr_read_generic, &spr_write_generic,
 204                     KVM_REG_PPC_DSISR, 0x00000000);
 205    spr_register_kvm(env, SPR_DAR, "DAR",
 206                     SPR_NOACCESS, SPR_NOACCESS,
 207                     &spr_read_generic, &spr_write_generic,
 208                     KVM_REG_PPC_DAR, 0x00000000);
 209    /* Timer */
 210    spr_register(env, SPR_DECR, "DECR",
 211                 SPR_NOACCESS, SPR_NOACCESS,
 212                 &spr_read_decr, &spr_write_decr,
 213                 0x00000000);
 214}
 215
 216/* Storage Description Register 1 */
 217static void register_sdr1_sprs(CPUPPCState *env)
 218{
 219#ifndef CONFIG_USER_ONLY
 220    if (env->has_hv_mode) {
 221        /*
 222         * SDR1 is a hypervisor resource on CPUs which have a
 223         * hypervisor mode
 224         */
 225        spr_register_hv(env, SPR_SDR1, "SDR1",
 226                        SPR_NOACCESS, SPR_NOACCESS,
 227                        SPR_NOACCESS, SPR_NOACCESS,
 228                        &spr_read_generic, &spr_write_sdr1,
 229                        0x00000000);
 230    } else {
 231        spr_register(env, SPR_SDR1, "SDR1",
 232                     SPR_NOACCESS, SPR_NOACCESS,
 233                     &spr_read_generic, &spr_write_sdr1,
 234                     0x00000000);
 235    }
 236#endif
 237}
 238
 239/* BATs 0-3 */
 240static void register_low_BATs(CPUPPCState *env)
 241{
 242#if !defined(CONFIG_USER_ONLY)
 243    spr_register(env, SPR_IBAT0U, "IBAT0U",
 244                 SPR_NOACCESS, SPR_NOACCESS,
 245                 &spr_read_ibat, &spr_write_ibatu,
 246                 0x00000000);
 247    spr_register(env, SPR_IBAT0L, "IBAT0L",
 248                 SPR_NOACCESS, SPR_NOACCESS,
 249                 &spr_read_ibat, &spr_write_ibatl,
 250                 0x00000000);
 251    spr_register(env, SPR_IBAT1U, "IBAT1U",
 252                 SPR_NOACCESS, SPR_NOACCESS,
 253                 &spr_read_ibat, &spr_write_ibatu,
 254                 0x00000000);
 255    spr_register(env, SPR_IBAT1L, "IBAT1L",
 256                 SPR_NOACCESS, SPR_NOACCESS,
 257                 &spr_read_ibat, &spr_write_ibatl,
 258                 0x00000000);
 259    spr_register(env, SPR_IBAT2U, "IBAT2U",
 260                 SPR_NOACCESS, SPR_NOACCESS,
 261                 &spr_read_ibat, &spr_write_ibatu,
 262                 0x00000000);
 263    spr_register(env, SPR_IBAT2L, "IBAT2L",
 264                 SPR_NOACCESS, SPR_NOACCESS,
 265                 &spr_read_ibat, &spr_write_ibatl,
 266                 0x00000000);
 267    spr_register(env, SPR_IBAT3U, "IBAT3U",
 268                 SPR_NOACCESS, SPR_NOACCESS,
 269                 &spr_read_ibat, &spr_write_ibatu,
 270                 0x00000000);
 271    spr_register(env, SPR_IBAT3L, "IBAT3L",
 272                 SPR_NOACCESS, SPR_NOACCESS,
 273                 &spr_read_ibat, &spr_write_ibatl,
 274                 0x00000000);
 275    spr_register(env, SPR_DBAT0U, "DBAT0U",
 276                 SPR_NOACCESS, SPR_NOACCESS,
 277                 &spr_read_dbat, &spr_write_dbatu,
 278                 0x00000000);
 279    spr_register(env, SPR_DBAT0L, "DBAT0L",
 280                 SPR_NOACCESS, SPR_NOACCESS,
 281                 &spr_read_dbat, &spr_write_dbatl,
 282                 0x00000000);
 283    spr_register(env, SPR_DBAT1U, "DBAT1U",
 284                 SPR_NOACCESS, SPR_NOACCESS,
 285                 &spr_read_dbat, &spr_write_dbatu,
 286                 0x00000000);
 287    spr_register(env, SPR_DBAT1L, "DBAT1L",
 288                 SPR_NOACCESS, SPR_NOACCESS,
 289                 &spr_read_dbat, &spr_write_dbatl,
 290                 0x00000000);
 291    spr_register(env, SPR_DBAT2U, "DBAT2U",
 292                 SPR_NOACCESS, SPR_NOACCESS,
 293                 &spr_read_dbat, &spr_write_dbatu,
 294                 0x00000000);
 295    spr_register(env, SPR_DBAT2L, "DBAT2L",
 296                 SPR_NOACCESS, SPR_NOACCESS,
 297                 &spr_read_dbat, &spr_write_dbatl,
 298                 0x00000000);
 299    spr_register(env, SPR_DBAT3U, "DBAT3U",
 300                 SPR_NOACCESS, SPR_NOACCESS,
 301                 &spr_read_dbat, &spr_write_dbatu,
 302                 0x00000000);
 303    spr_register(env, SPR_DBAT3L, "DBAT3L",
 304                 SPR_NOACCESS, SPR_NOACCESS,
 305                 &spr_read_dbat, &spr_write_dbatl,
 306                 0x00000000);
 307    env->nb_BATs += 4;
 308#endif
 309}
 310
 311/* BATs 4-7 */
 312static void register_high_BATs(CPUPPCState *env)
 313{
 314#if !defined(CONFIG_USER_ONLY)
 315    spr_register(env, SPR_IBAT4U, "IBAT4U",
 316                 SPR_NOACCESS, SPR_NOACCESS,
 317                 &spr_read_ibat_h, &spr_write_ibatu_h,
 318                 0x00000000);
 319    spr_register(env, SPR_IBAT4L, "IBAT4L",
 320                 SPR_NOACCESS, SPR_NOACCESS,
 321                 &spr_read_ibat_h, &spr_write_ibatl_h,
 322                 0x00000000);
 323    spr_register(env, SPR_IBAT5U, "IBAT5U",
 324                 SPR_NOACCESS, SPR_NOACCESS,
 325                 &spr_read_ibat_h, &spr_write_ibatu_h,
 326                 0x00000000);
 327    spr_register(env, SPR_IBAT5L, "IBAT5L",
 328                 SPR_NOACCESS, SPR_NOACCESS,
 329                 &spr_read_ibat_h, &spr_write_ibatl_h,
 330                 0x00000000);
 331    spr_register(env, SPR_IBAT6U, "IBAT6U",
 332                 SPR_NOACCESS, SPR_NOACCESS,
 333                 &spr_read_ibat_h, &spr_write_ibatu_h,
 334                 0x00000000);
 335    spr_register(env, SPR_IBAT6L, "IBAT6L",
 336                 SPR_NOACCESS, SPR_NOACCESS,
 337                 &spr_read_ibat_h, &spr_write_ibatl_h,
 338                 0x00000000);
 339    spr_register(env, SPR_IBAT7U, "IBAT7U",
 340                 SPR_NOACCESS, SPR_NOACCESS,
 341                 &spr_read_ibat_h, &spr_write_ibatu_h,
 342                 0x00000000);
 343    spr_register(env, SPR_IBAT7L, "IBAT7L",
 344                 SPR_NOACCESS, SPR_NOACCESS,
 345                 &spr_read_ibat_h, &spr_write_ibatl_h,
 346                 0x00000000);
 347    spr_register(env, SPR_DBAT4U, "DBAT4U",
 348                 SPR_NOACCESS, SPR_NOACCESS,
 349                 &spr_read_dbat_h, &spr_write_dbatu_h,
 350                 0x00000000);
 351    spr_register(env, SPR_DBAT4L, "DBAT4L",
 352                 SPR_NOACCESS, SPR_NOACCESS,
 353                 &spr_read_dbat_h, &spr_write_dbatl_h,
 354                 0x00000000);
 355    spr_register(env, SPR_DBAT5U, "DBAT5U",
 356                 SPR_NOACCESS, SPR_NOACCESS,
 357                 &spr_read_dbat_h, &spr_write_dbatu_h,
 358                 0x00000000);
 359    spr_register(env, SPR_DBAT5L, "DBAT5L",
 360                 SPR_NOACCESS, SPR_NOACCESS,
 361                 &spr_read_dbat_h, &spr_write_dbatl_h,
 362                 0x00000000);
 363    spr_register(env, SPR_DBAT6U, "DBAT6U",
 364                 SPR_NOACCESS, SPR_NOACCESS,
 365                 &spr_read_dbat_h, &spr_write_dbatu_h,
 366                 0x00000000);
 367    spr_register(env, SPR_DBAT6L, "DBAT6L",
 368                 SPR_NOACCESS, SPR_NOACCESS,
 369                 &spr_read_dbat_h, &spr_write_dbatl_h,
 370                 0x00000000);
 371    spr_register(env, SPR_DBAT7U, "DBAT7U",
 372                 SPR_NOACCESS, SPR_NOACCESS,
 373                 &spr_read_dbat_h, &spr_write_dbatu_h,
 374                 0x00000000);
 375    spr_register(env, SPR_DBAT7L, "DBAT7L",
 376                 SPR_NOACCESS, SPR_NOACCESS,
 377                 &spr_read_dbat_h, &spr_write_dbatl_h,
 378                 0x00000000);
 379    env->nb_BATs += 4;
 380#endif
 381}
 382
 383/* Generic PowerPC time base */
 384static void register_tbl(CPUPPCState *env)
 385{
 386    spr_register(env, SPR_VTBL,  "TBL",
 387                 &spr_read_tbl, SPR_NOACCESS,
 388                 &spr_read_tbl, SPR_NOACCESS,
 389                 0x00000000);
 390    spr_register(env, SPR_TBL,   "TBL",
 391                 &spr_read_tbl, SPR_NOACCESS,
 392                 &spr_read_tbl, &spr_write_tbl,
 393                 0x00000000);
 394    spr_register(env, SPR_VTBU,  "TBU",
 395                 &spr_read_tbu, SPR_NOACCESS,
 396                 &spr_read_tbu, SPR_NOACCESS,
 397                 0x00000000);
 398    spr_register(env, SPR_TBU,   "TBU",
 399                 &spr_read_tbu, SPR_NOACCESS,
 400                 &spr_read_tbu, &spr_write_tbu,
 401                 0x00000000);
 402}
 403
 404/* Softare table search registers */
 405static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
 406{
 407#if !defined(CONFIG_USER_ONLY)
 408    env->nb_tlb = nb_tlbs;
 409    env->nb_ways = nb_ways;
 410    env->id_tlbs = 1;
 411    env->tlb_type = TLB_6XX;
 412    spr_register(env, SPR_DMISS, "DMISS",
 413                 SPR_NOACCESS, SPR_NOACCESS,
 414                 &spr_read_generic, SPR_NOACCESS,
 415                 0x00000000);
 416    spr_register(env, SPR_DCMP, "DCMP",
 417                 SPR_NOACCESS, SPR_NOACCESS,
 418                 &spr_read_generic, SPR_NOACCESS,
 419                 0x00000000);
 420    spr_register(env, SPR_HASH1, "HASH1",
 421                 SPR_NOACCESS, SPR_NOACCESS,
 422                 &spr_read_generic, SPR_NOACCESS,
 423                 0x00000000);
 424    spr_register(env, SPR_HASH2, "HASH2",
 425                 SPR_NOACCESS, SPR_NOACCESS,
 426                 &spr_read_generic, SPR_NOACCESS,
 427                 0x00000000);
 428    spr_register(env, SPR_IMISS, "IMISS",
 429                 SPR_NOACCESS, SPR_NOACCESS,
 430                 &spr_read_generic, SPR_NOACCESS,
 431                 0x00000000);
 432    spr_register(env, SPR_ICMP, "ICMP",
 433                 SPR_NOACCESS, SPR_NOACCESS,
 434                 &spr_read_generic, SPR_NOACCESS,
 435                 0x00000000);
 436    spr_register(env, SPR_RPA, "RPA",
 437                 SPR_NOACCESS, SPR_NOACCESS,
 438                 &spr_read_generic, &spr_write_generic,
 439                 0x00000000);
 440#endif
 441}
 442
 443/* SPR common to MPC755 and G2 */
 444static void register_G2_755_sprs(CPUPPCState *env)
 445{
 446    /* SGPRs */
 447    spr_register(env, SPR_SPRG4, "SPRG4",
 448                 SPR_NOACCESS, SPR_NOACCESS,
 449                 &spr_read_generic, &spr_write_generic,
 450                 0x00000000);
 451    spr_register(env, SPR_SPRG5, "SPRG5",
 452                 SPR_NOACCESS, SPR_NOACCESS,
 453                 &spr_read_generic, &spr_write_generic,
 454                 0x00000000);
 455    spr_register(env, SPR_SPRG6, "SPRG6",
 456                 SPR_NOACCESS, SPR_NOACCESS,
 457                 &spr_read_generic, &spr_write_generic,
 458                 0x00000000);
 459    spr_register(env, SPR_SPRG7, "SPRG7",
 460                 SPR_NOACCESS, SPR_NOACCESS,
 461                 &spr_read_generic, &spr_write_generic,
 462                 0x00000000);
 463}
 464
 465/* SPR common to all 7xx PowerPC implementations */
 466static void register_7xx_sprs(CPUPPCState *env)
 467{
 468    /* Breakpoints */
 469    /* XXX : not implemented */
 470    spr_register_kvm(env, SPR_DABR, "DABR",
 471                     SPR_NOACCESS, SPR_NOACCESS,
 472                     &spr_read_generic, &spr_write_generic,
 473                     KVM_REG_PPC_DABR, 0x00000000);
 474    /* XXX : not implemented */
 475    spr_register(env, SPR_IABR, "IABR",
 476                 SPR_NOACCESS, SPR_NOACCESS,
 477                 &spr_read_generic, &spr_write_generic,
 478                 0x00000000);
 479    /* Cache management */
 480    /* XXX : not implemented */
 481    spr_register(env, SPR_ICTC, "ICTC",
 482                 SPR_NOACCESS, SPR_NOACCESS,
 483                 &spr_read_generic, &spr_write_generic,
 484                 0x00000000);
 485    /* Performance monitors */
 486    /* XXX : not implemented */
 487    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
 488                 SPR_NOACCESS, SPR_NOACCESS,
 489                 &spr_read_generic, &spr_write_generic,
 490                 0x00000000);
 491    /* XXX : not implemented */
 492    spr_register(env, SPR_7XX_MMCR1, "MMCR1",
 493                 SPR_NOACCESS, SPR_NOACCESS,
 494                 &spr_read_generic, &spr_write_generic,
 495                 0x00000000);
 496    /* XXX : not implemented */
 497    spr_register(env, SPR_7XX_PMC1, "PMC1",
 498                 SPR_NOACCESS, SPR_NOACCESS,
 499                 &spr_read_generic, &spr_write_generic,
 500                 0x00000000);
 501    /* XXX : not implemented */
 502    spr_register(env, SPR_7XX_PMC2, "PMC2",
 503                 SPR_NOACCESS, SPR_NOACCESS,
 504                 &spr_read_generic, &spr_write_generic,
 505                 0x00000000);
 506    /* XXX : not implemented */
 507    spr_register(env, SPR_7XX_PMC3, "PMC3",
 508                 SPR_NOACCESS, SPR_NOACCESS,
 509                 &spr_read_generic, &spr_write_generic,
 510                 0x00000000);
 511    /* XXX : not implemented */
 512    spr_register(env, SPR_7XX_PMC4, "PMC4",
 513                 SPR_NOACCESS, SPR_NOACCESS,
 514                 &spr_read_generic, &spr_write_generic,
 515                 0x00000000);
 516    /* XXX : not implemented */
 517    spr_register(env, SPR_7XX_SIAR, "SIAR",
 518                 SPR_NOACCESS, SPR_NOACCESS,
 519                 &spr_read_generic, SPR_NOACCESS,
 520                 0x00000000);
 521    /* XXX : not implemented */
 522    spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
 523                 &spr_read_ureg, SPR_NOACCESS,
 524                 &spr_read_ureg, SPR_NOACCESS,
 525                 0x00000000);
 526    /* XXX : not implemented */
 527    spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
 528                 &spr_read_ureg, SPR_NOACCESS,
 529                 &spr_read_ureg, SPR_NOACCESS,
 530                 0x00000000);
 531    /* XXX : not implemented */
 532    spr_register(env, SPR_7XX_UPMC1, "UPMC1",
 533                 &spr_read_ureg, SPR_NOACCESS,
 534                 &spr_read_ureg, SPR_NOACCESS,
 535                 0x00000000);
 536    /* XXX : not implemented */
 537    spr_register(env, SPR_7XX_UPMC2, "UPMC2",
 538                 &spr_read_ureg, SPR_NOACCESS,
 539                 &spr_read_ureg, SPR_NOACCESS,
 540                 0x00000000);
 541    /* XXX : not implemented */
 542    spr_register(env, SPR_7XX_UPMC3, "UPMC3",
 543                 &spr_read_ureg, SPR_NOACCESS,
 544                 &spr_read_ureg, SPR_NOACCESS,
 545                 0x00000000);
 546    /* XXX : not implemented */
 547    spr_register(env, SPR_7XX_UPMC4, "UPMC4",
 548                 &spr_read_ureg, SPR_NOACCESS,
 549                 &spr_read_ureg, SPR_NOACCESS,
 550                 0x00000000);
 551    /* XXX : not implemented */
 552    spr_register(env, SPR_7XX_USIAR, "USIAR",
 553                 &spr_read_ureg, SPR_NOACCESS,
 554                 &spr_read_ureg, SPR_NOACCESS,
 555                 0x00000000);
 556    /* External access control */
 557    /* XXX : not implemented */
 558    spr_register(env, SPR_EAR, "EAR",
 559                 SPR_NOACCESS, SPR_NOACCESS,
 560                 &spr_read_generic, &spr_write_generic,
 561                 0x00000000);
 562}
 563
 564#ifdef TARGET_PPC64
 565static void register_amr_sprs(CPUPPCState *env)
 566{
 567#ifndef CONFIG_USER_ONLY
 568    /*
 569     * Virtual Page Class Key protection
 570     *
 571     * The AMR is accessible either via SPR 13 or SPR 29.  13 is
 572     * userspace accessible, 29 is privileged.  So we only need to set
 573     * the kvm ONE_REG id on one of them, we use 29
 574     */
 575    spr_register(env, SPR_UAMR, "UAMR",
 576                 &spr_read_generic, &spr_write_amr,
 577                 &spr_read_generic, &spr_write_amr,
 578                 0);
 579    spr_register_kvm_hv(env, SPR_AMR, "AMR",
 580                     SPR_NOACCESS, SPR_NOACCESS,
 581                     &spr_read_generic, &spr_write_amr,
 582                     &spr_read_generic, &spr_write_generic,
 583                     KVM_REG_PPC_AMR, 0);
 584    spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
 585                     SPR_NOACCESS, SPR_NOACCESS,
 586                     &spr_read_generic, &spr_write_uamor,
 587                     &spr_read_generic, &spr_write_generic,
 588                     KVM_REG_PPC_UAMOR, 0);
 589    spr_register_hv(env, SPR_AMOR, "AMOR",
 590                    SPR_NOACCESS, SPR_NOACCESS,
 591                    SPR_NOACCESS, SPR_NOACCESS,
 592                    &spr_read_generic, &spr_write_generic,
 593                    0);
 594#endif /* !CONFIG_USER_ONLY */
 595}
 596
 597static void register_iamr_sprs(CPUPPCState *env)
 598{
 599#ifndef CONFIG_USER_ONLY
 600    spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
 601                        SPR_NOACCESS, SPR_NOACCESS,
 602                        &spr_read_generic, &spr_write_iamr,
 603                        &spr_read_generic, &spr_write_generic,
 604                        KVM_REG_PPC_IAMR, 0);
 605#endif /* !CONFIG_USER_ONLY */
 606}
 607#endif /* TARGET_PPC64 */
 608
 609static void register_thrm_sprs(CPUPPCState *env)
 610{
 611    /* Thermal management */
 612    /* XXX : not implemented */
 613    spr_register(env, SPR_THRM1, "THRM1",
 614                 SPR_NOACCESS, SPR_NOACCESS,
 615                 &spr_read_thrm, &spr_write_generic,
 616                 0x00000000);
 617    /* XXX : not implemented */
 618    spr_register(env, SPR_THRM2, "THRM2",
 619                 SPR_NOACCESS, SPR_NOACCESS,
 620                 &spr_read_thrm, &spr_write_generic,
 621                 0x00000000);
 622    /* XXX : not implemented */
 623    spr_register(env, SPR_THRM3, "THRM3",
 624                 SPR_NOACCESS, SPR_NOACCESS,
 625                 &spr_read_thrm, &spr_write_generic,
 626                 0x00000000);
 627}
 628
 629/* SPR specific to PowerPC 604 implementation */
 630static void register_604_sprs(CPUPPCState *env)
 631{
 632    /* Processor identification */
 633    spr_register(env, SPR_PIR, "PIR",
 634                 SPR_NOACCESS, SPR_NOACCESS,
 635                 &spr_read_generic, &spr_write_pir,
 636                 0x00000000);
 637    /* Breakpoints */
 638    /* XXX : not implemented */
 639    spr_register(env, SPR_IABR, "IABR",
 640                 SPR_NOACCESS, SPR_NOACCESS,
 641                 &spr_read_generic, &spr_write_generic,
 642                 0x00000000);
 643    /* XXX : not implemented */
 644    spr_register_kvm(env, SPR_DABR, "DABR",
 645                     SPR_NOACCESS, SPR_NOACCESS,
 646                     &spr_read_generic, &spr_write_generic,
 647                     KVM_REG_PPC_DABR, 0x00000000);
 648    /* Performance counters */
 649    /* XXX : not implemented */
 650    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
 651                 SPR_NOACCESS, SPR_NOACCESS,
 652                 &spr_read_generic, &spr_write_generic,
 653                 0x00000000);
 654    /* XXX : not implemented */
 655    spr_register(env, SPR_7XX_PMC1, "PMC1",
 656                 SPR_NOACCESS, SPR_NOACCESS,
 657                 &spr_read_generic, &spr_write_generic,
 658                 0x00000000);
 659    /* XXX : not implemented */
 660    spr_register(env, SPR_7XX_PMC2, "PMC2",
 661                 SPR_NOACCESS, SPR_NOACCESS,
 662                 &spr_read_generic, &spr_write_generic,
 663                 0x00000000);
 664    /* XXX : not implemented */
 665    spr_register(env, SPR_7XX_SIAR, "SIAR",
 666                 SPR_NOACCESS, SPR_NOACCESS,
 667                 &spr_read_generic, SPR_NOACCESS,
 668                 0x00000000);
 669    /* XXX : not implemented */
 670    spr_register(env, SPR_SDA, "SDA",
 671                 SPR_NOACCESS, SPR_NOACCESS,
 672                 &spr_read_generic, SPR_NOACCESS,
 673                 0x00000000);
 674    /* External access control */
 675    /* XXX : not implemented */
 676    spr_register(env, SPR_EAR, "EAR",
 677                 SPR_NOACCESS, SPR_NOACCESS,
 678                 &spr_read_generic, &spr_write_generic,
 679                 0x00000000);
 680}
 681
 682/* SPR specific to PowerPC 603 implementation */
 683static void register_603_sprs(CPUPPCState *env)
 684{
 685    /* External access control */
 686    /* XXX : not implemented */
 687    spr_register(env, SPR_EAR, "EAR",
 688                 SPR_NOACCESS, SPR_NOACCESS,
 689                 &spr_read_generic, &spr_write_generic,
 690                 0x00000000);
 691    /* Breakpoints */
 692    /* XXX : not implemented */
 693    spr_register(env, SPR_IABR, "IABR",
 694                 SPR_NOACCESS, SPR_NOACCESS,
 695                 &spr_read_generic, &spr_write_generic,
 696                 0x00000000);
 697
 698}
 699
 700/* SPR specific to PowerPC G2 implementation */
 701static void register_G2_sprs(CPUPPCState *env)
 702{
 703    /* Memory base address */
 704    /* MBAR */
 705    /* XXX : not implemented */
 706    spr_register(env, SPR_MBAR, "MBAR",
 707                 SPR_NOACCESS, SPR_NOACCESS,
 708                 &spr_read_generic, &spr_write_generic,
 709                 0x00000000);
 710    /* Exception processing */
 711    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
 712                 SPR_NOACCESS, SPR_NOACCESS,
 713                 &spr_read_generic, &spr_write_generic,
 714                 0x00000000);
 715    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
 716                 SPR_NOACCESS, SPR_NOACCESS,
 717                 &spr_read_generic, &spr_write_generic,
 718                 0x00000000);
 719    /* Breakpoints */
 720    /* XXX : not implemented */
 721    spr_register(env, SPR_DABR, "DABR",
 722                 SPR_NOACCESS, SPR_NOACCESS,
 723                 &spr_read_generic, &spr_write_generic,
 724                 0x00000000);
 725    /* XXX : not implemented */
 726    spr_register(env, SPR_DABR2, "DABR2",
 727                 SPR_NOACCESS, SPR_NOACCESS,
 728                 &spr_read_generic, &spr_write_generic,
 729                 0x00000000);
 730    /* XXX : not implemented */
 731    spr_register(env, SPR_IABR, "IABR",
 732                 SPR_NOACCESS, SPR_NOACCESS,
 733                 &spr_read_generic, &spr_write_generic,
 734                 0x00000000);
 735    /* XXX : not implemented */
 736    spr_register(env, SPR_IABR2, "IABR2",
 737                 SPR_NOACCESS, SPR_NOACCESS,
 738                 &spr_read_generic, &spr_write_generic,
 739                 0x00000000);
 740    /* XXX : not implemented */
 741    spr_register(env, SPR_IBCR, "IBCR",
 742                 SPR_NOACCESS, SPR_NOACCESS,
 743                 &spr_read_generic, &spr_write_generic,
 744                 0x00000000);
 745    /* XXX : not implemented */
 746    spr_register(env, SPR_DBCR, "DBCR",
 747                 SPR_NOACCESS, SPR_NOACCESS,
 748                 &spr_read_generic, &spr_write_generic,
 749                 0x00000000);
 750}
 751
 752/* SPR specific to PowerPC 602 implementation */
 753static void register_602_sprs(CPUPPCState *env)
 754{
 755    /* ESA registers */
 756    /* XXX : not implemented */
 757    spr_register(env, SPR_SER, "SER",
 758                 SPR_NOACCESS, SPR_NOACCESS,
 759                 &spr_read_generic, &spr_write_generic,
 760                 0x00000000);
 761    /* XXX : not implemented */
 762    spr_register(env, SPR_SEBR, "SEBR",
 763                 SPR_NOACCESS, SPR_NOACCESS,
 764                 &spr_read_generic, &spr_write_generic,
 765                 0x00000000);
 766    /* XXX : not implemented */
 767    spr_register(env, SPR_ESASRR, "ESASRR",
 768                 SPR_NOACCESS, SPR_NOACCESS,
 769                 &spr_read_generic, &spr_write_generic,
 770                 0x00000000);
 771    /* Floating point status */
 772    /* XXX : not implemented */
 773    spr_register(env, SPR_SP, "SP",
 774                 SPR_NOACCESS, SPR_NOACCESS,
 775                 &spr_read_generic, &spr_write_generic,
 776                 0x00000000);
 777    /* XXX : not implemented */
 778    spr_register(env, SPR_LT, "LT",
 779                 SPR_NOACCESS, SPR_NOACCESS,
 780                 &spr_read_generic, &spr_write_generic,
 781                 0x00000000);
 782    /* Watchdog timer */
 783    /* XXX : not implemented */
 784    spr_register(env, SPR_TCR, "TCR",
 785                 SPR_NOACCESS, SPR_NOACCESS,
 786                 &spr_read_generic, &spr_write_generic,
 787                 0x00000000);
 788    /* Interrupt base */
 789    spr_register(env, SPR_IBR, "IBR",
 790                 SPR_NOACCESS, SPR_NOACCESS,
 791                 &spr_read_generic, &spr_write_generic,
 792                 0x00000000);
 793    /* XXX : not implemented */
 794    spr_register(env, SPR_IABR, "IABR",
 795                 SPR_NOACCESS, SPR_NOACCESS,
 796                 &spr_read_generic, &spr_write_generic,
 797                 0x00000000);
 798}
 799
 800/* SPR specific to PowerPC 601 implementation */
 801static void register_601_sprs(CPUPPCState *env)
 802{
 803    /* Multiplication/division register */
 804    /* MQ */
 805    spr_register(env, SPR_MQ, "MQ",
 806                 &spr_read_generic, &spr_write_generic,
 807                 &spr_read_generic, &spr_write_generic,
 808                 0x00000000);
 809    /* RTC registers */
 810    spr_register(env, SPR_601_RTCU, "RTCU",
 811                 SPR_NOACCESS, SPR_NOACCESS,
 812                 SPR_NOACCESS, &spr_write_601_rtcu,
 813                 0x00000000);
 814    spr_register(env, SPR_601_VRTCU, "RTCU",
 815                 &spr_read_601_rtcu, SPR_NOACCESS,
 816                 &spr_read_601_rtcu, SPR_NOACCESS,
 817                 0x00000000);
 818    spr_register(env, SPR_601_RTCL, "RTCL",
 819                 SPR_NOACCESS, SPR_NOACCESS,
 820                 SPR_NOACCESS, &spr_write_601_rtcl,
 821                 0x00000000);
 822    spr_register(env, SPR_601_VRTCL, "RTCL",
 823                 &spr_read_601_rtcl, SPR_NOACCESS,
 824                 &spr_read_601_rtcl, SPR_NOACCESS,
 825                 0x00000000);
 826    /* Timer */
 827#if 0 /* ? */
 828    spr_register(env, SPR_601_UDECR, "UDECR",
 829                 &spr_read_decr, SPR_NOACCESS,
 830                 &spr_read_decr, SPR_NOACCESS,
 831                 0x00000000);
 832#endif
 833    /* External access control */
 834    /* XXX : not implemented */
 835    spr_register(env, SPR_EAR, "EAR",
 836                 SPR_NOACCESS, SPR_NOACCESS,
 837                 &spr_read_generic, &spr_write_generic,
 838                 0x00000000);
 839    /* Memory management */
 840#if !defined(CONFIG_USER_ONLY)
 841    spr_register(env, SPR_IBAT0U, "IBAT0U",
 842                 SPR_NOACCESS, SPR_NOACCESS,
 843                 &spr_read_601_ubat, &spr_write_601_ubatu,
 844                 0x00000000);
 845    spr_register(env, SPR_IBAT0L, "IBAT0L",
 846                 SPR_NOACCESS, SPR_NOACCESS,
 847                 &spr_read_601_ubat, &spr_write_601_ubatl,
 848                 0x00000000);
 849    spr_register(env, SPR_IBAT1U, "IBAT1U",
 850                 SPR_NOACCESS, SPR_NOACCESS,
 851                 &spr_read_601_ubat, &spr_write_601_ubatu,
 852                 0x00000000);
 853    spr_register(env, SPR_IBAT1L, "IBAT1L",
 854                 SPR_NOACCESS, SPR_NOACCESS,
 855                 &spr_read_601_ubat, &spr_write_601_ubatl,
 856                 0x00000000);
 857    spr_register(env, SPR_IBAT2U, "IBAT2U",
 858                 SPR_NOACCESS, SPR_NOACCESS,
 859                 &spr_read_601_ubat, &spr_write_601_ubatu,
 860                 0x00000000);
 861    spr_register(env, SPR_IBAT2L, "IBAT2L",
 862                 SPR_NOACCESS, SPR_NOACCESS,
 863                 &spr_read_601_ubat, &spr_write_601_ubatl,
 864                 0x00000000);
 865    spr_register(env, SPR_IBAT3U, "IBAT3U",
 866                 SPR_NOACCESS, SPR_NOACCESS,
 867                 &spr_read_601_ubat, &spr_write_601_ubatu,
 868                 0x00000000);
 869    spr_register(env, SPR_IBAT3L, "IBAT3L",
 870                 SPR_NOACCESS, SPR_NOACCESS,
 871                 &spr_read_601_ubat, &spr_write_601_ubatl,
 872                 0x00000000);
 873    env->nb_BATs = 4;
 874#endif
 875}
 876
 877static void register_74xx_sprs(CPUPPCState *env)
 878{
 879    /* Processor identification */
 880    spr_register(env, SPR_PIR, "PIR",
 881                 SPR_NOACCESS, SPR_NOACCESS,
 882                 &spr_read_generic, &spr_write_pir,
 883                 0x00000000);
 884    /* XXX : not implemented */
 885    spr_register(env, SPR_74XX_MMCR2, "MMCR2",
 886                 SPR_NOACCESS, SPR_NOACCESS,
 887                 &spr_read_generic, &spr_write_generic,
 888                 0x00000000);
 889    /* XXX : not implemented */
 890    spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
 891                 &spr_read_ureg, SPR_NOACCESS,
 892                 &spr_read_ureg, SPR_NOACCESS,
 893                 0x00000000);
 894    /* XXX: not implemented */
 895    spr_register(env, SPR_BAMR, "BAMR",
 896                 SPR_NOACCESS, SPR_NOACCESS,
 897                 &spr_read_generic, &spr_write_generic,
 898                 0x00000000);
 899    /* XXX : not implemented */
 900    spr_register(env, SPR_MSSCR0, "MSSCR0",
 901                 SPR_NOACCESS, SPR_NOACCESS,
 902                 &spr_read_generic, &spr_write_generic,
 903                 0x00000000);
 904    /* Hardware implementation registers */
 905    /* XXX : not implemented */
 906    spr_register(env, SPR_HID0, "HID0",
 907                 SPR_NOACCESS, SPR_NOACCESS,
 908                 &spr_read_generic, &spr_write_generic,
 909                 0x00000000);
 910    /* XXX : not implemented */
 911    spr_register(env, SPR_HID1, "HID1",
 912                 SPR_NOACCESS, SPR_NOACCESS,
 913                 &spr_read_generic, &spr_write_generic,
 914                 0x00000000);
 915    /* Altivec */
 916    spr_register(env, SPR_VRSAVE, "VRSAVE",
 917                 &spr_read_generic, &spr_write_generic,
 918                 &spr_read_generic, &spr_write_generic,
 919                 0x00000000);
 920    /* XXX : not implemented */
 921    spr_register(env, SPR_L2CR, "L2CR",
 922                 SPR_NOACCESS, SPR_NOACCESS,
 923                 &spr_read_generic, spr_access_nop,
 924                 0x00000000);
 925}
 926
 927static void register_l3_ctrl(CPUPPCState *env)
 928{
 929    /* L3CR */
 930    /* XXX : not implemented */
 931    spr_register(env, SPR_L3CR, "L3CR",
 932                 SPR_NOACCESS, SPR_NOACCESS,
 933                 &spr_read_generic, &spr_write_generic,
 934                 0x00000000);
 935    /* L3ITCR0 */
 936    /* XXX : not implemented */
 937    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
 938                 SPR_NOACCESS, SPR_NOACCESS,
 939                 &spr_read_generic, &spr_write_generic,
 940                 0x00000000);
 941    /* L3PM */
 942    /* XXX : not implemented */
 943    spr_register(env, SPR_L3PM, "L3PM",
 944                 SPR_NOACCESS, SPR_NOACCESS,
 945                 &spr_read_generic, &spr_write_generic,
 946                 0x00000000);
 947}
 948
 949static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
 950{
 951#if !defined(CONFIG_USER_ONLY)
 952    env->nb_tlb = nb_tlbs;
 953    env->nb_ways = nb_ways;
 954    env->id_tlbs = 1;
 955    env->tlb_type = TLB_6XX;
 956    /* XXX : not implemented */
 957    spr_register(env, SPR_PTEHI, "PTEHI",
 958                 SPR_NOACCESS, SPR_NOACCESS,
 959                 &spr_read_generic, &spr_write_generic,
 960                 0x00000000);
 961    /* XXX : not implemented */
 962    spr_register(env, SPR_PTELO, "PTELO",
 963                 SPR_NOACCESS, SPR_NOACCESS,
 964                 &spr_read_generic, &spr_write_generic,
 965                 0x00000000);
 966    /* XXX : not implemented */
 967    spr_register(env, SPR_TLBMISS, "TLBMISS",
 968                 SPR_NOACCESS, SPR_NOACCESS,
 969                 &spr_read_generic, &spr_write_generic,
 970                 0x00000000);
 971#endif
 972}
 973
 974static void register_usprg3_sprs(CPUPPCState *env)
 975{
 976    spr_register(env, SPR_USPRG3, "USPRG3",
 977                 &spr_read_ureg, SPR_NOACCESS,
 978                 &spr_read_ureg, SPR_NOACCESS,
 979                 0x00000000);
 980}
 981
 982static void register_usprgh_sprs(CPUPPCState *env)
 983{
 984    spr_register(env, SPR_USPRG4, "USPRG4",
 985                 &spr_read_ureg, SPR_NOACCESS,
 986                 &spr_read_ureg, SPR_NOACCESS,
 987                 0x00000000);
 988    spr_register(env, SPR_USPRG5, "USPRG5",
 989                 &spr_read_ureg, SPR_NOACCESS,
 990                 &spr_read_ureg, SPR_NOACCESS,
 991                 0x00000000);
 992    spr_register(env, SPR_USPRG6, "USPRG6",
 993                 &spr_read_ureg, SPR_NOACCESS,
 994                 &spr_read_ureg, SPR_NOACCESS,
 995                 0x00000000);
 996    spr_register(env, SPR_USPRG7, "USPRG7",
 997                 &spr_read_ureg, SPR_NOACCESS,
 998                 &spr_read_ureg, SPR_NOACCESS,
 999                 0x00000000);
1000}

1001
1002/* PowerPC BookE SPR */
1003static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
1004{
1005    const char *ivor_names[64] = {
1006        "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1007        "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1008        "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1009        "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1010        "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1011        "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1012        "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1013        "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1014        "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1015        "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1016        "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1017        "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1018        "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1019        "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1020        "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1021        "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1022    };
1023#define SPR_BOOKE_IVORxx (-1)
1024    int ivor_sprn[64] = {
1025        SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1026        SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1027        SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1028        SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1029        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1030        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1031        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1032        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1033        SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1034        SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1035        SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1036        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1037        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1038        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1039        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1040        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1041    };
1042    int i;
1043
1044    /* Interrupt processing */
1045    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1046                 SPR_NOACCESS, SPR_NOACCESS,
1047                 &spr_read_generic, &spr_write_generic,
1048                 0x00000000);
1049    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1050                 SPR_NOACCESS, SPR_NOACCESS,
1051                 &spr_read_generic, &spr_write_generic,
1052                 0x00000000);
1053    /* Debug */
1054    /* XXX : not implemented */
1055    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1056                 SPR_NOACCESS, SPR_NOACCESS,
1057                 &spr_read_generic, &spr_write_generic,
1058                 0x00000000);
1059    /* XXX : not implemented */
1060    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1061                 SPR_NOACCESS, SPR_NOACCESS,
1062                 &spr_read_generic, &spr_write_generic,
1063                 0x00000000);
1064    /* XXX : not implemented */
1065    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1066                 SPR_NOACCESS, SPR_NOACCESS,
1067                 &spr_read_generic, &spr_write_generic,
1068                 0x00000000);
1069    /* XXX : not implemented */
1070    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1071                 SPR_NOACCESS, SPR_NOACCESS,
1072                 &spr_read_generic, &spr_write_generic,
1073                 0x00000000);
1074    /* XXX : not implemented */
1075    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1076                 SPR_NOACCESS, SPR_NOACCESS,
1077                 &spr_read_generic, &spr_write_40x_dbcr0,
1078                 0x00000000);
1079    /* XXX : not implemented */
1080    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1081                 SPR_NOACCESS, SPR_NOACCESS,
1082                 &spr_read_generic, &spr_write_generic,
1083                 0x00000000);
1084    /* XXX : not implemented */
1085    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1086                 SPR_NOACCESS, SPR_NOACCESS,
1087                 &spr_read_generic, &spr_write_generic,
1088                 0x00000000);
1089    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1090                 SPR_NOACCESS, SPR_NOACCESS,
1091                 &spr_read_generic, &spr_write_generic,
1092                 0x00000000);
1093    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1094                 SPR_NOACCESS, SPR_NOACCESS,
1095                 &spr_read_generic, &spr_write_generic,
1096                 0x00000000);
1097    /* XXX : not implemented */
1098    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1099                 SPR_NOACCESS, SPR_NOACCESS,
1100                 &spr_read_generic, &spr_write_clear,
1101                 0x00000000);
1102    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1103                 SPR_NOACCESS, SPR_NOACCESS,
1104                 &spr_read_generic, &spr_write_generic,
1105                 0x00000000);
1106    spr_register(env, SPR_BOOKE_ESR, "ESR",
1107                 SPR_NOACCESS, SPR_NOACCESS,
1108                 &spr_read_generic, &spr_write_generic,
1109                 0x00000000);
1110    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1111                 SPR_NOACCESS, SPR_NOACCESS,
1112                 &spr_read_generic, &spr_write_excp_prefix,
1113                 0x00000000);
1114    /* Exception vectors */
1115    for (i = 0; i < 64; i++) {
1116        if (ivor_mask & (1ULL << i)) {
1117            if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1118                fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1119                exit(1);
1120            }
1121            spr_register(env, ivor_sprn[i], ivor_names[i],
1122                         SPR_NOACCESS, SPR_NOACCESS,
1123                         &spr_read_generic, &spr_write_excp_vector,
1124                         0x00000000);
1125        }
1126    }
1127    spr_register(env, SPR_BOOKE_PID, "PID",
1128                 SPR_NOACCESS, SPR_NOACCESS,
1129                 &spr_read_generic, &spr_write_booke_pid,
1130                 0x00000000);
1131    spr_register(env, SPR_BOOKE_TCR, "TCR",
1132                 SPR_NOACCESS, SPR_NOACCESS,
1133                 &spr_read_generic, &spr_write_booke_tcr,
1134                 0x00000000);
1135    spr_register(env, SPR_BOOKE_TSR, "TSR",
1136                 SPR_NOACCESS, SPR_NOACCESS,
1137                 &spr_read_generic, &spr_write_booke_tsr,
1138                 0x00000000);
1139    /* Timer */
1140    spr_register(env, SPR_DECR, "DECR",
1141                 SPR_NOACCESS, SPR_NOACCESS,
1142                 &spr_read_decr, &spr_write_decr,
1143                 0x00000000);
1144    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1145                 SPR_NOACCESS, SPR_NOACCESS,
1146                 SPR_NOACCESS, &spr_write_generic,
1147                 0x00000000);
1148    /* SPRGs */
1149    spr_register(env, SPR_USPRG0, "USPRG0",
1150                 &spr_read_generic, &spr_write_generic,
1151                 &spr_read_generic, &spr_write_generic,
1152                 0x00000000);
1153    spr_register(env, SPR_SPRG4, "SPRG4",
1154                 SPR_NOACCESS, SPR_NOACCESS,
1155                 &spr_read_generic, &spr_write_generic,
1156                 0x00000000);
1157    spr_register(env, SPR_SPRG5, "SPRG5",
1158                 SPR_NOACCESS, SPR_NOACCESS,
1159                 &spr_read_generic, &spr_write_generic,
1160                 0x00000000);
1161    spr_register(env, SPR_SPRG6, "SPRG6",
1162                 SPR_NOACCESS, SPR_NOACCESS,
1163                 &spr_read_generic, &spr_write_generic,
1164                 0x00000000);
1165    spr_register(env, SPR_SPRG7, "SPRG7",
1166                 SPR_NOACCESS, SPR_NOACCESS,
1167                 &spr_read_generic, &spr_write_generic,
1168                 0x00000000);
1169    spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1170                 SPR_NOACCESS, SPR_NOACCESS,
1171                 &spr_read_generic, &spr_write_generic,
1172                 0x00000000);
1173    spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1174                 SPR_NOACCESS, SPR_NOACCESS,
1175                 &spr_read_generic, &spr_write_generic,
1176                 0x00000000);
1177}
1178
1179#if !defined(CONFIG_USER_ONLY)
1180static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1181                                   uint32_t maxsize, uint32_t flags,
1182                                   uint32_t nentries)
1183{
1184    return (assoc << TLBnCFG_ASSOC_SHIFT) |
1185           (minsize << TLBnCFG_MINSIZE_SHIFT) |
1186           (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1187           flags | nentries;
1188}
1189#endif /* !CONFIG_USER_ONLY */
1190
1191/* BookE 2.06 storage control registers */
1192static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1193                             uint32_t *tlbncfg, uint32_t mmucfg)
1194{
1195#if !defined(CONFIG_USER_ONLY)
1196    const char *mas_names[8] = {
1197        "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1198    };
1199    int mas_sprn[8] = {
1200        SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1201        SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1202    };
1203    int i;
1204
1205    /* TLB assist registers */
1206    /* XXX : not implemented */
1207    for (i = 0; i < 8; i++) {
1208        if (mas_mask & (1 << i)) {
1209            spr_register(env, mas_sprn[i], mas_names[i],
1210                         SPR_NOACCESS, SPR_NOACCESS,
1211                         &spr_read_generic,
1212                         (i == 2 && (env->insns_flags & PPC_64B))
1213                         ? &spr_write_generic : &spr_write_generic32,
1214                         0x00000000);
1215        }
1216    }
1217    if (env->nb_pids > 1) {
1218        /* XXX : not implemented */
1219        spr_register(env, SPR_BOOKE_PID1, "PID1",
1220                     SPR_NOACCESS, SPR_NOACCESS,
1221                     &spr_read_generic, &spr_write_booke_pid,
1222                     0x00000000);
1223    }
1224    if (env->nb_pids > 2) {
1225        /* XXX : not implemented */
1226        spr_register(env, SPR_BOOKE_PID2, "PID2",
1227                     SPR_NOACCESS, SPR_NOACCESS,
1228                     &spr_read_generic, &spr_write_booke_pid,
1229                     0x00000000);
1230    }
1231
1232    spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1233                 SPR_NOACCESS, SPR_NOACCESS,
1234                 &spr_read_generic, &spr_write_eplc,
1235                 0x00000000);
1236    spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1237                 SPR_NOACCESS, SPR_NOACCESS,
1238                 &spr_read_generic, &spr_write_epsc,
1239                 0x00000000);
1240
1241    /* XXX : not implemented */
1242    spr_register(env, SPR_MMUCFG, "MMUCFG",
1243                 SPR_NOACCESS, SPR_NOACCESS,
1244                 &spr_read_generic, SPR_NOACCESS,
1245                 mmucfg);
1246    switch (env->nb_ways) {
1247    case 4:
1248        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1249                     SPR_NOACCESS, SPR_NOACCESS,
1250                     &spr_read_generic, SPR_NOACCESS,
1251                     tlbncfg[3]);
1252        /* Fallthru */
1253    case 3:
1254        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1255                     SPR_NOACCESS, SPR_NOACCESS,
1256                     &spr_read_generic, SPR_NOACCESS,
1257                     tlbncfg[2]);
1258        /* Fallthru */
1259    case 2:
1260        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1261                     SPR_NOACCESS, SPR_NOACCESS,
1262                     &spr_read_generic, SPR_NOACCESS,
1263                     tlbncfg[1]);
1264        /* Fallthru */
1265    case 1:
1266        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1267                     SPR_NOACCESS, SPR_NOACCESS,
1268                     &spr_read_generic, SPR_NOACCESS,
1269                     tlbncfg[0]);
1270        /* Fallthru */
1271    case 0:
1272    default:
1273        break;
1274    }
1275#endif
1276
1277    register_usprgh_sprs(env);
1278}
1279
1280/* SPR specific to PowerPC 440 implementation */
1281static void register_440_sprs(CPUPPCState *env)
1282{
1283    /* Cache control */
1284    /* XXX : not implemented */
1285    spr_register(env, SPR_440_DNV0, "DNV0",
1286                 SPR_NOACCESS, SPR_NOACCESS,
1287                 &spr_read_generic, &spr_write_generic,
1288                 0x00000000);
1289    /* XXX : not implemented */
1290    spr_register(env, SPR_440_DNV1, "DNV1",
1291                 SPR_NOACCESS, SPR_NOACCESS,
1292                 &spr_read_generic, &spr_write_generic,
1293                 0x00000000);
1294    /* XXX : not implemented */
1295    spr_register(env, SPR_440_DNV2, "DNV2",
1296                 SPR_NOACCESS, SPR_NOACCESS,
1297                 &spr_read_generic, &spr_write_generic,
1298                 0x00000000);
1299    /* XXX : not implemented */
1300    spr_register(env, SPR_440_DNV3, "DNV3",
1301                 SPR_NOACCESS, SPR_NOACCESS,
1302                 &spr_read_generic, &spr_write_generic,
1303                 0x00000000);
1304    /* XXX : not implemented */
1305    spr_register(env, SPR_440_DTV0, "DTV0",
1306                 SPR_NOACCESS, SPR_NOACCESS,
1307                 &spr_read_generic, &spr_write_generic,
1308                 0x00000000);
1309    /* XXX : not implemented */
1310    spr_register(env, SPR_440_DTV1, "DTV1",
1311                 SPR_NOACCESS, SPR_NOACCESS,
1312                 &spr_read_generic, &spr_write_generic,
1313                 0x00000000);
1314    /* XXX : not implemented */
1315    spr_register(env, SPR_440_DTV2, "DTV2",
1316                 SPR_NOACCESS, SPR_NOACCESS,
1317                 &spr_read_generic, &spr_write_generic,
1318                 0x00000000);
1319    /* XXX : not implemented */
1320    spr_register(env, SPR_440_DTV3, "DTV3",
1321                 SPR_NOACCESS, SPR_NOACCESS,
1322                 &spr_read_generic, &spr_write_generic,
1323                 0x00000000);
1324    /* XXX : not implemented */
1325    spr_register(env, SPR_440_DVLIM, "DVLIM",
1326                 SPR_NOACCESS, SPR_NOACCESS,
1327                 &spr_read_generic, &spr_write_generic,
1328                 0x00000000);
1329    /* XXX : not implemented */
1330    spr_register(env, SPR_440_INV0, "INV0",
1331                 SPR_NOACCESS, SPR_NOACCESS,
1332                 &spr_read_generic, &spr_write_generic,
1333                 0x00000000);
1334    /* XXX : not implemented */
1335    spr_register(env, SPR_440_INV1, "INV1",
1336                 SPR_NOACCESS, SPR_NOACCESS,
1337                 &spr_read_generic, &spr_write_generic,
1338                 0x00000000);
1339    /* XXX : not implemented */
1340    spr_register(env, SPR_440_INV2, "INV2",
1341                 SPR_NOACCESS, SPR_NOACCESS,
1342                 &spr_read_generic, &spr_write_generic,
1343                 0x00000000);
1344    /* XXX : not implemented */
1345    spr_register(env, SPR_440_INV3, "INV3",
1346                 SPR_NOACCESS, SPR_NOACCESS,
1347                 &spr_read_generic, &spr_write_generic,
1348                 0x00000000);
1349    /* XXX : not implemented */
1350    spr_register(env, SPR_440_ITV0, "ITV0",
1351                 SPR_NOACCESS, SPR_NOACCESS,
1352                 &spr_read_generic, &spr_write_generic,
1353                 0x00000000);
1354    /* XXX : not implemented */
1355    spr_register(env, SPR_440_ITV1, "ITV1",
1356                 SPR_NOACCESS, SPR_NOACCESS,
1357                 &spr_read_generic, &spr_write_generic,
1358                 0x00000000);
1359    /* XXX : not implemented */
1360    spr_register(env, SPR_440_ITV2, "ITV2",
1361                 SPR_NOACCESS, SPR_NOACCESS,
1362                 &spr_read_generic, &spr_write_generic,
1363                 0x00000000);
1364    /* XXX : not implemented */
1365    spr_register(env, SPR_440_ITV3, "ITV3",
1366                 SPR_NOACCESS, SPR_NOACCESS,
1367                 &spr_read_generic, &spr_write_generic,
1368                 0x00000000);
1369    /* XXX : not implemented */
1370    spr_register(env, SPR_440_IVLIM, "IVLIM",
1371                 SPR_NOACCESS, SPR_NOACCESS,
1372                 &spr_read_generic, &spr_write_generic,
1373                 0x00000000);
1374    /* Cache debug */
1375    /* XXX : not implemented */
1376    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1377                 SPR_NOACCESS, SPR_NOACCESS,
1378                 &spr_read_generic, SPR_NOACCESS,
1379                 0x00000000);
1380    /* XXX : not implemented */
1381    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1382                 SPR_NOACCESS, SPR_NOACCESS,
1383                 &spr_read_generic, SPR_NOACCESS,
1384                 0x00000000);
1385    /* XXX : not implemented */
1386    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1387                 SPR_NOACCESS, SPR_NOACCESS,
1388                 &spr_read_generic, SPR_NOACCESS,
1389                 0x00000000);
1390    /* XXX : not implemented */
1391    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1392                 SPR_NOACCESS, SPR_NOACCESS,
1393                 &spr_read_generic, SPR_NOACCESS,
1394                 0x00000000);
1395    /* XXX : not implemented */
1396    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1397                 SPR_NOACCESS, SPR_NOACCESS,
1398                 &spr_read_generic, SPR_NOACCESS,
1399                 0x00000000);
1400    /* XXX : not implemented */
1401    spr_register(env, SPR_440_DBDR, "DBDR",
1402                 SPR_NOACCESS, SPR_NOACCESS,
1403                 &spr_read_generic, &spr_write_generic,
1404                 0x00000000);
1405    /* Processor control */
1406    spr_register(env, SPR_4xx_CCR0, "CCR0",
1407                 SPR_NOACCESS, SPR_NOACCESS,
1408                 &spr_read_generic, &spr_write_generic,
1409                 0x00000000);
1410    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1411                 SPR_NOACCESS, SPR_NOACCESS,
1412                 &spr_read_generic, SPR_NOACCESS,
1413                 0x00000000);
1414    /* Storage control */
1415    spr_register(env, SPR_440_MMUCR, "MMUCR",
1416                 SPR_NOACCESS, SPR_NOACCESS,
1417                 &spr_read_generic, &spr_write_generic,
1418                 0x00000000);
1419}
1420
1421/* SPR shared between PowerPC 40x implementations */
1422static void register_40x_sprs(CPUPPCState *env)
1423{
1424    /* Cache */
1425    /* not emulated, as QEMU do not emulate caches */
1426    spr_register(env, SPR_40x_DCCR, "DCCR",
1427                 SPR_NOACCESS, SPR_NOACCESS,
1428                 &spr_read_generic, &spr_write_generic,
1429                 0x00000000);
1430    /* not emulated, as QEMU do not emulate caches */
1431    spr_register(env, SPR_40x_ICCR, "ICCR",
1432                 SPR_NOACCESS, SPR_NOACCESS,
1433                 &spr_read_generic, &spr_write_generic,
1434                 0x00000000);
1435    /* not emulated, as QEMU do not emulate caches */
1436    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1437                 SPR_NOACCESS, SPR_NOACCESS,
1438                 &spr_read_generic, SPR_NOACCESS,
1439                 0x00000000);
1440    /* Exception */
1441    spr_register(env, SPR_40x_DEAR, "DEAR",
1442                 SPR_NOACCESS, SPR_NOACCESS,
1443                 &spr_read_generic, &spr_write_generic,
1444                 0x00000000);
1445    spr_register(env, SPR_40x_ESR, "ESR",
1446                 SPR_NOACCESS, SPR_NOACCESS,
1447                 &spr_read_generic, &spr_write_generic,
1448                 0x00000000);
1449    spr_register(env, SPR_40x_EVPR, "EVPR",
1450                 SPR_NOACCESS, SPR_NOACCESS,
1451                 &spr_read_generic, &spr_write_excp_prefix,
1452                 0x00000000);
1453    spr_register(env, SPR_40x_SRR2, "SRR2",
1454                 &spr_read_generic, &spr_write_generic,
1455                 &spr_read_generic, &spr_write_generic,
1456                 0x00000000);
1457    spr_register(env, SPR_40x_SRR3, "SRR3",
1458                 &spr_read_generic, &spr_write_generic,
1459                 &spr_read_generic, &spr_write_generic,
1460                 0x00000000);
1461    /* Timers */
1462    spr_register(env, SPR_40x_PIT, "PIT",
1463                 SPR_NOACCESS, SPR_NOACCESS,
1464                 &spr_read_40x_pit, &spr_write_40x_pit,
1465                 0x00000000);
1466    spr_register(env, SPR_40x_TCR, "TCR",
1467                 SPR_NOACCESS, SPR_NOACCESS,
1468                 &spr_read_generic, &spr_write_booke_tcr,
1469                 0x00000000);
1470    spr_register(env, SPR_40x_TSR, "TSR",
1471                 SPR_NOACCESS, SPR_NOACCESS,
1472                 &spr_read_generic, &spr_write_booke_tsr,
1473                 0x00000000);
1474}
1475
1476/* SPR specific to PowerPC 405 implementation */
1477static void register_405_sprs(CPUPPCState *env)
1478{
1479    /* MMU */
1480    spr_register(env, SPR_40x_PID, "PID",
1481                 SPR_NOACCESS, SPR_NOACCESS,
1482                 &spr_read_generic, &spr_write_generic,
1483                 0x00000000);
1484    spr_register(env, SPR_4xx_CCR0, "CCR0",
1485                 SPR_NOACCESS, SPR_NOACCESS,
1486                 &spr_read_generic, &spr_write_generic,
1487                 0x00700000);
1488    /* Debug interface */
1489    /* XXX : not implemented */
1490    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1491                 SPR_NOACCESS, SPR_NOACCESS,
1492                 &spr_read_generic, &spr_write_40x_dbcr0,
1493                 0x00000000);
1494    /* XXX : not implemented */
1495    spr_register(env, SPR_405_DBCR1, "DBCR1",
1496                 SPR_NOACCESS, SPR_NOACCESS,
1497                 &spr_read_generic, &spr_write_generic,
1498                 0x00000000);
1499    /* XXX : not implemented */
1500    spr_register(env, SPR_40x_DBSR, "DBSR",
1501                 SPR_NOACCESS, SPR_NOACCESS,
1502                 &spr_read_generic, &spr_write_clear,
1503                 /* Last reset was system reset */
1504                 0x00000300);
1505    /* XXX : not implemented */
1506    spr_register(env, SPR_40x_DAC1, "DAC1",
1507                 SPR_NOACCESS, SPR_NOACCESS,
1508                 &spr_read_generic, &spr_write_generic,
1509                 0x00000000);
1510    spr_register(env, SPR_40x_DAC2, "DAC2",
1511                 SPR_NOACCESS, SPR_NOACCESS,
1512                 &spr_read_generic, &spr_write_generic,
1513                 0x00000000);
1514    /* XXX : not implemented */
1515    spr_register(env, SPR_405_DVC1, "DVC1",
1516                 SPR_NOACCESS, SPR_NOACCESS,
1517                 &spr_read_generic, &spr_write_generic,
1518                 0x00000000);
1519    /* XXX : not implemented */
1520    spr_register(env, SPR_405_DVC2, "DVC2",
1521                 SPR_NOACCESS, SPR_NOACCESS,
1522                 &spr_read_generic, &spr_write_generic,
1523                 0x00000000);
1524    /* XXX : not implemented */
1525    spr_register(env, SPR_40x_IAC1, "IAC1",
1526                 SPR_NOACCESS, SPR_NOACCESS,
1527                 &spr_read_generic, &spr_write_generic,
1528                 0x00000000);
1529    spr_register(env, SPR_40x_IAC2, "IAC2",
1530                 SPR_NOACCESS, SPR_NOACCESS,
1531                 &spr_read_generic, &spr_write_generic,
1532                 0x00000000);
1533    /* XXX : not implemented */
1534    spr_register(env, SPR_405_IAC3, "IAC3",
1535                 SPR_NOACCESS, SPR_NOACCESS,
1536                 &spr_read_generic, &spr_write_generic,
1537                 0x00000000);
1538    /* XXX : not implemented */
1539    spr_register(env, SPR_405_IAC4, "IAC4",
1540                 SPR_NOACCESS, SPR_NOACCESS,
1541                 &spr_read_generic, &spr_write_generic,
1542                 0x00000000);
1543    /* Storage control */
1544    /* XXX: TODO: not implemented */
1545    spr_register(env, SPR_405_SLER, "SLER",
1546                 SPR_NOACCESS, SPR_NOACCESS,
1547                 &spr_read_generic, &spr_write_40x_sler,
1548                 0x00000000);
1549    spr_register(env, SPR_40x_ZPR, "ZPR",
1550                 SPR_NOACCESS, SPR_NOACCESS,
1551                 &spr_read_generic, &spr_write_generic,
1552                 0x00000000);
1553    /* XXX : not implemented */
1554    spr_register(env, SPR_405_SU0R, "SU0R",
1555                 SPR_NOACCESS, SPR_NOACCESS,
1556                 &spr_read_generic, &spr_write_generic,
1557                 0x00000000);
1558    /* SPRG */
1559    spr_register(env, SPR_USPRG0, "USPRG0",
1560                 &spr_read_ureg, SPR_NOACCESS,
1561                 &spr_read_ureg, SPR_NOACCESS,
1562                 0x00000000);
1563    spr_register(env, SPR_SPRG4, "SPRG4",
1564                 SPR_NOACCESS, SPR_NOACCESS,
1565                 &spr_read_generic, &spr_write_generic,
1566                 0x00000000);
1567    spr_register(env, SPR_SPRG5, "SPRG5",
1568                 SPR_NOACCESS, SPR_NOACCESS,
1569                 spr_read_generic, &spr_write_generic,
1570                 0x00000000);
1571    spr_register(env, SPR_SPRG6, "SPRG6",
1572                 SPR_NOACCESS, SPR_NOACCESS,
1573                 spr_read_generic, &spr_write_generic,
1574                 0x00000000);
1575    spr_register(env, SPR_SPRG7, "SPRG7",
1576                 SPR_NOACCESS, SPR_NOACCESS,
1577                 spr_read_generic, &spr_write_generic,
1578                 0x00000000);
1579    register_usprgh_sprs(env);
1580}
1581
1582/* SPR shared between PowerPC 401 & 403 implementations */
1583static void register_401_403_sprs(CPUPPCState *env)
1584{
1585    /* Time base */
1586    spr_register(env, SPR_403_VTBL,  "TBL",
1587                 &spr_read_tbl, SPR_NOACCESS,
1588                 &spr_read_tbl, SPR_NOACCESS,
1589                 0x00000000);
1590    spr_register(env, SPR_403_TBL,   "TBL",
1591                 SPR_NOACCESS, SPR_NOACCESS,
1592                 SPR_NOACCESS, &spr_write_tbl,
1593                 0x00000000);
1594    spr_register(env, SPR_403_VTBU,  "TBU",
1595                 &spr_read_tbu, SPR_NOACCESS,
1596                 &spr_read_tbu, SPR_NOACCESS,
1597                 0x00000000);
1598    spr_register(env, SPR_403_TBU,   "TBU",
1599                 SPR_NOACCESS, SPR_NOACCESS,
1600                 SPR_NOACCESS, &spr_write_tbu,
1601                 0x00000000);
1602    /* Debug */
1603    /* not emulated, as QEMU do not emulate caches */
1604    spr_register(env, SPR_403_CDBCR, "CDBCR",
1605                 SPR_NOACCESS, SPR_NOACCESS,
1606                 &spr_read_generic, &spr_write_generic,
1607                 0x00000000);
1608}
1609
1610/* SPR specific to PowerPC 401 implementation */
1611static void register_401_sprs(CPUPPCState *env)
1612{
1613    /* Debug interface */
1614    /* XXX : not implemented */
1615    spr_register(env, SPR_40x_DBCR0, "DBCR",
1616                 SPR_NOACCESS, SPR_NOACCESS,
1617                 &spr_read_generic, &spr_write_40x_dbcr0,
1618                 0x00000000);
1619    /* XXX : not implemented */
1620    spr_register(env, SPR_40x_DBSR, "DBSR",
1621                 SPR_NOACCESS, SPR_NOACCESS,
1622                 &spr_read_generic, &spr_write_clear,
1623                 /* Last reset was system reset */
1624                 0x00000300);
1625    /* XXX : not implemented */
1626    spr_register(env, SPR_40x_DAC1, "DAC",
1627                 SPR_NOACCESS, SPR_NOACCESS,
1628                 &spr_read_generic, &spr_write_generic,
1629                 0x00000000);
1630    /* XXX : not implemented */
1631    spr_register(env, SPR_40x_IAC1, "IAC",
1632                 SPR_NOACCESS, SPR_NOACCESS,
1633                 &spr_read_generic, &spr_write_generic,
1634                 0x00000000);
1635    /* Storage control */
1636    /* XXX: TODO: not implemented */
1637    spr_register(env, SPR_405_SLER, "SLER",
1638                 SPR_NOACCESS, SPR_NOACCESS,
1639                 &spr_read_generic, &spr_write_40x_sler,
1640                 0x00000000);
1641    /* not emulated, as QEMU never does speculative access */
1642    spr_register(env, SPR_40x_SGR, "SGR",
1643                 SPR_NOACCESS, SPR_NOACCESS,
1644                 &spr_read_generic, &spr_write_generic,
1645                 0xFFFFFFFF);
1646    /* not emulated, as QEMU do not emulate caches */
1647    spr_register(env, SPR_40x_DCWR, "DCWR",
1648                 SPR_NOACCESS, SPR_NOACCESS,
1649                 &spr_read_generic, &spr_write_generic,
1650                 0x00000000);
1651}
1652
1653static void register_401x2_sprs(CPUPPCState *env)
1654{
1655    register_401_sprs(env);
1656    spr_register(env, SPR_40x_PID, "PID",
1657                 SPR_NOACCESS, SPR_NOACCESS,
1658                 &spr_read_generic, &spr_write_generic,
1659                 0x00000000);
1660    spr_register(env, SPR_40x_ZPR, "ZPR",
1661                 SPR_NOACCESS, SPR_NOACCESS,
1662                 &spr_read_generic, &spr_write_generic,
1663                 0x00000000);
1664}
1665
1666/* SPR specific to PowerPC 403 implementation */
1667static void register_403_sprs(CPUPPCState *env)
1668{
1669    /* Debug interface */
1670    /* XXX : not implemented */
1671    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1672                 SPR_NOACCESS, SPR_NOACCESS,
1673                 &spr_read_generic, &spr_write_40x_dbcr0,
1674                 0x00000000);
1675    /* XXX : not implemented */
1676    spr_register(env, SPR_40x_DBSR, "DBSR",
1677                 SPR_NOACCESS, SPR_NOACCESS,
1678                 &spr_read_generic, &spr_write_clear,
1679                 /* Last reset was system reset */
1680                 0x00000300);
1681    /* XXX : not implemented */
1682    spr_register(env, SPR_40x_DAC1, "DAC1",
1683                 SPR_NOACCESS, SPR_NOACCESS,
1684                 &spr_read_generic, &spr_write_generic,
1685                 0x00000000);
1686    /* XXX : not implemented */
1687    spr_register(env, SPR_40x_DAC2, "DAC2",
1688                 SPR_NOACCESS, SPR_NOACCESS,
1689                 &spr_read_generic, &spr_write_generic,
1690                 0x00000000);
1691    /* XXX : not implemented */
1692    spr_register(env, SPR_40x_IAC1, "IAC1",
1693                 SPR_NOACCESS, SPR_NOACCESS,
1694                 &spr_read_generic, &spr_write_generic,
1695                 0x00000000);
1696    /* XXX : not implemented */
1697    spr_register(env, SPR_40x_IAC2, "IAC2",
1698                 SPR_NOACCESS, SPR_NOACCESS,
1699                 &spr_read_generic, &spr_write_generic,
1700                 0x00000000);
1701}
1702
1703static void register_403_real_sprs(CPUPPCState *env)
1704{
1705    spr_register(env, SPR_403_PBL1,  "PBL1",
1706                 SPR_NOACCESS, SPR_NOACCESS,
1707                 &spr_read_403_pbr, &spr_write_403_pbr,
1708                 0x00000000);
1709    spr_register(env, SPR_403_PBU1,  "PBU1",
1710                 SPR_NOACCESS, SPR_NOACCESS,
1711                 &spr_read_403_pbr, &spr_write_403_pbr,
1712                 0x00000000);
1713    spr_register(env, SPR_403_PBL2,  "PBL2",
1714                 SPR_NOACCESS, SPR_NOACCESS,
1715                 &spr_read_403_pbr, &spr_write_403_pbr,
1716                 0x00000000);
1717    spr_register(env, SPR_403_PBU2,  "PBU2",
1718                 SPR_NOACCESS, SPR_NOACCESS,
1719                 &spr_read_403_pbr, &spr_write_403_pbr,
1720                 0x00000000);
1721}
1722
1723static void register_403_mmu_sprs(CPUPPCState *env)
1724{
1725    /* MMU */
1726    spr_register(env, SPR_40x_PID, "PID",
1727                 SPR_NOACCESS, SPR_NOACCESS,
1728                 &spr_read_generic, &spr_write_generic,
1729                 0x00000000);
1730    spr_register(env, SPR_40x_ZPR, "ZPR",
1731                 SPR_NOACCESS, SPR_NOACCESS,
1732                 &spr_read_generic, &spr_write_generic,
1733                 0x00000000);
1734}
1735
1736/* SPR specific to PowerPC compression coprocessor extension */
1737static void register_compress_sprs(CPUPPCState *env)
1738{
1739    /* XXX : not implemented */
1740    spr_register(env, SPR_401_SKR, "SKR",
1741                 SPR_NOACCESS, SPR_NOACCESS,
1742                 &spr_read_generic, &spr_write_generic,
1743                 0x00000000);
1744}
1745
1746static void register_5xx_8xx_sprs(CPUPPCState *env)
1747{
1748    /* Exception processing */
1749    spr_register_kvm(env, SPR_DSISR, "DSISR",
1750                     SPR_NOACCESS, SPR_NOACCESS,
1751                     &spr_read_generic, &spr_write_generic,
1752                     KVM_REG_PPC_DSISR, 0x00000000);
1753    spr_register_kvm(env, SPR_DAR, "DAR",
1754                     SPR_NOACCESS, SPR_NOACCESS,
1755                     &spr_read_generic, &spr_write_generic,
1756                     KVM_REG_PPC_DAR, 0x00000000);
1757    /* Timer */
1758    spr_register(env, SPR_DECR, "DECR",
1759                 SPR_NOACCESS, SPR_NOACCESS,
1760                 &spr_read_decr, &spr_write_decr,
1761                 0x00000000);
1762    /* XXX : not implemented */
1763    spr_register(env, SPR_MPC_EIE, "EIE",
1764                 SPR_NOACCESS, SPR_NOACCESS,
1765                 &spr_read_generic, &spr_write_generic,
1766                 0x00000000);
1767    /* XXX : not implemented */
1768    spr_register(env, SPR_MPC_EID, "EID",
1769                 SPR_NOACCESS, SPR_NOACCESS,
1770                 &spr_read_generic, &spr_write_generic,
1771                 0x00000000);
1772    /* XXX : not implemented */
1773    spr_register(env, SPR_MPC_NRI, "NRI",
1774                 SPR_NOACCESS, SPR_NOACCESS,
1775                 &spr_read_generic, &spr_write_generic,
1776                 0x00000000);
1777    /* XXX : not implemented */
1778    spr_register(env, SPR_MPC_CMPA, "CMPA",
1779                 SPR_NOACCESS, SPR_NOACCESS,
1780                 &spr_read_generic, &spr_write_generic,
1781                 0x00000000);
1782    /* XXX : not implemented */
1783    spr_register(env, SPR_MPC_CMPB, "CMPB",
1784                 SPR_NOACCESS, SPR_NOACCESS,
1785                 &spr_read_generic, &spr_write_generic,
1786                 0x00000000);
1787    /* XXX : not implemented */
1788    spr_register(env, SPR_MPC_CMPC, "CMPC",
1789                 SPR_NOACCESS, SPR_NOACCESS,
1790                 &spr_read_generic, &spr_write_generic,
1791                 0x00000000);
1792    /* XXX : not implemented */
1793    spr_register(env, SPR_MPC_CMPD, "CMPD",
1794                 SPR_NOACCESS, SPR_NOACCESS,
1795                 &spr_read_generic, &spr_write_generic,
1796                 0x00000000);
1797    /* XXX : not implemented */
1798    spr_register(env, SPR_MPC_ECR, "ECR",
1799                 SPR_NOACCESS, SPR_NOACCESS,
1800                 &spr_read_generic, &spr_write_generic,
1801                 0x00000000);
1802    /* XXX : not implemented */
1803    spr_register(env, SPR_MPC_DER, "DER",
1804                 SPR_NOACCESS, SPR_NOACCESS,
1805                 &spr_read_generic, &spr_write_generic,
1806                 0x00000000);
1807    /* XXX : not implemented */
1808    spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1809                 SPR_NOACCESS, SPR_NOACCESS,
1810                 &spr_read_generic, &spr_write_generic,
1811                 0x00000000);
1812    /* XXX : not implemented */
1813    spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1814                 SPR_NOACCESS, SPR_NOACCESS,
1815                 &spr_read_generic, &spr_write_generic,
1816                 0x00000000);
1817    /* XXX : not implemented */
1818    spr_register(env, SPR_MPC_CMPE, "CMPE",
1819                 SPR_NOACCESS, SPR_NOACCESS,
1820                 &spr_read_generic, &spr_write_generic,
1821                 0x00000000);
1822    /* XXX : not implemented */
1823    spr_register(env, SPR_MPC_CMPF, "CMPF",
1824                 SPR_NOACCESS, SPR_NOACCESS,
1825                 &spr_read_generic, &spr_write_generic,
1826                 0x00000000);
1827    /* XXX : not implemented */
1828    spr_register(env, SPR_MPC_CMPG, "CMPG",
1829                 SPR_NOACCESS, SPR_NOACCESS,
1830                 &spr_read_generic, &spr_write_generic,
1831                 0x00000000);
1832    /* XXX : not implemented */
1833    spr_register(env, SPR_MPC_CMPH, "CMPH",
1834                 SPR_NOACCESS, SPR_NOACCESS,
1835                 &spr_read_generic, &spr_write_generic,
1836                 0x00000000);
1837    /* XXX : not implemented */
1838    spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1839                 SPR_NOACCESS, SPR_NOACCESS,
1840                 &spr_read_generic, &spr_write_generic,
1841                 0x00000000);
1842    /* XXX : not implemented */
1843    spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1844                 SPR_NOACCESS, SPR_NOACCESS,
1845                 &spr_read_generic, &spr_write_generic,
1846                 0x00000000);
1847    /* XXX : not implemented */
1848    spr_register(env, SPR_MPC_BAR, "BAR",
1849                 SPR_NOACCESS, SPR_NOACCESS,
1850                 &spr_read_generic, &spr_write_generic,
1851                 0x00000000);
1852    /* XXX : not implemented */
1853    spr_register(env, SPR_MPC_DPDR, "DPDR",
1854                 SPR_NOACCESS, SPR_NOACCESS,
1855                 &spr_read_generic, &spr_write_generic,
1856                 0x00000000);
1857    /* XXX : not implemented */
1858    spr_register(env, SPR_MPC_IMMR, "IMMR",
1859                 SPR_NOACCESS, SPR_NOACCESS,
1860                 &spr_read_generic, &spr_write_generic,
1861                 0x00000000);
1862}
1863
1864static void register_5xx_sprs(CPUPPCState *env)
1865{
1866    /* XXX : not implemented */
1867    spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1868                 SPR_NOACCESS, SPR_NOACCESS,
1869                 &spr_read_generic, &spr_write_generic,
1870                 0x00000000);
1871    /* XXX : not implemented */
1872    spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1873                 SPR_NOACCESS, SPR_NOACCESS,
1874                 &spr_read_generic, &spr_write_generic,
1875                 0x00000000);
1876    /* XXX : not implemented */
1877    spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1878                 SPR_NOACCESS, SPR_NOACCESS,
1879                 &spr_read_generic, &spr_write_generic,
1880                 0x00000000);
1881    /* XXX : not implemented */
1882    spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1883                 SPR_NOACCESS, SPR_NOACCESS,
1884                 &spr_read_generic, &spr_write_generic,
1885                 0x00000000);
1886    /* XXX : not implemented */
1887    spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1888                 SPR_NOACCESS, SPR_NOACCESS,
1889                 &spr_read_generic, &spr_write_generic,
1890                 0x00000000);
1891    /* XXX : not implemented */
1892    spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1893                 SPR_NOACCESS, SPR_NOACCESS,
1894                 &spr_read_generic, &spr_write_generic,
1895                 0x00000000);
1896    /* XXX : not implemented */
1897    spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1898                 SPR_NOACCESS, SPR_NOACCESS,
1899                 &spr_read_generic, &spr_write_generic,
1900                 0x00000000);
1901    /* XXX : not implemented */
1902    spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1903                 SPR_NOACCESS, SPR_NOACCESS,
1904                 &spr_read_generic, &spr_write_generic,
1905                 0x00000000);
1906    /* XXX : not implemented */
1907    spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1908                 SPR_NOACCESS, SPR_NOACCESS,
1909                 &spr_read_generic, &spr_write_generic,
1910                 0x00000000);
1911    /* XXX : not implemented */
1912    spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1913                 SPR_NOACCESS, SPR_NOACCESS,
1914                 &spr_read_generic, &spr_write_generic,
1915                 0x00000000);
1916    /* XXX : not implemented */
1917    spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1918                 SPR_NOACCESS, SPR_NOACCESS,
1919                 &spr_read_generic, &spr_write_generic,
1920                 0x00000000);
1921    /* XXX : not implemented */
1922    spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1923                 SPR_NOACCESS, SPR_NOACCESS,
1924                 &spr_read_generic, &spr_write_generic,
1925                 0x00000000);
1926    /* XXX : not implemented */
1927    spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1928                 SPR_NOACCESS, SPR_NOACCESS,
1929                 &spr_read_generic, &spr_write_generic,
1930                 0x00000000);
1931    /* XXX : not implemented */
1932    spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1933                 SPR_NOACCESS, SPR_NOACCESS,
1934                 &spr_read_generic, &spr_write_generic,
1935                 0x00000000);
1936    /* XXX : not implemented */
1937    spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1938                 SPR_NOACCESS, SPR_NOACCESS,
1939                 &spr_read_generic, &spr_write_generic,
1940                 0x00000000);
1941    /* XXX : not implemented */
1942    spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1943                 SPR_NOACCESS, SPR_NOACCESS,
1944                 &spr_read_generic, &spr_write_generic,
1945                 0x00000000);
1946    /* XXX : not implemented */
1947    spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1948                 SPR_NOACCESS, SPR_NOACCESS,
1949                 &spr_read_generic, &spr_write_generic,
1950                 0x00000000);
1951    /* XXX : not implemented */
1952    spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1953                 SPR_NOACCESS, SPR_NOACCESS,
1954                 &spr_read_generic, &spr_write_generic,
1955                 0x00000000);
1956    /* XXX : not implemented */
1957    spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1958                 SPR_NOACCESS, SPR_NOACCESS,
1959                 &spr_read_generic, &spr_write_generic,
1960                 0x00000000);
1961    /* XXX : not implemented */
1962    spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1963                 SPR_NOACCESS, SPR_NOACCESS,
1964                 &spr_read_generic, &spr_write_generic,
1965                 0x00000000);
1966    /* XXX : not implemented */
1967    spr_register(env, SPR_RCPU_FPECR, "FPECR",
1968                 SPR_NOACCESS, SPR_NOACCESS,
1969                 &spr_read_generic, &spr_write_generic,
1970                 0x00000000);
1971}
1972
1973static void register_8xx_sprs(CPUPPCState *env)
1974{
1975    /* XXX : not implemented */
1976    spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1977                 SPR_NOACCESS, SPR_NOACCESS,
1978                 &spr_read_generic, &spr_write_generic,
1979                 0x00000000);
1980    /* XXX : not implemented */
1981    spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1982                 SPR_NOACCESS, SPR_NOACCESS,
1983                 &spr_read_generic, &spr_write_generic,
1984                 0x00000000);
1985    /* XXX : not implemented */
1986    spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1987                 SPR_NOACCESS, SPR_NOACCESS,
1988                 &spr_read_generic, &spr_write_generic,
1989                 0x00000000);
1990    /* XXX : not implemented */
1991    spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1992                 SPR_NOACCESS, SPR_NOACCESS,
1993                 &spr_read_generic, &spr_write_generic,
1994                 0x00000000);
1995    /* XXX : not implemented */
1996    spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1997                 SPR_NOACCESS, SPR_NOACCESS,
1998                 &spr_read_generic, &spr_write_generic,
1999                 0x00000000);
2000    /* XXX : not implemented */

2001    spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2002                 SPR_NOACCESS, SPR_NOACCESS,
2003                 &spr_read_generic, &spr_write_generic,
2004                 0x00000000);
2005    /* XXX : not implemented */
2006    spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2007                 SPR_NOACCESS, SPR_NOACCESS,
2008                 &spr_read_generic, &spr_write_generic,
2009                 0x00000000);
2010    /* XXX : not implemented */
2011    spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2012                 SPR_NOACCESS, SPR_NOACCESS,
2013                 &spr_read_generic, &spr_write_generic,
2014                 0x00000000);
2015    /* XXX : not implemented */
2016    spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2017                 SPR_NOACCESS, SPR_NOACCESS,
2018                 &spr_read_generic, &spr_write_generic,
2019                 0x00000000);
2020    /* XXX : not implemented */
2021    spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2022                 SPR_NOACCESS, SPR_NOACCESS,
2023                 &spr_read_generic, &spr_write_generic,
2024                 0x00000000);
2025    /* XXX : not implemented */
2026    spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2027                 SPR_NOACCESS, SPR_NOACCESS,
2028                 &spr_read_generic, &spr_write_generic,
2029                 0x00000000);
2030    /* XXX : not implemented */
2031    spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2032                 SPR_NOACCESS, SPR_NOACCESS,
2033                 &spr_read_generic, &spr_write_generic,
2034                 0x00000000);
2035    /* XXX : not implemented */
2036    spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2037                 SPR_NOACCESS, SPR_NOACCESS,
2038                 &spr_read_generic, &spr_write_generic,
2039                 0x00000000);
2040    /* XXX : not implemented */
2041    spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2042                 SPR_NOACCESS, SPR_NOACCESS,
2043                 &spr_read_generic, &spr_write_generic,
2044                 0x00000000);
2045    /* XXX : not implemented */
2046    spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2047                 SPR_NOACCESS, SPR_NOACCESS,
2048                 &spr_read_generic, &spr_write_generic,
2049                 0x00000000);
2050    /* XXX : not implemented */
2051    spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2052                 SPR_NOACCESS, SPR_NOACCESS,
2053                 &spr_read_generic, &spr_write_generic,
2054                 0x00000000);
2055    /* XXX : not implemented */
2056    spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2057                 SPR_NOACCESS, SPR_NOACCESS,
2058                 &spr_read_generic, &spr_write_generic,
2059                 0x00000000);
2060    /* XXX : not implemented */
2061    spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2062                 SPR_NOACCESS, SPR_NOACCESS,
2063                 &spr_read_generic, &spr_write_generic,
2064                 0x00000000);
2065    /* XXX : not implemented */
2066    spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2067                 SPR_NOACCESS, SPR_NOACCESS,
2068                 &spr_read_generic, &spr_write_generic,
2069                 0x00000000);
2070    /* XXX : not implemented */
2071    spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2072                 SPR_NOACCESS, SPR_NOACCESS,
2073                 &spr_read_generic, &spr_write_generic,
2074                 0x00000000);
2075    /* XXX : not implemented */
2076    spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2077                 SPR_NOACCESS, SPR_NOACCESS,
2078                 &spr_read_generic, &spr_write_generic,
2079                 0x00000000);
2080    /* XXX : not implemented */
2081    spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2082                 SPR_NOACCESS, SPR_NOACCESS,
2083                 &spr_read_generic, &spr_write_generic,
2084                 0x00000000);
2085    /* XXX : not implemented */
2086    spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2087                 SPR_NOACCESS, SPR_NOACCESS,
2088                 &spr_read_generic, &spr_write_generic,
2089                 0x00000000);
2090    /* XXX : not implemented */
2091    spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2092                 SPR_NOACCESS, SPR_NOACCESS,
2093                 &spr_read_generic, &spr_write_generic,
2094                 0x00000000);
2095    /* XXX : not implemented */
2096    spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2097                 SPR_NOACCESS, SPR_NOACCESS,
2098                 &spr_read_generic, &spr_write_generic,
2099                 0x00000000);
2100}
2101
2102/*
2103 * AMR     => SPR 29 (Power 2.04)
2104 * CTRL    => SPR 136 (Power 2.04)
2105 * CTRL    => SPR 152 (Power 2.04)
2106 * SCOMC   => SPR 276 (64 bits ?)
2107 * SCOMD   => SPR 277 (64 bits ?)
2108 * TBU40   => SPR 286 (Power 2.04 hypv)
2109 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2110 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2111 * HDSISR  => SPR 306 (Power 2.04 hypv)
2112 * HDAR    => SPR 307 (Power 2.04 hypv)
2113 * PURR    => SPR 309 (Power 2.04 hypv)
2114 * HDEC    => SPR 310 (Power 2.04 hypv)
2115 * HIOR    => SPR 311 (hypv)
2116 * RMOR    => SPR 312 (970)
2117 * HRMOR   => SPR 313 (Power 2.04 hypv)
2118 * HSRR0   => SPR 314 (Power 2.04 hypv)
2119 * HSRR1   => SPR 315 (Power 2.04 hypv)
2120 * LPIDR   => SPR 317 (970)
2121 * EPR     => SPR 702 (Power 2.04 emb)
2122 * perf    => 768-783 (Power 2.04)
2123 * perf    => 784-799 (Power 2.04)
2124 * PPR     => SPR 896 (Power 2.04)
2125 * DABRX   => 1015    (Power 2.04 hypv)
2126 * FPECR   => SPR 1022 (?)
2127 * ... and more (thermal management, performance counters, ...)
2128 */
2129
2130/*****************************************************************************/
2131/* Exception vectors models                                                  */
2132static void init_excp_4xx_real(CPUPPCState *env)
2133{
2134#if !defined(CONFIG_USER_ONLY)
2135    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2136    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2137    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2138    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2139    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2140    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2141    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2142    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2143    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2144    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2145    env->ivor_mask = 0x0000FFF0UL;
2146    env->ivpr_mask = 0xFFFF0000UL;
2147    /* Hardware reset vector */
2148    env->hreset_vector = 0xFFFFFFFCUL;
2149#endif
2150}
2151
2152static void init_excp_4xx_softmmu(CPUPPCState *env)
2153{
2154#if !defined(CONFIG_USER_ONLY)
2155    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2156    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2157    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2158    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2159    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2160    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2161    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2162    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2163    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2164    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2165    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2166    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2167    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2168    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2169    env->ivor_mask = 0x0000FFF0UL;
2170    env->ivpr_mask = 0xFFFF0000UL;
2171    /* Hardware reset vector */
2172    env->hreset_vector = 0xFFFFFFFCUL;
2173#endif
2174}
2175
2176static void init_excp_MPC5xx(CPUPPCState *env)
2177{
2178#if !defined(CONFIG_USER_ONLY)
2179    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2180    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2181    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2182    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2183    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2184    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2185    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2186    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2187    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2188    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2189    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2190    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2191    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2192    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2193    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2194    env->ivor_mask = 0x0000FFF0UL;
2195    env->ivpr_mask = 0xFFFF0000UL;
2196    /* Hardware reset vector */
2197    env->hreset_vector = 0x00000100UL;
2198#endif
2199}
2200
2201static void init_excp_MPC8xx(CPUPPCState *env)
2202{
2203#if !defined(CONFIG_USER_ONLY)
2204    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2205    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2206    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2207    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2208    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2209    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2210    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2211    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2212    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2213    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2214    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2215    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2216    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2217    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2218    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2219    env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2220    env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2221    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2222    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2223    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2224    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2225    env->ivor_mask = 0x0000FFF0UL;
2226    env->ivpr_mask = 0xFFFF0000UL;
2227    /* Hardware reset vector */
2228    env->hreset_vector = 0x00000100UL;
2229#endif
2230}
2231
2232static void init_excp_G2(CPUPPCState *env)
2233{
2234#if !defined(CONFIG_USER_ONLY)
2235    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2236    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2237    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2238    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2239    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2240    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2241    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2242    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2243    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2244    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2245    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2246    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2247    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2248    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2249    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2250    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2251    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2252    /* Hardware reset vector */
2253    env->hreset_vector = 0x00000100UL;
2254#endif
2255}
2256
2257static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2258{
2259#if !defined(CONFIG_USER_ONLY)
2260    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2261    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2262    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2263    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2264    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2265    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2266    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2267    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2268    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2269    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2270    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2271    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2272    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2273    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2274    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2275    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2276    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2277    env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2278    env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2279    env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2280    env->ivor_mask = 0x0000FFF7UL;
2281    env->ivpr_mask = ivpr_mask;
2282    /* Hardware reset vector */
2283    env->hreset_vector = 0xFFFFFFFCUL;
2284#endif
2285}
2286
2287static void init_excp_BookE(CPUPPCState *env)
2288{
2289#if !defined(CONFIG_USER_ONLY)
2290    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2291    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2292    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2293    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2294    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2295    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2296    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2297    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2298    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2299    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2300    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2301    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2302    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2303    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2304    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2305    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2306    env->ivor_mask = 0x0000FFF0UL;
2307    env->ivpr_mask = 0xFFFF0000UL;
2308    /* Hardware reset vector */
2309    env->hreset_vector = 0xFFFFFFFCUL;
2310#endif
2311}
2312
2313static void init_excp_601(CPUPPCState *env)
2314{
2315#if !defined(CONFIG_USER_ONLY)
2316    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2317    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2318    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2319    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2320    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2321    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2322    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2323    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2324    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2325    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2326    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2327    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2328    /* Hardware reset vector */
2329    env->hreset_vector = 0x00000100UL;
2330#endif
2331}
2332
2333static void init_excp_602(CPUPPCState *env)
2334{
2335#if !defined(CONFIG_USER_ONLY)
2336    /* XXX: exception prefix has a special behavior on 602 */
2337    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2338    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2339    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2340    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2341    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2342    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2343    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2344    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2345    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2346    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2347    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2348    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2349    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2350    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2351    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2352    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2353    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2354    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2355    /* Hardware reset vector */
2356    env->hreset_vector = 0x00000100UL;
2357#endif
2358}
2359
2360static void init_excp_603(CPUPPCState *env)
2361{
2362#if !defined(CONFIG_USER_ONLY)
2363    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2364    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2365    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2366    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2367    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2368    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2369    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2370    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2371    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2372    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2373    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2374    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2375    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2376    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2377    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2378    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2379    /* Hardware reset vector */
2380    env->hreset_vector = 0x00000100UL;
2381#endif
2382}
2383
2384static void init_excp_604(CPUPPCState *env)
2385{
2386#if !defined(CONFIG_USER_ONLY)
2387    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2388    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2389    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2390    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2391    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2392    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2393    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2394    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2395    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2396    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2397    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2398    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2399    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2400    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2401    /* Hardware reset vector */
2402    env->hreset_vector = 0x00000100UL;
2403#endif
2404}
2405
2406static void init_excp_7x0(CPUPPCState *env)
2407{
2408#if !defined(CONFIG_USER_ONLY)
2409    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2410    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2411    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2412    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2413    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2414    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2415    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2416    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2417    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2418    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2419    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2420    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2421    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2422    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2423    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2424    /* Hardware reset vector */
2425    env->hreset_vector = 0x00000100UL;
2426#endif
2427}
2428
2429static void init_excp_750cl(CPUPPCState *env)
2430{
2431#if !defined(CONFIG_USER_ONLY)
2432    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2433    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2434    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2435    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2436    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2437    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2438    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2439    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2440    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2441    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2442    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2443    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2444    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2445    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2446    /* Hardware reset vector */
2447    env->hreset_vector = 0x00000100UL;
2448#endif
2449}
2450
2451static void init_excp_750cx(CPUPPCState *env)
2452{
2453#if !defined(CONFIG_USER_ONLY)
2454    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2455    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2456    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2457    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2458    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2459    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2460    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2461    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2462    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2463    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2464    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2465    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2466    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2467    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2468    /* Hardware reset vector */
2469    env->hreset_vector = 0x00000100UL;
2470#endif
2471}
2472
2473/* XXX: Check if this is correct */
2474static void init_excp_7x5(CPUPPCState *env)
2475{
2476#if !defined(CONFIG_USER_ONLY)
2477    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2478    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2479    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2480    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2481    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2482    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2483    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2484    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2485    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2486    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2487    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2488    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2489    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2490    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2491    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2492    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2493    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2494    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2495    /* Hardware reset vector */
2496    env->hreset_vector = 0x00000100UL;
2497#endif
2498}
2499
2500static void init_excp_7400(CPUPPCState *env)
2501{
2502#if !defined(CONFIG_USER_ONLY)
2503    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2504    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2505    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2506    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2507    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2508    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2509    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2510    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2511    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2512    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2513    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2514    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2515    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2516    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2517    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2518    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2519    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2520    /* Hardware reset vector */
2521    env->hreset_vector = 0x00000100UL;
2522#endif
2523}
2524
2525static void init_excp_7450(CPUPPCState *env)
2526{
2527#if !defined(CONFIG_USER_ONLY)
2528    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2529    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2530    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2531    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2532    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2533    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2534    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2535    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2536    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2537    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2538    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2539    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2540    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2541    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2542    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2543    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2544    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2545    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2546    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2547    /* Hardware reset vector */
2548    env->hreset_vector = 0x00000100UL;
2549#endif
2550}
2551
2552#if defined(TARGET_PPC64)
2553static void init_excp_970(CPUPPCState *env)
2554{
2555#if !defined(CONFIG_USER_ONLY)
2556    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2557    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2558    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2559    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2560    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2561    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2562    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2563    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2564    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2565    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2566    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2567    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2568    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2569    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2570    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2571    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2572    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2573    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
2574    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
2575    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
2576    /* Hardware reset vector */
2577    env->hreset_vector = 0x0000000000000100ULL;
2578#endif
2579}
2580
2581static void init_excp_POWER7(CPUPPCState *env)
2582{
2583#if !defined(CONFIG_USER_ONLY)
2584    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2585    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2586    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2587    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2588    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2589    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2590    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2591    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2592    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2593    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2594    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2595    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2596    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2597    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2598    env->excp_vectors[POWERPC_EXCP_HDSI]     = 0x00000E00;
2599    env->excp_vectors[POWERPC_EXCP_HISI]     = 0x00000E20;
2600    env->excp_vectors[POWERPC_EXCP_HV_EMU]   = 0x00000E40;
2601    env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2602    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2603    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2604    env->excp_vectors[POWERPC_EXCP_VSXU]     = 0x00000F40;
2605    /* Hardware reset vector */
2606    env->hreset_vector = 0x0000000000000100ULL;
2607#endif
2608}
2609
2610static void init_excp_POWER8(CPUPPCState *env)
2611{
2612    init_excp_POWER7(env);
2613
2614#if !defined(CONFIG_USER_ONLY)
2615    env->excp_vectors[POWERPC_EXCP_SDOOR]    = 0x00000A00;
2616    env->excp_vectors[POWERPC_EXCP_FU]       = 0x00000F60;
2617    env->excp_vectors[POWERPC_EXCP_HV_FU]    = 0x00000F80;
2618    env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2619#endif
2620}
2621
2622static void init_excp_POWER9(CPUPPCState *env)
2623{
2624    init_excp_POWER8(env);
2625
2626#if !defined(CONFIG_USER_ONLY)
2627    env->excp_vectors[POWERPC_EXCP_HVIRT]    = 0x00000EA0;
2628    env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2629#endif
2630}
2631
2632static void init_excp_POWER10(CPUPPCState *env)
2633{
2634    init_excp_POWER9(env);
2635}
2636
2637#endif
2638
2639/*****************************************************************************/
2640/* Power management enable checks                                            */
2641static int check_pow_none(CPUPPCState *env)
2642{
2643    return 0;
2644}
2645
2646static int check_pow_nocheck(CPUPPCState *env)
2647{
2648    return 1;
2649}
2650
2651static int check_pow_hid0(CPUPPCState *env)
2652{
2653    if (env->spr[SPR_HID0] & 0x00E00000) {
2654        return 1;
2655    }
2656
2657    return 0;
2658}
2659
2660static int check_pow_hid0_74xx(CPUPPCState *env)
2661{
2662    if (env->spr[SPR_HID0] & 0x00600000) {
2663        return 1;
2664    }
2665
2666    return 0;
2667}
2668
2669/*****************************************************************************/
2670/* PowerPC implementations definitions                                       */
2671
2672#define POWERPC_FAMILY(_name)                                               \
2673    static void                                                             \
2674    glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2675                                                                            \
2676    static const TypeInfo                                                   \
2677    glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
2678        .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
2679        .parent = TYPE_POWERPC_CPU,                                         \
2680        .abstract = true,                                                   \
2681        .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
2682    };                                                                      \
2683                                                                            \
2684    static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
2685    {                                                                       \
2686        type_register_static(                                               \
2687            &glue(glue(ppc_, _name), _cpu_family_type_info));               \
2688    }                                                                       \
2689                                                                            \
2690    type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
2691                                                                            \
2692    static void glue(glue(ppc_, _name), _cpu_family_class_init)
2693
2694static void init_proc_401(CPUPPCState *env)
2695{
2696    register_40x_sprs(env);
2697    register_401_403_sprs(env);
2698    register_401_sprs(env);
2699    init_excp_4xx_real(env);
2700    env->dcache_line_size = 32;
2701    env->icache_line_size = 32;
2702    /* Allocate hardware IRQ controller */
2703    ppc40x_irq_init(env_archcpu(env));
2704
2705    SET_FIT_PERIOD(12, 16, 20, 24);
2706    SET_WDT_PERIOD(16, 20, 24, 28);
2707}
2708
2709POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
2710{
2711    DeviceClass *dc = DEVICE_CLASS(oc);
2712    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2713
2714    dc->desc = "PowerPC 401";
2715    pcc->init_proc = init_proc_401;
2716    pcc->check_pow = check_pow_nocheck;
2717    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2718                       PPC_WRTEE | PPC_DCR |
2719                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2720                       PPC_CACHE_DCBZ |
2721                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
2722                       PPC_4xx_COMMON | PPC_40x_EXCP;
2723    pcc->msr_mask = (1ull << MSR_KEY) |
2724                    (1ull << MSR_POW) |
2725                    (1ull << MSR_CE) |
2726                    (1ull << MSR_ILE) |
2727                    (1ull << MSR_EE) |
2728                    (1ull << MSR_PR) |
2729                    (1ull << MSR_ME) |
2730                    (1ull << MSR_DE) |
2731                    (1ull << MSR_LE);
2732    pcc->mmu_model = POWERPC_MMU_REAL;
2733    pcc->excp_model = POWERPC_EXCP_40x;
2734    pcc->bus_model = PPC_FLAGS_INPUT_401;
2735    pcc->bfd_mach = bfd_mach_ppc_403;
2736    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2737                 POWERPC_FLAG_BUS_CLK;
2738}
2739
2740static void init_proc_401x2(CPUPPCState *env)
2741{
2742    register_40x_sprs(env);
2743    register_401_403_sprs(env);
2744    register_401x2_sprs(env);
2745    register_compress_sprs(env);
2746    /* Memory management */
2747#if !defined(CONFIG_USER_ONLY)
2748    env->nb_tlb = 64;
2749    env->nb_ways = 1;
2750    env->id_tlbs = 0;
2751    env->tlb_type = TLB_EMB;
2752#endif
2753    init_excp_4xx_softmmu(env);
2754    env->dcache_line_size = 32;
2755    env->icache_line_size = 32;
2756    /* Allocate hardware IRQ controller */
2757    ppc40x_irq_init(env_archcpu(env));
2758
2759    SET_FIT_PERIOD(12, 16, 20, 24);
2760    SET_WDT_PERIOD(16, 20, 24, 28);
2761}
2762
2763POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
2764{
2765    DeviceClass *dc = DEVICE_CLASS(oc);
2766    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2767
2768    dc->desc = "PowerPC 401x2";
2769    pcc->init_proc = init_proc_401x2;
2770    pcc->check_pow = check_pow_nocheck;
2771    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2772                       PPC_DCR | PPC_WRTEE |
2773                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2774                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2775                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
2776                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2777                       PPC_4xx_COMMON | PPC_40x_EXCP;
2778    pcc->msr_mask = (1ull << 20) |
2779                    (1ull << MSR_KEY) |
2780                    (1ull << MSR_POW) |
2781                    (1ull << MSR_CE) |
2782                    (1ull << MSR_ILE) |
2783                    (1ull << MSR_EE) |
2784                    (1ull << MSR_PR) |
2785                    (1ull << MSR_ME) |
2786                    (1ull << MSR_DE) |
2787                    (1ull << MSR_IR) |
2788                    (1ull << MSR_DR) |
2789                    (1ull << MSR_LE);
2790    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2791    pcc->excp_model = POWERPC_EXCP_40x;
2792    pcc->bus_model = PPC_FLAGS_INPUT_401;
2793    pcc->bfd_mach = bfd_mach_ppc_403;
2794    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2795                 POWERPC_FLAG_BUS_CLK;
2796}
2797
2798static void init_proc_401x3(CPUPPCState *env)
2799{
2800    register_40x_sprs(env);
2801    register_401_403_sprs(env);
2802    register_401_sprs(env);
2803    register_401x2_sprs(env);
2804    register_compress_sprs(env);
2805    init_excp_4xx_softmmu(env);
2806    env->dcache_line_size = 32;
2807    env->icache_line_size = 32;
2808    /* Allocate hardware IRQ controller */
2809    ppc40x_irq_init(env_archcpu(env));
2810
2811    SET_FIT_PERIOD(12, 16, 20, 24);
2812    SET_WDT_PERIOD(16, 20, 24, 28);
2813}
2814
2815POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
2816{
2817    DeviceClass *dc = DEVICE_CLASS(oc);
2818    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2819
2820    dc->desc = "PowerPC 401x3";
2821    pcc->init_proc = init_proc_401x3;
2822    pcc->check_pow = check_pow_nocheck;
2823    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2824                       PPC_DCR | PPC_WRTEE |
2825                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2826                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2827                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
2828                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2829                       PPC_4xx_COMMON | PPC_40x_EXCP;
2830    pcc->msr_mask = (1ull << 20) |
2831                    (1ull << MSR_KEY) |
2832                    (1ull << MSR_POW) |
2833                    (1ull << MSR_CE) |
2834                    (1ull << MSR_ILE) |
2835                    (1ull << MSR_EE) |
2836                    (1ull << MSR_PR) |
2837                    (1ull << MSR_ME) |
2838                    (1ull << MSR_DWE) |
2839                    (1ull << MSR_DE) |
2840                    (1ull << MSR_IR) |
2841                    (1ull << MSR_DR) |
2842                    (1ull << MSR_LE);
2843    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2844    pcc->excp_model = POWERPC_EXCP_40x;
2845    pcc->bus_model = PPC_FLAGS_INPUT_401;
2846    pcc->bfd_mach = bfd_mach_ppc_403;
2847    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2848                 POWERPC_FLAG_BUS_CLK;
2849}
2850
2851static void init_proc_IOP480(CPUPPCState *env)
2852{
2853    register_40x_sprs(env);
2854    register_401_403_sprs(env);
2855    register_401x2_sprs(env);
2856    register_compress_sprs(env);
2857    /* Memory management */
2858#if !defined(CONFIG_USER_ONLY)
2859    env->nb_tlb = 64;
2860    env->nb_ways = 1;
2861    env->id_tlbs = 0;
2862    env->tlb_type = TLB_EMB;
2863#endif
2864    init_excp_4xx_softmmu(env);
2865    env->dcache_line_size = 32;
2866    env->icache_line_size = 32;
2867    /* Allocate hardware IRQ controller */
2868    ppc40x_irq_init(env_archcpu(env));
2869
2870    SET_FIT_PERIOD(8, 12, 16, 20);
2871    SET_WDT_PERIOD(16, 20, 24, 28);
2872}
2873
2874POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
2875{
2876    DeviceClass *dc = DEVICE_CLASS(oc);
2877    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2878
2879    dc->desc = "IOP480";
2880    pcc->init_proc = init_proc_IOP480;
2881    pcc->check_pow = check_pow_nocheck;
2882    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2883                       PPC_DCR | PPC_WRTEE |
2884                       PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |
2885                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2886                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
2887                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2888                       PPC_4xx_COMMON | PPC_40x_EXCP;
2889    pcc->msr_mask = (1ull << 20) |
2890                    (1ull << MSR_KEY) |
2891                    (1ull << MSR_POW) |
2892                    (1ull << MSR_CE) |
2893                    (1ull << MSR_ILE) |
2894                    (1ull << MSR_EE) |
2895                    (1ull << MSR_PR) |
2896                    (1ull << MSR_ME) |
2897                    (1ull << MSR_DE) |
2898                    (1ull << MSR_IR) |
2899                    (1ull << MSR_DR) |
2900                    (1ull << MSR_LE);
2901    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2902    pcc->excp_model = POWERPC_EXCP_40x;
2903    pcc->bus_model = PPC_FLAGS_INPUT_401;
2904    pcc->bfd_mach = bfd_mach_ppc_403;
2905    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2906                 POWERPC_FLAG_BUS_CLK;
2907}
2908
2909static void init_proc_403(CPUPPCState *env)
2910{
2911    register_40x_sprs(env);
2912    register_401_403_sprs(env);
2913    register_403_sprs(env);
2914    register_403_real_sprs(env);
2915    init_excp_4xx_real(env);
2916    env->dcache_line_size = 32;
2917    env->icache_line_size = 32;
2918    /* Allocate hardware IRQ controller */
2919    ppc40x_irq_init(env_archcpu(env));
2920
2921    SET_FIT_PERIOD(8, 12, 16, 20);
2922    SET_WDT_PERIOD(16, 20, 24, 28);
2923}
2924
2925POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
2926{
2927    DeviceClass *dc = DEVICE_CLASS(oc);
2928    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2929
2930    dc->desc = "PowerPC 403";
2931    pcc->init_proc = init_proc_403;
2932    pcc->check_pow = check_pow_nocheck;
2933    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2934                       PPC_DCR | PPC_WRTEE |
2935                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2936                       PPC_CACHE_DCBZ |
2937                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
2938                       PPC_4xx_COMMON | PPC_40x_EXCP;
2939    pcc->msr_mask = (1ull << MSR_POW) |
2940                    (1ull << MSR_CE) |
2941                    (1ull << MSR_ILE) |
2942                    (1ull << MSR_EE) |
2943                    (1ull << MSR_PR) |
2944                    (1ull << MSR_ME) |
2945                    (1ull << MSR_PE) |
2946                    (1ull << MSR_PX) |
2947                    (1ull << MSR_LE);
2948    pcc->mmu_model = POWERPC_MMU_REAL;
2949    pcc->excp_model = POWERPC_EXCP_40x;
2950    pcc->bus_model = PPC_FLAGS_INPUT_401;
2951    pcc->bfd_mach = bfd_mach_ppc_403;
2952    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
2953                 POWERPC_FLAG_BUS_CLK;
2954}
2955
2956static void init_proc_403GCX(CPUPPCState *env)
2957{
2958    register_40x_sprs(env);
2959    register_401_403_sprs(env);
2960    register_403_sprs(env);
2961    register_403_real_sprs(env);
2962    register_403_mmu_sprs(env);
2963    /* Bus access control */
2964    /* not emulated, as QEMU never does speculative access */
2965    spr_register(env, SPR_40x_SGR, "SGR",
2966                 SPR_NOACCESS, SPR_NOACCESS,
2967                 &spr_read_generic, &spr_write_generic,
2968                 0xFFFFFFFF);
2969    /* not emulated, as QEMU do not emulate caches */
2970    spr_register(env, SPR_40x_DCWR, "DCWR",
2971                 SPR_NOACCESS, SPR_NOACCESS,
2972                 &spr_read_generic, &spr_write_generic,
2973                 0x00000000);
2974    /* Memory management */
2975#if !defined(CONFIG_USER_ONLY)
2976    env->nb_tlb = 64;
2977    env->nb_ways = 1;
2978    env->id_tlbs = 0;
2979    env->tlb_type = TLB_EMB;
2980#endif
2981    init_excp_4xx_softmmu(env);
2982    env->dcache_line_size = 32;
2983    env->icache_line_size = 32;
2984    /* Allocate hardware IRQ controller */
2985    ppc40x_irq_init(env_archcpu(env));
2986
2987    SET_FIT_PERIOD(8, 12, 16, 20);
2988    SET_WDT_PERIOD(16, 20, 24, 28);
2989}
2990
2991POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
2992{
2993    DeviceClass *dc = DEVICE_CLASS(oc);
2994    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2995
2996    dc->desc = "PowerPC 403 GCX";
2997    pcc->init_proc = init_proc_403GCX;
2998    pcc->check_pow = check_pow_nocheck;
2999    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3000                       PPC_DCR | PPC_WRTEE |

3001                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3002                       PPC_CACHE_DCBZ |
3003                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3004                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3005                       PPC_4xx_COMMON | PPC_40x_EXCP;
3006    pcc->msr_mask = (1ull << MSR_POW) |
3007                    (1ull << MSR_CE) |
3008                    (1ull << MSR_ILE) |
3009                    (1ull << MSR_EE) |
3010                    (1ull << MSR_PR) |
3011                    (1ull << MSR_ME) |
3012                    (1ull << MSR_PE) |
3013                    (1ull << MSR_PX) |
3014                    (1ull << MSR_LE);
3015    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3016    pcc->excp_model = POWERPC_EXCP_40x;
3017    pcc->bus_model = PPC_FLAGS_INPUT_401;
3018    pcc->bfd_mach = bfd_mach_ppc_403;
3019    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3020                 POWERPC_FLAG_BUS_CLK;
3021}
3022
3023static void init_proc_405(CPUPPCState *env)
3024{
3025    /* Time base */
3026    register_tbl(env);
3027    register_40x_sprs(env);
3028    register_405_sprs(env);
3029    /* Bus access control */
3030    /* not emulated, as QEMU never does speculative access */
3031    spr_register(env, SPR_40x_SGR, "SGR",
3032                 SPR_NOACCESS, SPR_NOACCESS,
3033                 &spr_read_generic, &spr_write_generic,
3034                 0xFFFFFFFF);
3035    /* not emulated, as QEMU do not emulate caches */
3036    spr_register(env, SPR_40x_DCWR, "DCWR",
3037                 SPR_NOACCESS, SPR_NOACCESS,
3038                 &spr_read_generic, &spr_write_generic,
3039                 0x00000000);
3040    /* Memory management */
3041#if !defined(CONFIG_USER_ONLY)
3042    env->nb_tlb = 64;
3043    env->nb_ways = 1;
3044    env->id_tlbs = 0;
3045    env->tlb_type = TLB_EMB;
3046#endif
3047    init_excp_4xx_softmmu(env);
3048    env->dcache_line_size = 32;
3049    env->icache_line_size = 32;
3050    /* Allocate hardware IRQ controller */
3051    ppc40x_irq_init(env_archcpu(env));
3052
3053    SET_FIT_PERIOD(8, 12, 16, 20);
3054    SET_WDT_PERIOD(16, 20, 24, 28);
3055}
3056
3057POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3058{
3059    DeviceClass *dc = DEVICE_CLASS(oc);
3060    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3061
3062    dc->desc = "PowerPC 405";
3063    pcc->init_proc = init_proc_405;
3064    pcc->check_pow = check_pow_nocheck;
3065    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3066                       PPC_DCR | PPC_WRTEE |
3067                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3068                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3069                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3070                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3071                       PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3072    pcc->msr_mask = (1ull << MSR_POW) |
3073                    (1ull << MSR_CE) |
3074                    (1ull << MSR_EE) |
3075                    (1ull << MSR_PR) |
3076                    (1ull << MSR_FP) |
3077                    (1ull << MSR_DWE) |
3078                    (1ull << MSR_DE) |
3079                    (1ull << MSR_IR) |
3080                    (1ull << MSR_DR);
3081    pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3082    pcc->excp_model = POWERPC_EXCP_40x;
3083    pcc->bus_model = PPC_FLAGS_INPUT_405;
3084    pcc->bfd_mach = bfd_mach_ppc_403;
3085    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3086                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3087}
3088
3089static void init_proc_440EP(CPUPPCState *env)
3090{
3091    /* Time base */
3092    register_tbl(env);
3093    register_BookE_sprs(env, 0x000000000000FFFFULL);
3094    register_440_sprs(env);
3095    register_usprgh_sprs(env);
3096    /* Processor identification */
3097    spr_register(env, SPR_BOOKE_PIR, "PIR",
3098                 SPR_NOACCESS, SPR_NOACCESS,
3099                 &spr_read_generic, &spr_write_pir,
3100                 0x00000000);
3101    /* XXX : not implemented */
3102    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3103                 SPR_NOACCESS, SPR_NOACCESS,
3104                 &spr_read_generic, &spr_write_generic,
3105                 0x00000000);
3106    /* XXX : not implemented */
3107    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3108                 SPR_NOACCESS, SPR_NOACCESS,
3109                 &spr_read_generic, &spr_write_generic,
3110                 0x00000000);
3111    /* XXX : not implemented */
3112    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3113                 SPR_NOACCESS, SPR_NOACCESS,
3114                 &spr_read_generic, &spr_write_generic,
3115                 0x00000000);
3116    /* XXX : not implemented */
3117    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3118                 SPR_NOACCESS, SPR_NOACCESS,
3119                 &spr_read_generic, &spr_write_generic,
3120                 0x00000000);
3121    /* XXX : not implemented */
3122    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3123                 SPR_NOACCESS, SPR_NOACCESS,
3124                 &spr_read_generic, &spr_write_generic,
3125                 0x00000000);
3126    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3127                 SPR_NOACCESS, SPR_NOACCESS,
3128                 &spr_read_generic, &spr_write_generic,
3129                 0x00000000);
3130    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3131                 SPR_NOACCESS, SPR_NOACCESS,
3132                 &spr_read_generic, &spr_write_generic,
3133                 0x00000000);
3134    /* XXX : not implemented */
3135    spr_register(env, SPR_440_CCR1, "CCR1",
3136                 SPR_NOACCESS, SPR_NOACCESS,
3137                 &spr_read_generic, &spr_write_generic,
3138                 0x00000000);
3139    /* Memory management */
3140#if !defined(CONFIG_USER_ONLY)
3141    env->nb_tlb = 64;
3142    env->nb_ways = 1;
3143    env->id_tlbs = 0;
3144    env->tlb_type = TLB_EMB;
3145#endif
3146    init_excp_BookE(env);
3147    env->dcache_line_size = 32;
3148    env->icache_line_size = 32;
3149    ppc40x_irq_init(env_archcpu(env));
3150
3151    SET_FIT_PERIOD(12, 16, 20, 24);
3152    SET_WDT_PERIOD(20, 24, 28, 32);
3153}
3154
3155POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3156{
3157    DeviceClass *dc = DEVICE_CLASS(oc);
3158    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3159
3160    dc->desc = "PowerPC 440 EP";
3161    pcc->init_proc = init_proc_440EP;
3162    pcc->check_pow = check_pow_nocheck;
3163    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3164                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3165                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3166                       PPC_FLOAT_STFIWX |
3167                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3168                       PPC_CACHE | PPC_CACHE_ICBI |
3169                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3170                       PPC_MEM_TLBSYNC | PPC_MFTB |
3171                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3172                       PPC_440_SPEC;
3173    pcc->msr_mask = (1ull << MSR_POW) |
3174                    (1ull << MSR_CE) |
3175                    (1ull << MSR_EE) |
3176                    (1ull << MSR_PR) |
3177                    (1ull << MSR_FP) |
3178                    (1ull << MSR_ME) |
3179                    (1ull << MSR_FE0) |
3180                    (1ull << MSR_DWE) |
3181                    (1ull << MSR_DE) |
3182                    (1ull << MSR_FE1) |
3183                    (1ull << MSR_IR) |
3184                    (1ull << MSR_DR);
3185    pcc->mmu_model = POWERPC_MMU_BOOKE;
3186    pcc->excp_model = POWERPC_EXCP_BOOKE;
3187    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3188    pcc->bfd_mach = bfd_mach_ppc_403;
3189    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3190                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3191}
3192
3193POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3194{
3195    DeviceClass *dc = DEVICE_CLASS(oc);
3196    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3197
3198    dc->desc = "PowerPC 460 EX";
3199    pcc->init_proc = init_proc_440EP;
3200    pcc->check_pow = check_pow_nocheck;
3201    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3202                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3203                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3204                       PPC_FLOAT_STFIWX |
3205                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3206                       PPC_CACHE | PPC_CACHE_ICBI |
3207                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3208                       PPC_MEM_TLBSYNC | PPC_MFTB |
3209                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3210                       PPC_440_SPEC;
3211    pcc->msr_mask = (1ull << MSR_POW) |
3212                    (1ull << MSR_CE) |
3213                    (1ull << MSR_EE) |
3214                    (1ull << MSR_PR) |
3215                    (1ull << MSR_FP) |
3216                    (1ull << MSR_ME) |
3217                    (1ull << MSR_FE0) |
3218                    (1ull << MSR_DWE) |
3219                    (1ull << MSR_DE) |
3220                    (1ull << MSR_FE1) |
3221                    (1ull << MSR_IR) |
3222                    (1ull << MSR_DR);
3223    pcc->mmu_model = POWERPC_MMU_BOOKE;
3224    pcc->excp_model = POWERPC_EXCP_BOOKE;
3225    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3226    pcc->bfd_mach = bfd_mach_ppc_403;
3227    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3228                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3229}
3230
3231static void init_proc_440GP(CPUPPCState *env)
3232{
3233    /* Time base */
3234    register_tbl(env);
3235    register_BookE_sprs(env, 0x000000000000FFFFULL);
3236    register_440_sprs(env);
3237    register_usprgh_sprs(env);
3238    /* Processor identification */
3239    spr_register(env, SPR_BOOKE_PIR, "PIR",
3240                 SPR_NOACCESS, SPR_NOACCESS,
3241                 &spr_read_generic, &spr_write_pir,
3242                 0x00000000);
3243    /* XXX : not implemented */
3244    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3245                 SPR_NOACCESS, SPR_NOACCESS,
3246                 &spr_read_generic, &spr_write_generic,
3247                 0x00000000);
3248    /* XXX : not implemented */
3249    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3250                 SPR_NOACCESS, SPR_NOACCESS,
3251                 &spr_read_generic, &spr_write_generic,
3252                 0x00000000);
3253    /* XXX : not implemented */
3254    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3255                 SPR_NOACCESS, SPR_NOACCESS,
3256                 &spr_read_generic, &spr_write_generic,
3257                 0x00000000);
3258    /* XXX : not implemented */
3259    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3260                 SPR_NOACCESS, SPR_NOACCESS,
3261                 &spr_read_generic, &spr_write_generic,
3262                 0x00000000);
3263    /* Memory management */
3264#if !defined(CONFIG_USER_ONLY)
3265    env->nb_tlb = 64;
3266    env->nb_ways = 1;
3267    env->id_tlbs = 0;
3268    env->tlb_type = TLB_EMB;
3269#endif
3270    init_excp_BookE(env);
3271    env->dcache_line_size = 32;
3272    env->icache_line_size = 32;
3273    /* XXX: TODO: allocate internal IRQ controller */
3274
3275    SET_FIT_PERIOD(12, 16, 20, 24);
3276    SET_WDT_PERIOD(20, 24, 28, 32);
3277}
3278
3279POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3280{
3281    DeviceClass *dc = DEVICE_CLASS(oc);
3282    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3283
3284    dc->desc = "PowerPC 440 GP";
3285    pcc->init_proc = init_proc_440GP;
3286    pcc->check_pow = check_pow_nocheck;
3287    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3288                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3289                       PPC_CACHE | PPC_CACHE_ICBI |
3290                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3291                       PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3292                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3293                       PPC_440_SPEC;
3294    pcc->msr_mask = (1ull << MSR_POW) |
3295                    (1ull << MSR_CE) |
3296                    (1ull << MSR_EE) |
3297                    (1ull << MSR_PR) |
3298                    (1ull << MSR_FP) |
3299                    (1ull << MSR_ME) |
3300                    (1ull << MSR_FE0) |
3301                    (1ull << MSR_DWE) |
3302                    (1ull << MSR_DE) |
3303                    (1ull << MSR_FE1) |
3304                    (1ull << MSR_IR) |
3305                    (1ull << MSR_DR);
3306    pcc->mmu_model = POWERPC_MMU_BOOKE;
3307    pcc->excp_model = POWERPC_EXCP_BOOKE;
3308    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3309    pcc->bfd_mach = bfd_mach_ppc_403;
3310    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3311                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3312}
3313
3314static void init_proc_440x4(CPUPPCState *env)
3315{
3316    /* Time base */
3317    register_tbl(env);
3318    register_BookE_sprs(env, 0x000000000000FFFFULL);
3319    register_440_sprs(env);
3320    register_usprgh_sprs(env);
3321    /* Processor identification */
3322    spr_register(env, SPR_BOOKE_PIR, "PIR",
3323                 SPR_NOACCESS, SPR_NOACCESS,
3324                 &spr_read_generic, &spr_write_pir,
3325                 0x00000000);
3326    /* XXX : not implemented */
3327    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3328                 SPR_NOACCESS, SPR_NOACCESS,
3329                 &spr_read_generic, &spr_write_generic,
3330                 0x00000000);
3331    /* XXX : not implemented */
3332    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3333                 SPR_NOACCESS, SPR_NOACCESS,
3334                 &spr_read_generic, &spr_write_generic,
3335                 0x00000000);
3336    /* XXX : not implemented */
3337    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3338                 SPR_NOACCESS, SPR_NOACCESS,
3339                 &spr_read_generic, &spr_write_generic,
3340                 0x00000000);
3341    /* XXX : not implemented */
3342    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3343                 SPR_NOACCESS, SPR_NOACCESS,
3344                 &spr_read_generic, &spr_write_generic,
3345                 0x00000000);
3346    /* Memory management */
3347#if !defined(CONFIG_USER_ONLY)
3348    env->nb_tlb = 64;
3349    env->nb_ways = 1;
3350    env->id_tlbs = 0;
3351    env->tlb_type = TLB_EMB;
3352#endif
3353    init_excp_BookE(env);
3354    env->dcache_line_size = 32;
3355    env->icache_line_size = 32;
3356    /* XXX: TODO: allocate internal IRQ controller */
3357
3358    SET_FIT_PERIOD(12, 16, 20, 24);
3359    SET_WDT_PERIOD(20, 24, 28, 32);
3360}
3361
3362POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3363{
3364    DeviceClass *dc = DEVICE_CLASS(oc);
3365    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3366
3367    dc->desc = "PowerPC 440x4";
3368    pcc->init_proc = init_proc_440x4;
3369    pcc->check_pow = check_pow_nocheck;
3370    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3371                       PPC_DCR | PPC_WRTEE |
3372                       PPC_CACHE | PPC_CACHE_ICBI |
3373                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3374                       PPC_MEM_TLBSYNC | PPC_MFTB |
3375                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3376                       PPC_440_SPEC;
3377    pcc->msr_mask = (1ull << MSR_POW) |
3378                    (1ull << MSR_CE) |
3379                    (1ull << MSR_EE) |
3380                    (1ull << MSR_PR) |
3381                    (1ull << MSR_FP) |
3382                    (1ull << MSR_ME) |
3383                    (1ull << MSR_FE0) |
3384                    (1ull << MSR_DWE) |
3385                    (1ull << MSR_DE) |
3386                    (1ull << MSR_FE1) |
3387                    (1ull << MSR_IR) |
3388                    (1ull << MSR_DR);
3389    pcc->mmu_model = POWERPC_MMU_BOOKE;
3390    pcc->excp_model = POWERPC_EXCP_BOOKE;
3391    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3392    pcc->bfd_mach = bfd_mach_ppc_403;
3393    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3394                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3395}
3396
3397static void init_proc_440x5(CPUPPCState *env)
3398{
3399    /* Time base */
3400    register_tbl(env);
3401    register_BookE_sprs(env, 0x000000000000FFFFULL);
3402    register_440_sprs(env);
3403    register_usprgh_sprs(env);
3404    /* Processor identification */
3405    spr_register(env, SPR_BOOKE_PIR, "PIR",
3406                 SPR_NOACCESS, SPR_NOACCESS,
3407                 &spr_read_generic, &spr_write_pir,
3408                 0x00000000);
3409    /* XXX : not implemented */
3410    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3411                 SPR_NOACCESS, SPR_NOACCESS,
3412                 &spr_read_generic, &spr_write_generic,
3413                 0x00000000);
3414    /* XXX : not implemented */
3415    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3416                 SPR_NOACCESS, SPR_NOACCESS,
3417                 &spr_read_generic, &spr_write_generic,
3418                 0x00000000);
3419    /* XXX : not implemented */
3420    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3421                 SPR_NOACCESS, SPR_NOACCESS,
3422                 &spr_read_generic, &spr_write_generic,
3423                 0x00000000);
3424    /* XXX : not implemented */
3425    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3426                 SPR_NOACCESS, SPR_NOACCESS,
3427                 &spr_read_generic, &spr_write_generic,
3428                 0x00000000);
3429    /* XXX : not implemented */
3430    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3431                 SPR_NOACCESS, SPR_NOACCESS,
3432                 &spr_read_generic, &spr_write_generic,
3433                 0x00000000);
3434    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3435                 SPR_NOACCESS, SPR_NOACCESS,
3436                 &spr_read_generic, &spr_write_generic,
3437                 0x00000000);
3438    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3439                 SPR_NOACCESS, SPR_NOACCESS,
3440                 &spr_read_generic, &spr_write_generic,
3441                 0x00000000);
3442    /* XXX : not implemented */
3443    spr_register(env, SPR_440_CCR1, "CCR1",
3444                 SPR_NOACCESS, SPR_NOACCESS,
3445                 &spr_read_generic, &spr_write_generic,
3446                 0x00000000);
3447    /* Memory management */
3448#if !defined(CONFIG_USER_ONLY)
3449    env->nb_tlb = 64;
3450    env->nb_ways = 1;
3451    env->id_tlbs = 0;
3452    env->tlb_type = TLB_EMB;
3453#endif
3454    init_excp_BookE(env);
3455    env->dcache_line_size = 32;
3456    env->icache_line_size = 32;
3457    ppc40x_irq_init(env_archcpu(env));
3458
3459    SET_FIT_PERIOD(12, 16, 20, 24);
3460    SET_WDT_PERIOD(20, 24, 28, 32);
3461}
3462
3463POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3464{
3465    DeviceClass *dc = DEVICE_CLASS(oc);
3466    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3467
3468    dc->desc = "PowerPC 440x5";
3469    pcc->init_proc = init_proc_440x5;
3470    pcc->check_pow = check_pow_nocheck;
3471    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3472                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3473                       PPC_CACHE | PPC_CACHE_ICBI |
3474                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3475                       PPC_MEM_TLBSYNC | PPC_MFTB |
3476                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3477                       PPC_440_SPEC;
3478    pcc->msr_mask = (1ull << MSR_POW) |
3479                    (1ull << MSR_CE) |
3480                    (1ull << MSR_EE) |
3481                    (1ull << MSR_PR) |
3482                    (1ull << MSR_FP) |
3483                    (1ull << MSR_ME) |
3484                    (1ull << MSR_FE0) |
3485                    (1ull << MSR_DWE) |
3486                    (1ull << MSR_DE) |
3487                    (1ull << MSR_FE1) |
3488                    (1ull << MSR_IR) |
3489                    (1ull << MSR_DR);
3490    pcc->mmu_model = POWERPC_MMU_BOOKE;
3491    pcc->excp_model = POWERPC_EXCP_BOOKE;
3492    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3493    pcc->bfd_mach = bfd_mach_ppc_403;
3494    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3495                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3496}
3497
3498POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
3499{
3500    DeviceClass *dc = DEVICE_CLASS(oc);
3501    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3502
3503    dc->desc = "PowerPC 440x5 with double precision FPU";
3504    pcc->init_proc = init_proc_440x5;
3505    pcc->check_pow = check_pow_nocheck;
3506    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3507                       PPC_FLOAT | PPC_FLOAT_FSQRT |
3508                       PPC_FLOAT_STFIWX |
3509                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3510                       PPC_CACHE | PPC_CACHE_ICBI |
3511                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3512                       PPC_MEM_TLBSYNC | PPC_MFTB |
3513                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3514                       PPC_440_SPEC;
3515    pcc->insns_flags2 = PPC2_FP_CVT_S64;
3516    pcc->msr_mask = (1ull << MSR_POW) |
3517                    (1ull << MSR_CE) |
3518                    (1ull << MSR_EE) |
3519                    (1ull << MSR_PR) |
3520                    (1ull << MSR_FP) |
3521                    (1ull << MSR_ME) |
3522                    (1ull << MSR_FE0) |
3523                    (1ull << MSR_DWE) |
3524                    (1ull << MSR_DE) |
3525                    (1ull << MSR_FE1) |
3526                    (1ull << MSR_IR) |
3527                    (1ull << MSR_DR);
3528    pcc->mmu_model = POWERPC_MMU_BOOKE;
3529    pcc->excp_model = POWERPC_EXCP_BOOKE;
3530    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3531    pcc->bfd_mach = bfd_mach_ppc_403;
3532    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3533                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3534}
3535
3536static void init_proc_MPC5xx(CPUPPCState *env)
3537{
3538    /* Time base */
3539    register_tbl(env);
3540    register_5xx_8xx_sprs(env);
3541    register_5xx_sprs(env);
3542    init_excp_MPC5xx(env);
3543    env->dcache_line_size = 32;
3544    env->icache_line_size = 32;
3545    /* XXX: TODO: allocate internal IRQ controller */
3546}
3547
3548POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3549{
3550    DeviceClass *dc = DEVICE_CLASS(oc);
3551    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3552
3553    dc->desc = "Freescale 5xx cores (aka RCPU)";
3554    pcc->init_proc = init_proc_MPC5xx;
3555    pcc->check_pow = check_pow_none;
3556    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3557                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
3558                       PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
3559                       PPC_MFTB;
3560    pcc->msr_mask = (1ull << MSR_ILE) |
3561                    (1ull << MSR_EE) |
3562                    (1ull << MSR_PR) |
3563                    (1ull << MSR_FP) |
3564                    (1ull << MSR_ME) |
3565                    (1ull << MSR_FE0) |
3566                    (1ull << MSR_SE) |
3567                    (1ull << MSR_DE) |
3568                    (1ull << MSR_FE1) |
3569                    (1ull << MSR_EP) |
3570                    (1ull << MSR_RI) |
3571                    (1ull << MSR_LE);
3572    pcc->mmu_model = POWERPC_MMU_REAL;
3573    pcc->excp_model = POWERPC_EXCP_603;
3574    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3575    pcc->bfd_mach = bfd_mach_ppc_505;
3576    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3577                 POWERPC_FLAG_BUS_CLK;
3578}
3579
3580static void init_proc_MPC8xx(CPUPPCState *env)
3581{
3582    /* Time base */
3583    register_tbl(env);
3584    register_5xx_8xx_sprs(env);
3585    register_8xx_sprs(env);
3586    init_excp_MPC8xx(env);
3587    env->dcache_line_size = 32;
3588    env->icache_line_size = 32;
3589    /* XXX: TODO: allocate internal IRQ controller */
3590}
3591
3592POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
3593{
3594    DeviceClass *dc = DEVICE_CLASS(oc);
3595    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3596
3597    dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
3598    pcc->init_proc = init_proc_MPC8xx;
3599    pcc->check_pow = check_pow_none;
3600    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING  |
3601                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
3602                       PPC_CACHE_ICBI | PPC_MFTB;
3603    pcc->msr_mask = (1ull << MSR_ILE) |
3604                    (1ull << MSR_EE) |
3605                    (1ull << MSR_PR) |
3606                    (1ull << MSR_FP) |
3607                    (1ull << MSR_ME) |
3608                    (1ull << MSR_SE) |
3609                    (1ull << MSR_DE) |
3610                    (1ull << MSR_EP) |
3611                    (1ull << MSR_IR) |
3612                    (1ull << MSR_DR) |
3613                    (1ull << MSR_RI) |
3614                    (1ull << MSR_LE);
3615    pcc->mmu_model = POWERPC_MMU_MPC8xx;
3616    pcc->excp_model = POWERPC_EXCP_603;
3617    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3618    pcc->bfd_mach = bfd_mach_ppc_860;
3619    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3620                 POWERPC_FLAG_BUS_CLK;
3621}
3622
3623/* Freescale 82xx cores (aka PowerQUICC-II)                                  */
3624
3625static void init_proc_G2(CPUPPCState *env)
3626{
3627    register_ne_601_sprs(env);
3628    register_sdr1_sprs(env);
3629    register_G2_755_sprs(env);
3630    register_G2_sprs(env);
3631    /* Time base */
3632    register_tbl(env);
3633    /* External access control */
3634    /* XXX : not implemented */
3635    spr_register(env, SPR_EAR, "EAR",
3636                 SPR_NOACCESS, SPR_NOACCESS,
3637                 &spr_read_generic, &spr_write_generic,
3638                 0x00000000);
3639    /* Hardware implementation register */
3640    /* XXX : not implemented */
3641    spr_register(env, SPR_HID0, "HID0",
3642                 SPR_NOACCESS, SPR_NOACCESS,
3643                 &spr_read_generic, &spr_write_generic,
3644                 0x00000000);
3645    /* XXX : not implemented */
3646    spr_register(env, SPR_HID1, "HID1",
3647                 SPR_NOACCESS, SPR_NOACCESS,
3648                 &spr_read_generic, &spr_write_generic,
3649                 0x00000000);
3650    /* XXX : not implemented */
3651    spr_register(env, SPR_HID2, "HID2",
3652                 SPR_NOACCESS, SPR_NOACCESS,
3653                 &spr_read_generic, &spr_write_generic,
3654                 0x00000000);
3655    /* Memory management */
3656    register_low_BATs(env);
3657    register_high_BATs(env);
3658    register_6xx_7xx_soft_tlb(env, 64, 2);
3659    init_excp_G2(env);
3660    env->dcache_line_size = 32;
3661    env->icache_line_size = 32;
3662    /* Allocate hardware IRQ controller */
3663    ppc6xx_irq_init(env_archcpu(env));
3664}
3665
3666POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
3667{
3668    DeviceClass *dc = DEVICE_CLASS(oc);
3669    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3670
3671    dc->desc = "PowerPC G2";
3672    pcc->init_proc = init_proc_G2;
3673    pcc->check_pow = check_pow_hid0;
3674    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3675                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3676                       PPC_FLOAT_STFIWX |
3677                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3678                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3679                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3680                       PPC_SEGMENT | PPC_EXTERN;
3681    pcc->msr_mask = (1ull << MSR_POW) |
3682                    (1ull << MSR_TGPR) |
3683                    (1ull << MSR_EE) |
3684                    (1ull << MSR_PR) |
3685                    (1ull << MSR_FP) |
3686                    (1ull << MSR_ME) |
3687                    (1ull << MSR_FE0) |
3688                    (1ull << MSR_SE) |
3689                    (1ull << MSR_DE) |
3690                    (1ull << MSR_FE1) |
3691                    (1ull << MSR_AL) |
3692                    (1ull << MSR_EP) |
3693                    (1ull << MSR_IR) |
3694                    (1ull << MSR_DR) |
3695                    (1ull << MSR_RI);
3696    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3697    pcc->excp_model = POWERPC_EXCP_G2;
3698    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3699    pcc->bfd_mach = bfd_mach_ppc_ec603e;
3700    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3701                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3702}
3703
3704static void init_proc_G2LE(CPUPPCState *env)
3705{
3706    register_ne_601_sprs(env);
3707    register_sdr1_sprs(env);
3708    register_G2_755_sprs(env);
3709    register_G2_sprs(env);
3710    /* Time base */
3711    register_tbl(env);
3712    /* External access control */
3713    /* XXX : not implemented */
3714    spr_register(env, SPR_EAR, "EAR",
3715                 SPR_NOACCESS, SPR_NOACCESS,
3716                 &spr_read_generic, &spr_write_generic,
3717                 0x00000000);
3718    /* Hardware implementation register */
3719    /* XXX : not implemented */
3720    spr_register(env, SPR_HID0, "HID0",
3721                 SPR_NOACCESS, SPR_NOACCESS,
3722                 &spr_read_generic, &spr_write_generic,
3723                 0x00000000);
3724    /* XXX : not implemented */
3725    spr_register(env, SPR_HID1, "HID1",
3726                 SPR_NOACCESS, SPR_NOACCESS,
3727                 &spr_read_generic, &spr_write_generic,
3728                 0x00000000);
3729    /* XXX : not implemented */
3730    spr_register(env, SPR_HID2, "HID2",
3731                 SPR_NOACCESS, SPR_NOACCESS,
3732                 &spr_read_generic, &spr_write_generic,
3733                 0x00000000);
3734
3735    /* Memory management */
3736    register_low_BATs(env);
3737    register_high_BATs(env);
3738    register_6xx_7xx_soft_tlb(env, 64, 2);
3739    init_excp_G2(env);
3740    env->dcache_line_size = 32;
3741    env->icache_line_size = 32;
3742    /* Allocate hardware IRQ controller */
3743    ppc6xx_irq_init(env_archcpu(env));
3744}
3745
3746POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
3747{
3748    DeviceClass *dc = DEVICE_CLASS(oc);
3749    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3750
3751    dc->desc = "PowerPC G2LE";
3752    pcc->init_proc = init_proc_G2LE;
3753    pcc->check_pow = check_pow_hid0;
3754    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3755                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3756                       PPC_FLOAT_STFIWX |
3757                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3758                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3759                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3760                       PPC_SEGMENT | PPC_EXTERN;
3761    pcc->msr_mask = (1ull << MSR_POW) |
3762                    (1ull << MSR_TGPR) |
3763                    (1ull << MSR_ILE) |
3764                    (1ull << MSR_EE) |
3765                    (1ull << MSR_PR) |
3766                    (1ull << MSR_FP) |
3767                    (1ull << MSR_ME) |
3768                    (1ull << MSR_FE0) |
3769                    (1ull << MSR_SE) |
3770                    (1ull << MSR_DE) |
3771                    (1ull << MSR_FE1) |
3772                    (1ull << MSR_AL) |
3773                    (1ull << MSR_EP) |
3774                    (1ull << MSR_IR) |
3775                    (1ull << MSR_DR) |
3776                    (1ull << MSR_RI) |
3777                    (1ull << MSR_LE);
3778    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3779    pcc->excp_model = POWERPC_EXCP_G2;
3780    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3781    pcc->bfd_mach = bfd_mach_ppc_ec603e;
3782    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3783                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3784}
3785
3786static void init_proc_e200(CPUPPCState *env)
3787{
3788    /* Time base */
3789    register_tbl(env);
3790    register_BookE_sprs(env, 0x000000070000FFFFULL);
3791    /* XXX : not implemented */
3792    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3793                 &spr_read_spefscr, &spr_write_spefscr,
3794                 &spr_read_spefscr, &spr_write_spefscr,
3795                 0x00000000);
3796    /* Memory management */
3797    register_BookE206_sprs(env, 0x0000005D, NULL, 0);
3798    /* XXX : not implemented */
3799    spr_register(env, SPR_HID0, "HID0",
3800                 SPR_NOACCESS, SPR_NOACCESS,
3801                 &spr_read_generic, &spr_write_generic,
3802                 0x00000000);
3803    /* XXX : not implemented */
3804    spr_register(env, SPR_HID1, "HID1",
3805                 SPR_NOACCESS, SPR_NOACCESS,
3806                 &spr_read_generic, &spr_write_generic,
3807                 0x00000000);
3808    /* XXX : not implemented */
3809    spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3810                 SPR_NOACCESS, SPR_NOACCESS,
3811                 &spr_read_generic, &spr_write_generic,
3812                 0x00000000);
3813    /* XXX : not implemented */
3814    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3815                 SPR_NOACCESS, SPR_NOACCESS,
3816                 &spr_read_generic, &spr_write_generic,
3817                 0x00000000);
3818    /* XXX : not implemented */
3819    spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3820                 SPR_NOACCESS, SPR_NOACCESS,
3821                 &spr_read_generic, &spr_write_generic,
3822                 0x00000000);
3823    /* XXX : not implemented */
3824    spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3825                 SPR_NOACCESS, SPR_NOACCESS,
3826                 &spr_read_generic, &spr_write_generic,
3827                 0x00000000);
3828    /* XXX : not implemented */
3829    spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3830                 SPR_NOACCESS, SPR_NOACCESS,
3831                 &spr_read_generic, &spr_write_generic,
3832                 0x00000000);
3833    /* XXX : not implemented */
3834    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3835                 &spr_read_generic, SPR_NOACCESS,
3836                 &spr_read_generic, SPR_NOACCESS,
3837                 0x00000000);
3838    /* XXX : not implemented */
3839    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3840                 SPR_NOACCESS, SPR_NOACCESS,
3841                 &spr_read_generic, &spr_write_generic,
3842                 0x00000000);
3843    /* XXX : not implemented */
3844    spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3845                 SPR_NOACCESS, SPR_NOACCESS,
3846                 &spr_read_generic, &spr_write_generic,
3847                 0x00000000);
3848    /* XXX : not implemented */
3849    spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3850                 SPR_NOACCESS, SPR_NOACCESS,
3851                 &spr_read_generic, &spr_write_generic,
3852                 0x00000000);
3853    /* XXX : not implemented */
3854    spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3855                 SPR_NOACCESS, SPR_NOACCESS,
3856                 &spr_read_generic, &spr_write_generic,
3857                 0x00000000);
3858    /* XXX : not implemented */
3859    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3860                 SPR_NOACCESS, SPR_NOACCESS,
3861                 &spr_read_generic, &spr_write_generic,
3862                 0x00000000);
3863    /* XXX : not implemented */
3864    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3865                 SPR_NOACCESS, SPR_NOACCESS,
3866                 &spr_read_generic, &spr_write_generic,
3867                 0x00000000);
3868    /* XXX : not implemented */
3869    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3870                 SPR_NOACCESS, SPR_NOACCESS,
3871                 &spr_read_generic, &spr_write_generic,
3872                 0x00000000); /* TOFIX */
3873    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3874                 SPR_NOACCESS, SPR_NOACCESS,
3875                 &spr_read_generic, &spr_write_generic,
3876                 0x00000000);
3877    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3878                 SPR_NOACCESS, SPR_NOACCESS,
3879                 &spr_read_generic, &spr_write_generic,
3880                 0x00000000);
3881#if !defined(CONFIG_USER_ONLY)
3882    env->nb_tlb = 64;
3883    env->nb_ways = 1;
3884    env->id_tlbs = 0;
3885    env->tlb_type = TLB_EMB;
3886#endif
3887    init_excp_e200(env, 0xFFFF0000UL);
3888    env->dcache_line_size = 32;
3889    env->icache_line_size = 32;
3890    /* XXX: TODO: allocate internal IRQ controller */
3891}
3892
3893POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3894{
3895    DeviceClass *dc = DEVICE_CLASS(oc);
3896    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3897
3898    dc->desc = "e200 core";
3899    pcc->init_proc = init_proc_e200;
3900    pcc->check_pow = check_pow_hid0;
3901    /*
3902     * XXX: unimplemented instructions:
3903     * dcblc
3904     * dcbtlst
3905     * dcbtstls
3906     * icblc
3907     * icbtls
3908     * tlbivax
3909     * all SPE multiply-accumulate instructions
3910     */
3911    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3912                       PPC_SPE | PPC_SPE_SINGLE |
3913                       PPC_WRTEE | PPC_RFDI |
3914                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3915                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3916                       PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3917                       PPC_BOOKE;
3918    pcc->msr_mask = (1ull << MSR_UCLE) |
3919                    (1ull << MSR_SPE) |
3920                    (1ull << MSR_POW) |
3921                    (1ull << MSR_CE) |
3922                    (1ull << MSR_EE) |
3923                    (1ull << MSR_PR) |
3924                    (1ull << MSR_FP) |
3925                    (1ull << MSR_ME) |
3926                    (1ull << MSR_FE0) |
3927                    (1ull << MSR_DWE) |
3928                    (1ull << MSR_DE) |
3929                    (1ull << MSR_FE1) |
3930                    (1ull << MSR_IR) |
3931                    (1ull << MSR_DR);
3932    pcc->mmu_model = POWERPC_MMU_BOOKE206;
3933    pcc->excp_model = POWERPC_EXCP_BOOKE;
3934    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3935    pcc->bfd_mach = bfd_mach_ppc_860;
3936    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3937                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3938                 POWERPC_FLAG_BUS_CLK;
3939}
3940
3941static void init_proc_e300(CPUPPCState *env)
3942{
3943    register_ne_601_sprs(env);
3944    register_sdr1_sprs(env);
3945    register_603_sprs(env);
3946    /* Time base */
3947    register_tbl(env);
3948    /* hardware implementation registers */
3949    /* XXX : not implemented */
3950    spr_register(env, SPR_HID0, "HID0",
3951                 SPR_NOACCESS, SPR_NOACCESS,
3952                 &spr_read_generic, &spr_write_generic,
3953                 0x00000000);
3954    /* XXX : not implemented */
3955    spr_register(env, SPR_HID1, "HID1",
3956                 SPR_NOACCESS, SPR_NOACCESS,
3957                 &spr_read_generic, &spr_write_generic,
3958                 0x00000000);
3959    /* XXX : not implemented */
3960    spr_register(env, SPR_HID2, "HID2",
3961                 SPR_NOACCESS, SPR_NOACCESS,
3962                 &spr_read_generic, &spr_write_generic,
3963                 0x00000000);
3964    /* Breakpoints */
3965    /* XXX : not implemented */
3966    spr_register(env, SPR_DABR, "DABR",
3967                 SPR_NOACCESS, SPR_NOACCESS,
3968                 &spr_read_generic, &spr_write_generic,
3969                 0x00000000);
3970    /* XXX : not implemented */
3971    spr_register(env, SPR_DABR2, "DABR2",
3972                 SPR_NOACCESS, SPR_NOACCESS,
3973                 &spr_read_generic, &spr_write_generic,
3974                 0x00000000);
3975    /* XXX : not implemented */
3976    spr_register(env, SPR_IABR2, "IABR2",
3977                 SPR_NOACCESS, SPR_NOACCESS,
3978                 &spr_read_generic, &spr_write_generic,
3979                 0x00000000);
3980    /* XXX : not implemented */
3981    spr_register(env, SPR_IBCR, "IBCR",
3982                 SPR_NOACCESS, SPR_NOACCESS,
3983                 &spr_read_generic, &spr_write_generic,
3984                 0x00000000);
3985    /* XXX : not implemented */
3986    spr_register(env, SPR_DBCR, "DBCR",
3987                 SPR_NOACCESS, SPR_NOACCESS,
3988                 &spr_read_generic, &spr_write_generic,
3989                 0x00000000);
3990    /* Memory management */
3991    register_low_BATs(env);
3992    register_high_BATs(env);
3993    register_6xx_7xx_soft_tlb(env, 64, 2);
3994    init_excp_603(env);
3995    env->dcache_line_size = 32;
3996    env->icache_line_size = 32;
3997    /* Allocate hardware IRQ controller */
3998    ppc6xx_irq_init(env_archcpu(env));
3999}
4000

4001POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4002{
4003    DeviceClass *dc = DEVICE_CLASS(oc);
4004    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4005
4006    dc->desc = "e300 core";
4007    pcc->init_proc = init_proc_e300;
4008    pcc->check_pow = check_pow_hid0;
4009    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4010                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4011                       PPC_FLOAT_STFIWX |
4012                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4013                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4014                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4015                       PPC_SEGMENT | PPC_EXTERN;
4016    pcc->msr_mask = (1ull << MSR_POW) |
4017                    (1ull << MSR_TGPR) |
4018                    (1ull << MSR_ILE) |
4019                    (1ull << MSR_EE) |
4020                    (1ull << MSR_PR) |
4021                    (1ull << MSR_FP) |
4022                    (1ull << MSR_ME) |
4023                    (1ull << MSR_FE0) |
4024                    (1ull << MSR_SE) |
4025                    (1ull << MSR_DE) |
4026                    (1ull << MSR_FE1) |
4027                    (1ull << MSR_AL) |
4028                    (1ull << MSR_EP) |
4029                    (1ull << MSR_IR) |
4030                    (1ull << MSR_DR) |
4031                    (1ull << MSR_RI) |
4032                    (1ull << MSR_LE);
4033    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4034    pcc->excp_model = POWERPC_EXCP_603;
4035    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4036    pcc->bfd_mach = bfd_mach_ppc_603;
4037    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4038                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4039}
4040
4041enum fsl_e500_version {
4042    fsl_e500v1,
4043    fsl_e500v2,
4044    fsl_e500mc,
4045    fsl_e5500,
4046    fsl_e6500,
4047};
4048
4049static void init_proc_e500(CPUPPCState *env, int version)
4050{
4051    uint32_t tlbncfg[2];
4052    uint64_t ivor_mask;
4053    uint64_t ivpr_mask = 0xFFFF0000ULL;
4054    uint32_t l1cfg0 = 0x3800  /* 8 ways */
4055                    | 0x0020; /* 32 kb */
4056    uint32_t l1cfg1 = 0x3800  /* 8 ways */
4057                    | 0x0020; /* 32 kb */
4058    uint32_t mmucfg = 0;
4059#if !defined(CONFIG_USER_ONLY)
4060    int i;
4061#endif
4062
4063    /* Time base */
4064    register_tbl(env);
4065    /*
4066     * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4067     *     complain when accessing them.
4068     * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
4069     */
4070    switch (version) {
4071    case fsl_e500v1:
4072    case fsl_e500v2:
4073    default:
4074        ivor_mask = 0x0000000F0000FFFFULL;
4075        break;
4076    case fsl_e500mc:
4077    case fsl_e5500:
4078        ivor_mask = 0x000003FE0000FFFFULL;
4079        break;
4080    case fsl_e6500:
4081        ivor_mask = 0x000003FF0000FFFFULL;
4082        break;
4083    }
4084    register_BookE_sprs(env, ivor_mask);
4085    register_usprg3_sprs(env);
4086    /* Processor identification */
4087    spr_register(env, SPR_BOOKE_PIR, "PIR",
4088                 SPR_NOACCESS, SPR_NOACCESS,
4089                 &spr_read_generic, &spr_write_pir,
4090                 0x00000000);
4091    /* XXX : not implemented */
4092    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4093                 &spr_read_spefscr, &spr_write_spefscr,
4094                 &spr_read_spefscr, &spr_write_spefscr,
4095                 0x00000000);
4096#if !defined(CONFIG_USER_ONLY)
4097    /* Memory management */
4098    env->nb_pids = 3;
4099    env->nb_ways = 2;
4100    env->id_tlbs = 0;
4101    switch (version) {
4102    case fsl_e500v1:
4103        tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
4104        tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4105        break;
4106    case fsl_e500v2:
4107        tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
4108        tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4109        break;
4110    case fsl_e500mc:
4111    case fsl_e5500:
4112        tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
4113        tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4114        break;
4115    case fsl_e6500:
4116        mmucfg = 0x6510B45;
4117        env->nb_pids = 1;
4118        tlbncfg[0] = 0x08052400;
4119        tlbncfg[1] = 0x40028040;
4120        break;
4121    default:
4122        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4123                  env->spr[SPR_PVR]);
4124    }
4125#endif
4126    /* Cache sizes */
4127    switch (version) {
4128    case fsl_e500v1:
4129    case fsl_e500v2:
4130        env->dcache_line_size = 32;
4131        env->icache_line_size = 32;
4132        break;
4133    case fsl_e500mc:
4134    case fsl_e5500:
4135        env->dcache_line_size = 64;
4136        env->icache_line_size = 64;
4137        l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4138        l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4139        break;
4140    case fsl_e6500:
4141        env->dcache_line_size = 32;
4142        env->icache_line_size = 32;
4143        l1cfg0 |= 0x0F83820;
4144        l1cfg1 |= 0x0B83820;
4145        break;
4146    default:
4147        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4148                  env->spr[SPR_PVR]);
4149    }
4150    register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
4151    /* XXX : not implemented */
4152    spr_register(env, SPR_HID0, "HID0",
4153                 SPR_NOACCESS, SPR_NOACCESS,
4154                 &spr_read_generic, &spr_write_generic,
4155                 0x00000000);
4156    /* XXX : not implemented */
4157    spr_register(env, SPR_HID1, "HID1",
4158                 SPR_NOACCESS, SPR_NOACCESS,
4159                 &spr_read_generic, &spr_write_generic,
4160                 0x00000000);
4161    /* XXX : not implemented */
4162    spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4163                 SPR_NOACCESS, SPR_NOACCESS,
4164                 &spr_read_generic, &spr_write_generic,
4165                 0x00000000);
4166    /* XXX : not implemented */
4167    spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4168                 SPR_NOACCESS, SPR_NOACCESS,
4169                 &spr_read_generic, &spr_write_generic,
4170                 0x00000000);
4171    /* XXX : not implemented */
4172    spr_register(env, SPR_Exxx_MCAR, "MCAR",
4173                 SPR_NOACCESS, SPR_NOACCESS,
4174                 &spr_read_generic, &spr_write_generic,
4175                 0x00000000);
4176    /* XXX : not implemented */
4177    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4178                 SPR_NOACCESS, SPR_NOACCESS,
4179                 &spr_read_generic, &spr_write_generic,
4180                 0x00000000);
4181    /* XXX : not implemented */
4182    spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4183                 SPR_NOACCESS, SPR_NOACCESS,
4184                 &spr_read_generic, &spr_write_generic,
4185                 0x00000000);
4186    /* XXX : not implemented */
4187    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4188                 SPR_NOACCESS, SPR_NOACCESS,
4189                 &spr_read_generic, &spr_write_generic,
4190                 0x00000000);
4191    /* XXX : not implemented */
4192    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4193                 &spr_read_generic, SPR_NOACCESS,
4194                 &spr_read_generic, SPR_NOACCESS,
4195                 l1cfg0);
4196    spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4197                 &spr_read_generic, SPR_NOACCESS,
4198                 &spr_read_generic, SPR_NOACCESS,
4199                 l1cfg1);
4200    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4201                 SPR_NOACCESS, SPR_NOACCESS,
4202                 &spr_read_generic, &spr_write_e500_l1csr0,
4203                 0x00000000);
4204    spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4205                 SPR_NOACCESS, SPR_NOACCESS,
4206                 &spr_read_generic, &spr_write_e500_l1csr1,
4207                 0x00000000);
4208    if (version != fsl_e500v1 && version != fsl_e500v2) {
4209        spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
4210                     SPR_NOACCESS, SPR_NOACCESS,
4211                     &spr_read_generic, &spr_write_e500_l2csr0,
4212                     0x00000000);
4213    }
4214    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4215                 SPR_NOACCESS, SPR_NOACCESS,
4216                 &spr_read_generic, &spr_write_generic,
4217                 0x00000000);
4218    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4219                 SPR_NOACCESS, SPR_NOACCESS,
4220                 &spr_read_generic, &spr_write_generic,
4221                 0x00000000);
4222    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4223                 SPR_NOACCESS, SPR_NOACCESS,
4224                 &spr_read_generic, &spr_write_booke206_mmucsr0,
4225                 0x00000000);
4226    spr_register(env, SPR_BOOKE_EPR, "EPR",
4227                 SPR_NOACCESS, SPR_NOACCESS,
4228                 &spr_read_generic, SPR_NOACCESS,
4229                 0x00000000);
4230    /* XXX better abstract into Emb.xxx features */
4231    if ((version == fsl_e5500) || (version == fsl_e6500)) {
4232        spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4233                     SPR_NOACCESS, SPR_NOACCESS,
4234                     &spr_read_generic, &spr_write_generic,
4235                     0x00000000);
4236        spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4237                     SPR_NOACCESS, SPR_NOACCESS,
4238                     &spr_read_mas73, &spr_write_mas73,
4239                     0x00000000);
4240        ivpr_mask = (target_ulong)~0xFFFFULL;
4241    }
4242
4243    if (version == fsl_e6500) {
4244        /* Thread identification */
4245        spr_register(env, SPR_TIR, "TIR",
4246                     SPR_NOACCESS, SPR_NOACCESS,
4247                     &spr_read_generic, SPR_NOACCESS,
4248                     0x00000000);
4249        spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
4250                     SPR_NOACCESS, SPR_NOACCESS,
4251                     &spr_read_generic, SPR_NOACCESS,
4252                     0x00000004);
4253        spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
4254                     SPR_NOACCESS, SPR_NOACCESS,
4255                     &spr_read_generic, SPR_NOACCESS,
4256                     0x7FFFFFFC);
4257    }
4258
4259#if !defined(CONFIG_USER_ONLY)
4260    env->nb_tlb = 0;
4261    env->tlb_type = TLB_MAS;
4262    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4263        env->nb_tlb += booke206_tlb_size(env, i);
4264    }
4265#endif
4266
4267    init_excp_e200(env, ivpr_mask);
4268    /* Allocate hardware IRQ controller */
4269    ppce500_irq_init(env_archcpu(env));
4270}
4271
4272static void init_proc_e500v1(CPUPPCState *env)
4273{
4274    init_proc_e500(env, fsl_e500v1);
4275}
4276
4277POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4278{
4279    DeviceClass *dc = DEVICE_CLASS(oc);
4280    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4281
4282    dc->desc = "e500v1 core";
4283    pcc->init_proc = init_proc_e500v1;
4284    pcc->check_pow = check_pow_hid0;
4285    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4286                       PPC_SPE | PPC_SPE_SINGLE |
4287                       PPC_WRTEE | PPC_RFDI |
4288                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4289                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4290                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4291    pcc->insns_flags2 = PPC2_BOOKE206;
4292    pcc->msr_mask = (1ull << MSR_UCLE) |
4293                    (1ull << MSR_SPE) |
4294                    (1ull << MSR_POW) |
4295                    (1ull << MSR_CE) |
4296                    (1ull << MSR_EE) |
4297                    (1ull << MSR_PR) |
4298                    (1ull << MSR_FP) |
4299                    (1ull << MSR_ME) |
4300                    (1ull << MSR_FE0) |
4301                    (1ull << MSR_DWE) |
4302                    (1ull << MSR_DE) |
4303                    (1ull << MSR_FE1) |
4304                    (1ull << MSR_IR) |
4305                    (1ull << MSR_DR);
4306    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4307    pcc->excp_model = POWERPC_EXCP_BOOKE;
4308    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4309    pcc->bfd_mach = bfd_mach_ppc_860;
4310    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4311                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4312                 POWERPC_FLAG_BUS_CLK;
4313}
4314
4315static void init_proc_e500v2(CPUPPCState *env)
4316{
4317    init_proc_e500(env, fsl_e500v2);
4318}
4319
4320POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4321{
4322    DeviceClass *dc = DEVICE_CLASS(oc);
4323    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4324
4325    dc->desc = "e500v2 core";
4326    pcc->init_proc = init_proc_e500v2;
4327    pcc->check_pow = check_pow_hid0;
4328    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4329                       PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4330                       PPC_WRTEE | PPC_RFDI |
4331                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4332                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4333                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4334    pcc->insns_flags2 = PPC2_BOOKE206;
4335    pcc->msr_mask = (1ull << MSR_UCLE) |
4336                    (1ull << MSR_SPE) |
4337                    (1ull << MSR_POW) |
4338                    (1ull << MSR_CE) |
4339                    (1ull << MSR_EE) |
4340                    (1ull << MSR_PR) |
4341                    (1ull << MSR_FP) |
4342                    (1ull << MSR_ME) |
4343                    (1ull << MSR_FE0) |
4344                    (1ull << MSR_DWE) |
4345                    (1ull << MSR_DE) |
4346                    (1ull << MSR_FE1) |
4347                    (1ull << MSR_IR) |
4348                    (1ull << MSR_DR);
4349    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4350    pcc->excp_model = POWERPC_EXCP_BOOKE;
4351    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4352    pcc->bfd_mach = bfd_mach_ppc_860;
4353    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4354                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4355                 POWERPC_FLAG_BUS_CLK;
4356}
4357
4358static void init_proc_e500mc(CPUPPCState *env)
4359{
4360    init_proc_e500(env, fsl_e500mc);
4361}
4362
4363POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4364{
4365    DeviceClass *dc = DEVICE_CLASS(oc);
4366    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4367
4368    dc->desc = "e500mc core";
4369    pcc->init_proc = init_proc_e500mc;
4370    pcc->check_pow = check_pow_none;
4371    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4372                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4373                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4374                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4375                       PPC_FLOAT | PPC_FLOAT_FRES |
4376                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4377                       PPC_FLOAT_STFIWX | PPC_WAIT |
4378                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4379    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4380    pcc->msr_mask = (1ull << MSR_GS) |
4381                    (1ull << MSR_UCLE) |
4382                    (1ull << MSR_CE) |
4383                    (1ull << MSR_EE) |
4384                    (1ull << MSR_PR) |
4385                    (1ull << MSR_FP) |
4386                    (1ull << MSR_ME) |
4387                    (1ull << MSR_FE0) |
4388                    (1ull << MSR_DE) |
4389                    (1ull << MSR_FE1) |
4390                    (1ull << MSR_IR) |
4391                    (1ull << MSR_DR) |
4392                    (1ull << MSR_PX) |
4393                    (1ull << MSR_RI);
4394    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4395    pcc->excp_model = POWERPC_EXCP_BOOKE;
4396    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4397    /* FIXME: figure out the correct flag for e500mc */
4398    pcc->bfd_mach = bfd_mach_ppc_e500;
4399    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4400                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4401}
4402
4403#ifdef TARGET_PPC64
4404static void init_proc_e5500(CPUPPCState *env)
4405{
4406    init_proc_e500(env, fsl_e5500);
4407}
4408
4409POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4410{
4411    DeviceClass *dc = DEVICE_CLASS(oc);
4412    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4413
4414    dc->desc = "e5500 core";
4415    pcc->init_proc = init_proc_e5500;
4416    pcc->check_pow = check_pow_none;
4417    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4418                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4419                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4420                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4421                       PPC_FLOAT | PPC_FLOAT_FRES |
4422                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4423                       PPC_FLOAT_STFIWX | PPC_WAIT |
4424                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4425                       PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4426    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
4427                        PPC2_FP_CVT_S64;
4428    pcc->msr_mask = (1ull << MSR_CM) |
4429                    (1ull << MSR_GS) |
4430                    (1ull << MSR_UCLE) |
4431                    (1ull << MSR_CE) |
4432                    (1ull << MSR_EE) |
4433                    (1ull << MSR_PR) |
4434                    (1ull << MSR_FP) |
4435                    (1ull << MSR_ME) |
4436                    (1ull << MSR_FE0) |
4437                    (1ull << MSR_DE) |
4438                    (1ull << MSR_FE1) |
4439                    (1ull << MSR_IR) |
4440                    (1ull << MSR_DR) |
4441                    (1ull << MSR_PX) |
4442                    (1ull << MSR_RI);
4443    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4444    pcc->excp_model = POWERPC_EXCP_BOOKE;
4445    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4446    /* FIXME: figure out the correct flag for e5500 */
4447    pcc->bfd_mach = bfd_mach_ppc_e500;
4448    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4449                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4450}
4451
4452static void init_proc_e6500(CPUPPCState *env)
4453{
4454    init_proc_e500(env, fsl_e6500);
4455}
4456
4457POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
4458{
4459    DeviceClass *dc = DEVICE_CLASS(oc);
4460    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4461
4462    dc->desc = "e6500 core";
4463    pcc->init_proc = init_proc_e6500;
4464    pcc->check_pow = check_pow_none;
4465    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4466                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4467                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4468                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4469                       PPC_FLOAT | PPC_FLOAT_FRES |
4470                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4471                       PPC_FLOAT_STFIWX | PPC_WAIT |
4472                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4473                       PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
4474    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
4475                        PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
4476    pcc->msr_mask = (1ull << MSR_CM) |
4477                    (1ull << MSR_GS) |
4478                    (1ull << MSR_UCLE) |
4479                    (1ull << MSR_CE) |
4480                    (1ull << MSR_EE) |
4481                    (1ull << MSR_PR) |
4482                    (1ull << MSR_FP) |
4483                    (1ull << MSR_ME) |
4484                    (1ull << MSR_FE0) |
4485                    (1ull << MSR_DE) |
4486                    (1ull << MSR_FE1) |
4487                    (1ull << MSR_IS) |
4488                    (1ull << MSR_DS) |
4489                    (1ull << MSR_PX) |
4490                    (1ull << MSR_RI) |
4491                    (1ull << MSR_VR);
4492    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4493    pcc->excp_model = POWERPC_EXCP_BOOKE;
4494    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4495    pcc->bfd_mach = bfd_mach_ppc_e500;
4496    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4497                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
4498}
4499
4500#endif
4501
4502/* Non-embedded PowerPC                                                      */
4503
4504#define POWERPC_MSRR_601     (0x0000000000001040ULL)
4505
4506static void init_proc_601(CPUPPCState *env)
4507{
4508    register_ne_601_sprs(env);
4509    register_sdr1_sprs(env);
4510    register_601_sprs(env);
4511    /* Hardware implementation registers */
4512    /* XXX : not implemented */
4513    spr_register(env, SPR_HID0, "HID0",
4514                 SPR_NOACCESS, SPR_NOACCESS,
4515                 &spr_read_generic, &spr_write_hid0_601,
4516                 0x80010080);
4517    /* XXX : not implemented */
4518    spr_register(env, SPR_HID1, "HID1",
4519                 SPR_NOACCESS, SPR_NOACCESS,
4520                 &spr_read_generic, &spr_write_generic,
4521                 0x00000000);
4522    /* XXX : not implemented */
4523    spr_register(env, SPR_601_HID2, "HID2",
4524                 SPR_NOACCESS, SPR_NOACCESS,
4525                 &spr_read_generic, &spr_write_generic,
4526                 0x00000000);
4527    /* XXX : not implemented */
4528    spr_register(env, SPR_601_HID5, "HID5",
4529                 SPR_NOACCESS, SPR_NOACCESS,
4530                 &spr_read_generic, &spr_write_generic,
4531                 0x00000000);
4532    /* Memory management */
4533    init_excp_601(env);
4534    /*
4535     * XXX: beware that dcache line size is 64
4536     *      but dcbz uses 32 bytes "sectors"
4537     * XXX: this breaks clcs instruction !
4538     */
4539    env->dcache_line_size = 32;
4540    env->icache_line_size = 64;
4541    /* Allocate hardware IRQ controller */
4542    ppc6xx_irq_init(env_archcpu(env));
4543}
4544
4545POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4546{
4547    DeviceClass *dc = DEVICE_CLASS(oc);
4548    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4549
4550    dc->desc = "PowerPC 601";
4551    pcc->init_proc = init_proc_601;
4552    pcc->check_pow = check_pow_none;
4553    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4554                       PPC_FLOAT |
4555                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4556                       PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4557                       PPC_SEGMENT | PPC_EXTERN;
4558    pcc->msr_mask = (1ull << MSR_EE) |
4559                    (1ull << MSR_PR) |
4560                    (1ull << MSR_FP) |
4561                    (1ull << MSR_ME) |
4562                    (1ull << MSR_FE0) |
4563                    (1ull << MSR_SE) |
4564                    (1ull << MSR_FE1) |
4565                    (1ull << MSR_EP) |
4566                    (1ull << MSR_IR) |
4567                    (1ull << MSR_DR);
4568    pcc->mmu_model = POWERPC_MMU_601;
4569    pcc->excp_model = POWERPC_EXCP_601;
4570    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4571    pcc->bfd_mach = bfd_mach_ppc_601;
4572    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4573}
4574
4575#define POWERPC_MSRR_601v    (0x0000000000001040ULL)
4576
4577static void init_proc_601v(CPUPPCState *env)
4578{
4579    init_proc_601(env);
4580    /* XXX : not implemented */
4581    spr_register(env, SPR_601_HID15, "HID15",
4582                 SPR_NOACCESS, SPR_NOACCESS,
4583                 &spr_read_generic, &spr_write_generic,
4584                 0x00000000);
4585}
4586
4587POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4588{
4589    DeviceClass *dc = DEVICE_CLASS(oc);
4590    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4591
4592    dc->desc = "PowerPC 601v";
4593    pcc->init_proc = init_proc_601v;
4594    pcc->check_pow = check_pow_none;
4595    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4596                       PPC_FLOAT |
4597                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4598                       PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4599                       PPC_SEGMENT | PPC_EXTERN;
4600    pcc->msr_mask = (1ull << MSR_EE) |
4601                    (1ull << MSR_PR) |
4602                    (1ull << MSR_FP) |
4603                    (1ull << MSR_ME) |
4604                    (1ull << MSR_FE0) |
4605                    (1ull << MSR_SE) |
4606                    (1ull << MSR_FE1) |
4607                    (1ull << MSR_EP) |
4608                    (1ull << MSR_IR) |
4609                    (1ull << MSR_DR);
4610    pcc->mmu_model = POWERPC_MMU_601;
4611    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4612    pcc->bfd_mach = bfd_mach_ppc_601;
4613    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4614}
4615
4616static void init_proc_602(CPUPPCState *env)
4617{
4618    register_ne_601_sprs(env);
4619    register_sdr1_sprs(env);
4620    register_602_sprs(env);
4621    /* Time base */
4622    register_tbl(env);
4623    /* hardware implementation registers */
4624    /* XXX : not implemented */
4625    spr_register(env, SPR_HID0, "HID0",
4626                 SPR_NOACCESS, SPR_NOACCESS,
4627                 &spr_read_generic, &spr_write_generic,
4628                 0x00000000);
4629    /* XXX : not implemented */
4630    spr_register(env, SPR_HID1, "HID1",
4631                 SPR_NOACCESS, SPR_NOACCESS,
4632                 &spr_read_generic, &spr_write_generic,
4633                 0x00000000);
4634    /* Memory management */
4635    register_low_BATs(env);
4636    register_6xx_7xx_soft_tlb(env, 64, 2);
4637    init_excp_602(env);
4638    env->dcache_line_size = 32;
4639    env->icache_line_size = 32;
4640    /* Allocate hardware IRQ controller */
4641    ppc6xx_irq_init(env_archcpu(env));
4642}
4643
4644POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4645{
4646    DeviceClass *dc = DEVICE_CLASS(oc);
4647    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4648
4649    dc->desc = "PowerPC 602";
4650    pcc->init_proc = init_proc_602;
4651    pcc->check_pow = check_pow_hid0;
4652    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4653                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4654                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4655                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4656                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4657                       PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4658                       PPC_SEGMENT | PPC_602_SPEC;
4659    pcc->msr_mask = (1ull << MSR_VSX) |
4660                    (1ull << MSR_SA) |
4661                    (1ull << MSR_POW) |
4662                    (1ull << MSR_TGPR) |
4663                    (1ull << MSR_ILE) |
4664                    (1ull << MSR_EE) |
4665                    (1ull << MSR_PR) |
4666                    (1ull << MSR_FP) |
4667                    (1ull << MSR_ME) |
4668                    (1ull << MSR_FE0) |
4669                    (1ull << MSR_SE) |
4670                    (1ull << MSR_DE) |
4671                    (1ull << MSR_FE1) |
4672                    (1ull << MSR_EP) |
4673                    (1ull << MSR_IR) |
4674                    (1ull << MSR_DR) |
4675                    (1ull << MSR_RI) |
4676                    (1ull << MSR_LE);
4677    /* XXX: 602 MMU is quite specific. Should add a special case */
4678    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4679    pcc->excp_model = POWERPC_EXCP_602;
4680    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4681    pcc->bfd_mach = bfd_mach_ppc_602;
4682    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4683                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4684}
4685
4686static void init_proc_603(CPUPPCState *env)
4687{
4688    register_ne_601_sprs(env);
4689    register_sdr1_sprs(env);
4690    register_603_sprs(env);
4691    /* Time base */
4692    register_tbl(env);
4693    /* hardware implementation registers */
4694    /* XXX : not implemented */
4695    spr_register(env, SPR_HID0, "HID0",
4696                 SPR_NOACCESS, SPR_NOACCESS,
4697                 &spr_read_generic, &spr_write_generic,
4698                 0x00000000);
4699    /* XXX : not implemented */
4700    spr_register(env, SPR_HID1, "HID1",
4701                 SPR_NOACCESS, SPR_NOACCESS,
4702                 &spr_read_generic, &spr_write_generic,
4703                 0x00000000);
4704    /* Memory management */
4705    register_low_BATs(env);
4706    register_6xx_7xx_soft_tlb(env, 64, 2);
4707    init_excp_603(env);
4708    env->dcache_line_size = 32;
4709    env->icache_line_size = 32;
4710    /* Allocate hardware IRQ controller */
4711    ppc6xx_irq_init(env_archcpu(env));
4712}
4713
4714POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4715{
4716    DeviceClass *dc = DEVICE_CLASS(oc);
4717    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4718
4719    dc->desc = "PowerPC 603";
4720    pcc->init_proc = init_proc_603;
4721    pcc->check_pow = check_pow_hid0;
4722    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4723                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4724                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4725                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4726                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4727                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4728                       PPC_SEGMENT | PPC_EXTERN;
4729    pcc->msr_mask = (1ull << MSR_POW) |
4730                    (1ull << MSR_TGPR) |
4731                    (1ull << MSR_ILE) |
4732                    (1ull << MSR_EE) |
4733                    (1ull << MSR_PR) |
4734                    (1ull << MSR_FP) |
4735                    (1ull << MSR_ME) |
4736                    (1ull << MSR_FE0) |
4737                    (1ull << MSR_SE) |
4738                    (1ull << MSR_DE) |
4739                    (1ull << MSR_FE1) |
4740                    (1ull << MSR_EP) |
4741                    (1ull << MSR_IR) |
4742                    (1ull << MSR_DR) |
4743                    (1ull << MSR_RI) |
4744                    (1ull << MSR_LE);
4745    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4746    pcc->excp_model = POWERPC_EXCP_603;
4747    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4748    pcc->bfd_mach = bfd_mach_ppc_603;
4749    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4750                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4751}
4752
4753static void init_proc_603E(CPUPPCState *env)
4754{
4755    register_ne_601_sprs(env);
4756    register_sdr1_sprs(env);
4757    register_603_sprs(env);
4758    /* Time base */
4759    register_tbl(env);
4760    /* hardware implementation registers */
4761    /* XXX : not implemented */
4762    spr_register(env, SPR_HID0, "HID0",
4763                 SPR_NOACCESS, SPR_NOACCESS,
4764                 &spr_read_generic, &spr_write_generic,
4765                 0x00000000);
4766    /* XXX : not implemented */
4767    spr_register(env, SPR_HID1, "HID1",
4768                 SPR_NOACCESS, SPR_NOACCESS,
4769                 &spr_read_generic, &spr_write_generic,
4770                 0x00000000);
4771    /* Memory management */
4772    register_low_BATs(env);
4773    register_6xx_7xx_soft_tlb(env, 64, 2);
4774    init_excp_603(env);
4775    env->dcache_line_size = 32;
4776    env->icache_line_size = 32;
4777    /* Allocate hardware IRQ controller */
4778    ppc6xx_irq_init(env_archcpu(env));
4779}
4780
4781POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4782{
4783    DeviceClass *dc = DEVICE_CLASS(oc);
4784    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4785
4786    dc->desc = "PowerPC 603e";
4787    pcc->init_proc = init_proc_603E;
4788    pcc->check_pow = check_pow_hid0;
4789    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4790                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4791                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4792                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4793                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4794                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4795                       PPC_SEGMENT | PPC_EXTERN;
4796    pcc->msr_mask = (1ull << MSR_POW) |
4797                    (1ull << MSR_TGPR) |
4798                    (1ull << MSR_ILE) |
4799                    (1ull << MSR_EE) |
4800                    (1ull << MSR_PR) |
4801                    (1ull << MSR_FP) |
4802                    (1ull << MSR_ME) |
4803                    (1ull << MSR_FE0) |
4804                    (1ull << MSR_SE) |
4805                    (1ull << MSR_DE) |
4806                    (1ull << MSR_FE1) |
4807                    (1ull << MSR_EP) |
4808                    (1ull << MSR_IR) |
4809                    (1ull << MSR_DR) |
4810                    (1ull << MSR_RI) |
4811                    (1ull << MSR_LE);
4812    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4813    pcc->excp_model = POWERPC_EXCP_603E;
4814    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4815    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4816    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4817                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4818}
4819
4820static void init_proc_604(CPUPPCState *env)
4821{
4822    register_ne_601_sprs(env);
4823    register_sdr1_sprs(env);
4824    register_604_sprs(env);
4825    /* Time base */
4826    register_tbl(env);
4827    /* Hardware implementation registers */
4828    /* XXX : not implemented */
4829    spr_register(env, SPR_HID0, "HID0",
4830                 SPR_NOACCESS, SPR_NOACCESS,
4831                 &spr_read_generic, &spr_write_generic,
4832                 0x00000000);
4833    /* Memory management */
4834    register_low_BATs(env);
4835    init_excp_604(env);
4836    env->dcache_line_size = 32;
4837    env->icache_line_size = 32;
4838    /* Allocate hardware IRQ controller */
4839    ppc6xx_irq_init(env_archcpu(env));
4840}
4841
4842POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
4843{
4844    DeviceClass *dc = DEVICE_CLASS(oc);
4845    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4846
4847    dc->desc = "PowerPC 604";
4848    pcc->init_proc = init_proc_604;
4849    pcc->check_pow = check_pow_nocheck;
4850    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4851                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4852                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4853                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4854                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4855                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4856                       PPC_SEGMENT | PPC_EXTERN;
4857    pcc->msr_mask = (1ull << MSR_POW) |
4858                    (1ull << MSR_ILE) |
4859                    (1ull << MSR_EE) |
4860                    (1ull << MSR_PR) |
4861                    (1ull << MSR_FP) |
4862                    (1ull << MSR_ME) |
4863                    (1ull << MSR_FE0) |
4864                    (1ull << MSR_SE) |
4865                    (1ull << MSR_DE) |
4866                    (1ull << MSR_FE1) |
4867                    (1ull << MSR_EP) |
4868                    (1ull << MSR_IR) |
4869                    (1ull << MSR_DR) |
4870                    (1ull << MSR_PMM) |
4871                    (1ull << MSR_RI) |
4872                    (1ull << MSR_LE);
4873    pcc->mmu_model = POWERPC_MMU_32B;
4874    pcc->excp_model = POWERPC_EXCP_604;
4875    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4876    pcc->bfd_mach = bfd_mach_ppc_604;
4877    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4878                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4879}
4880
4881static void init_proc_604E(CPUPPCState *env)
4882{
4883    register_ne_601_sprs(env);
4884    register_sdr1_sprs(env);
4885    register_604_sprs(env);
4886    /* XXX : not implemented */
4887    spr_register(env, SPR_7XX_MMCR1, "MMCR1",
4888                 SPR_NOACCESS, SPR_NOACCESS,
4889                 &spr_read_generic, &spr_write_generic,
4890                 0x00000000);
4891    /* XXX : not implemented */
4892    spr_register(env, SPR_7XX_PMC3, "PMC3",
4893                 SPR_NOACCESS, SPR_NOACCESS,
4894                 &spr_read_generic, &spr_write_generic,
4895                 0x00000000);
4896    /* XXX : not implemented */
4897    spr_register(env, SPR_7XX_PMC4, "PMC4",
4898                 SPR_NOACCESS, SPR_NOACCESS,
4899                 &spr_read_generic, &spr_write_generic,
4900                 0x00000000);
4901    /* Time base */
4902    register_tbl(env);
4903    /* Hardware implementation registers */
4904    /* XXX : not implemented */
4905    spr_register(env, SPR_HID0, "HID0",
4906                 SPR_NOACCESS, SPR_NOACCESS,
4907                 &spr_read_generic, &spr_write_generic,
4908                 0x00000000);
4909    /* XXX : not implemented */
4910    spr_register(env, SPR_HID1, "HID1",
4911                 SPR_NOACCESS, SPR_NOACCESS,
4912                 &spr_read_generic, &spr_write_generic,
4913                 0x00000000);
4914    /* Memory management */
4915    register_low_BATs(env);
4916    init_excp_604(env);
4917    env->dcache_line_size = 32;
4918    env->icache_line_size = 32;
4919    /* Allocate hardware IRQ controller */
4920    ppc6xx_irq_init(env_archcpu(env));
4921}
4922
4923POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
4924{
4925    DeviceClass *dc = DEVICE_CLASS(oc);
4926    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4927
4928    dc->desc = "PowerPC 604E";
4929    pcc->init_proc = init_proc_604E;
4930    pcc->check_pow = check_pow_nocheck;
4931    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4932                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4933                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4934                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4935                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4936                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4937                       PPC_SEGMENT | PPC_EXTERN;
4938    pcc->msr_mask = (1ull << MSR_POW) |
4939                    (1ull << MSR_ILE) |
4940                    (1ull << MSR_EE) |
4941                    (1ull << MSR_PR) |
4942                    (1ull << MSR_FP) |
4943                    (1ull << MSR_ME) |
4944                    (1ull << MSR_FE0) |
4945                    (1ull << MSR_SE) |
4946                    (1ull << MSR_DE) |
4947                    (1ull << MSR_FE1) |
4948                    (1ull << MSR_EP) |
4949                    (1ull << MSR_IR) |
4950                    (1ull << MSR_DR) |
4951                    (1ull << MSR_PMM) |
4952                    (1ull << MSR_RI) |
4953                    (1ull << MSR_LE);
4954    pcc->mmu_model = POWERPC_MMU_32B;
4955    pcc->excp_model = POWERPC_EXCP_604;
4956    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4957    pcc->bfd_mach = bfd_mach_ppc_604;
4958    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4959                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4960}
4961
4962static void init_proc_740(CPUPPCState *env)
4963{
4964    register_ne_601_sprs(env);
4965    register_sdr1_sprs(env);
4966    register_7xx_sprs(env);
4967    /* Time base */
4968    register_tbl(env);
4969    /* Thermal management */
4970    register_thrm_sprs(env);
4971    /* Hardware implementation registers */
4972    /* XXX : not implemented */
4973    spr_register(env, SPR_HID0, "HID0",
4974                 SPR_NOACCESS, SPR_NOACCESS,
4975                 &spr_read_generic, &spr_write_generic,
4976                 0x00000000);
4977    /* XXX : not implemented */
4978    spr_register(env, SPR_HID1, "HID1",
4979                 SPR_NOACCESS, SPR_NOACCESS,
4980                 &spr_read_generic, &spr_write_generic,
4981                 0x00000000);
4982    /* Memory management */
4983    register_low_BATs(env);
4984    init_excp_7x0(env);
4985    env->dcache_line_size = 32;
4986    env->icache_line_size = 32;
4987    /* Allocate hardware IRQ controller */
4988    ppc6xx_irq_init(env_archcpu(env));
4989}
4990
4991POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
4992{
4993    DeviceClass *dc = DEVICE_CLASS(oc);
4994    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4995
4996    dc->desc = "PowerPC 740";
4997    pcc->init_proc = init_proc_740;
4998    pcc->check_pow = check_pow_hid0;
4999    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5000                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |

5001                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5002                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5003                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5004                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5005                       PPC_SEGMENT | PPC_EXTERN;
5006    pcc->msr_mask = (1ull << MSR_POW) |
5007                    (1ull << MSR_ILE) |
5008                    (1ull << MSR_EE) |
5009                    (1ull << MSR_PR) |
5010                    (1ull << MSR_FP) |
5011                    (1ull << MSR_ME) |
5012                    (1ull << MSR_FE0) |
5013                    (1ull << MSR_SE) |
5014                    (1ull << MSR_DE) |
5015                    (1ull << MSR_FE1) |
5016                    (1ull << MSR_EP) |
5017                    (1ull << MSR_IR) |
5018                    (1ull << MSR_DR) |
5019                    (1ull << MSR_PMM) |
5020                    (1ull << MSR_RI) |
5021                    (1ull << MSR_LE);
5022    pcc->mmu_model = POWERPC_MMU_32B;
5023    pcc->excp_model = POWERPC_EXCP_7x0;
5024    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5025    pcc->bfd_mach = bfd_mach_ppc_750;
5026    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5027                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5028}
5029
5030static void init_proc_750(CPUPPCState *env)
5031{
5032    register_ne_601_sprs(env);
5033    register_sdr1_sprs(env);
5034    register_7xx_sprs(env);
5035    /* XXX : not implemented */
5036    spr_register(env, SPR_L2CR, "L2CR",
5037                 SPR_NOACCESS, SPR_NOACCESS,
5038                 &spr_read_generic, spr_access_nop,
5039                 0x00000000);
5040    /* Time base */
5041    register_tbl(env);
5042    /* Thermal management */
5043    register_thrm_sprs(env);
5044    /* Hardware implementation registers */
5045    /* XXX : not implemented */
5046    spr_register(env, SPR_HID0, "HID0",
5047                 SPR_NOACCESS, SPR_NOACCESS,
5048                 &spr_read_generic, &spr_write_generic,
5049                 0x00000000);
5050    /* XXX : not implemented */
5051    spr_register(env, SPR_HID1, "HID1",
5052                 SPR_NOACCESS, SPR_NOACCESS,
5053                 &spr_read_generic, &spr_write_generic,
5054                 0x00000000);
5055    /* Memory management */
5056    register_low_BATs(env);
5057    /*
5058     * XXX: high BATs are also present but are known to be bugged on
5059     *      die version 1.x
5060     */
5061    init_excp_7x0(env);
5062    env->dcache_line_size = 32;
5063    env->icache_line_size = 32;
5064    /* Allocate hardware IRQ controller */
5065    ppc6xx_irq_init(env_archcpu(env));
5066}
5067
5068POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5069{
5070    DeviceClass *dc = DEVICE_CLASS(oc);
5071    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5072
5073    dc->desc = "PowerPC 750";
5074    pcc->init_proc = init_proc_750;
5075    pcc->check_pow = check_pow_hid0;
5076    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5077                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5078                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5079                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5080                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5081                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5082                       PPC_SEGMENT | PPC_EXTERN;
5083    pcc->msr_mask = (1ull << MSR_POW) |
5084                    (1ull << MSR_ILE) |
5085                    (1ull << MSR_EE) |
5086                    (1ull << MSR_PR) |
5087                    (1ull << MSR_FP) |
5088                    (1ull << MSR_ME) |
5089                    (1ull << MSR_FE0) |
5090                    (1ull << MSR_SE) |
5091                    (1ull << MSR_DE) |
5092                    (1ull << MSR_FE1) |
5093                    (1ull << MSR_EP) |
5094                    (1ull << MSR_IR) |
5095                    (1ull << MSR_DR) |
5096                    (1ull << MSR_PMM) |
5097                    (1ull << MSR_RI) |
5098                    (1ull << MSR_LE);
5099    pcc->mmu_model = POWERPC_MMU_32B;
5100    pcc->excp_model = POWERPC_EXCP_7x0;
5101    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5102    pcc->bfd_mach = bfd_mach_ppc_750;
5103    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5104                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5105}
5106
5107static void init_proc_750cl(CPUPPCState *env)
5108{
5109    register_ne_601_sprs(env);
5110    register_sdr1_sprs(env);
5111    register_7xx_sprs(env);
5112    /* XXX : not implemented */
5113    spr_register(env, SPR_L2CR, "L2CR",
5114                 SPR_NOACCESS, SPR_NOACCESS,
5115                 &spr_read_generic, spr_access_nop,
5116                 0x00000000);
5117    /* Time base */
5118    register_tbl(env);
5119    /* Thermal management */
5120    /* Those registers are fake on 750CL */
5121    spr_register(env, SPR_THRM1, "THRM1",
5122                 SPR_NOACCESS, SPR_NOACCESS,
5123                 &spr_read_generic, &spr_write_generic,
5124                 0x00000000);
5125    spr_register(env, SPR_THRM2, "THRM2",
5126                 SPR_NOACCESS, SPR_NOACCESS,
5127                 &spr_read_generic, &spr_write_generic,
5128                 0x00000000);
5129    spr_register(env, SPR_THRM3, "THRM3",
5130                 SPR_NOACCESS, SPR_NOACCESS,
5131                 &spr_read_generic, &spr_write_generic,
5132                 0x00000000);
5133    /* XXX: not implemented */
5134    spr_register(env, SPR_750_TDCL, "TDCL",
5135                 SPR_NOACCESS, SPR_NOACCESS,
5136                 &spr_read_generic, &spr_write_generic,
5137                 0x00000000);
5138    spr_register(env, SPR_750_TDCH, "TDCH",
5139                 SPR_NOACCESS, SPR_NOACCESS,
5140                 &spr_read_generic, &spr_write_generic,
5141                 0x00000000);
5142    /* DMA */
5143    /* XXX : not implemented */
5144    spr_register(env, SPR_750_WPAR, "WPAR",
5145                 SPR_NOACCESS, SPR_NOACCESS,
5146                 &spr_read_generic, &spr_write_generic,
5147                 0x00000000);
5148    spr_register(env, SPR_750_DMAL, "DMAL",
5149                 SPR_NOACCESS, SPR_NOACCESS,
5150                 &spr_read_generic, &spr_write_generic,
5151                 0x00000000);
5152    spr_register(env, SPR_750_DMAU, "DMAU",
5153                 SPR_NOACCESS, SPR_NOACCESS,
5154                 &spr_read_generic, &spr_write_generic,
5155                 0x00000000);
5156    /* Hardware implementation registers */
5157    /* XXX : not implemented */
5158    spr_register(env, SPR_HID0, "HID0",
5159                 SPR_NOACCESS, SPR_NOACCESS,
5160                 &spr_read_generic, &spr_write_generic,
5161                 0x00000000);
5162    /* XXX : not implemented */
5163    spr_register(env, SPR_HID1, "HID1",
5164                 SPR_NOACCESS, SPR_NOACCESS,
5165                 &spr_read_generic, &spr_write_generic,
5166                 0x00000000);
5167    /* XXX : not implemented */
5168    spr_register(env, SPR_750CL_HID2, "HID2",
5169                 SPR_NOACCESS, SPR_NOACCESS,
5170                 &spr_read_generic, &spr_write_generic,
5171                 0x00000000);
5172    /* XXX : not implemented */
5173    spr_register(env, SPR_750CL_HID4, "HID4",
5174                 SPR_NOACCESS, SPR_NOACCESS,
5175                 &spr_read_generic, &spr_write_generic,
5176                 0x00000000);
5177    /* Quantization registers */
5178    /* XXX : not implemented */
5179    spr_register(env, SPR_750_GQR0, "GQR0",
5180                 SPR_NOACCESS, SPR_NOACCESS,
5181                 &spr_read_generic, &spr_write_generic,
5182                 0x00000000);
5183    /* XXX : not implemented */
5184    spr_register(env, SPR_750_GQR1, "GQR1",
5185                 SPR_NOACCESS, SPR_NOACCESS,
5186                 &spr_read_generic, &spr_write_generic,
5187                 0x00000000);
5188    /* XXX : not implemented */
5189    spr_register(env, SPR_750_GQR2, "GQR2",
5190                 SPR_NOACCESS, SPR_NOACCESS,
5191                 &spr_read_generic, &spr_write_generic,
5192                 0x00000000);
5193    /* XXX : not implemented */
5194    spr_register(env, SPR_750_GQR3, "GQR3",
5195                 SPR_NOACCESS, SPR_NOACCESS,
5196                 &spr_read_generic, &spr_write_generic,
5197                 0x00000000);
5198    /* XXX : not implemented */
5199    spr_register(env, SPR_750_GQR4, "GQR4",
5200                 SPR_NOACCESS, SPR_NOACCESS,
5201                 &spr_read_generic, &spr_write_generic,
5202                 0x00000000);
5203    /* XXX : not implemented */
5204    spr_register(env, SPR_750_GQR5, "GQR5",
5205                 SPR_NOACCESS, SPR_NOACCESS,
5206                 &spr_read_generic, &spr_write_generic,
5207                 0x00000000);
5208    /* XXX : not implemented */
5209    spr_register(env, SPR_750_GQR6, "GQR6",
5210                 SPR_NOACCESS, SPR_NOACCESS,
5211                 &spr_read_generic, &spr_write_generic,
5212                 0x00000000);
5213    /* XXX : not implemented */
5214    spr_register(env, SPR_750_GQR7, "GQR7",
5215                 SPR_NOACCESS, SPR_NOACCESS,
5216                 &spr_read_generic, &spr_write_generic,
5217                 0x00000000);
5218    /* Memory management */
5219    register_low_BATs(env);
5220    /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5221    register_high_BATs(env);
5222    init_excp_750cl(env);
5223    env->dcache_line_size = 32;
5224    env->icache_line_size = 32;
5225    /* Allocate hardware IRQ controller */
5226    ppc6xx_irq_init(env_archcpu(env));
5227}
5228
5229POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5230{
5231    DeviceClass *dc = DEVICE_CLASS(oc);
5232    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5233
5234    dc->desc = "PowerPC 750 CL";
5235    pcc->init_proc = init_proc_750cl;
5236    pcc->check_pow = check_pow_hid0;
5237    /*
5238     * XXX: not implemented:
5239     * cache lock instructions:
5240     * dcbz_l
5241     * floating point paired instructions
5242     * psq_lux
5243     * psq_lx
5244     * psq_stux
5245     * psq_stx
5246     * ps_abs
5247     * ps_add
5248     * ps_cmpo0
5249     * ps_cmpo1
5250     * ps_cmpu0
5251     * ps_cmpu1
5252     * ps_div
5253     * ps_madd
5254     * ps_madds0
5255     * ps_madds1
5256     * ps_merge00
5257     * ps_merge01
5258     * ps_merge10
5259     * ps_merge11
5260     * ps_mr
5261     * ps_msub
5262     * ps_mul
5263     * ps_muls0
5264     * ps_muls1
5265     * ps_nabs
5266     * ps_neg
5267     * ps_nmadd
5268     * ps_nmsub
5269     * ps_res
5270     * ps_rsqrte
5271     * ps_sel
5272     * ps_sub
5273     * ps_sum0
5274     * ps_sum1
5275     */
5276    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5277                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5278                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5279                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5280                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5281                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5282                       PPC_SEGMENT | PPC_EXTERN;
5283    pcc->msr_mask = (1ull << MSR_POW) |
5284                    (1ull << MSR_ILE) |
5285                    (1ull << MSR_EE) |
5286                    (1ull << MSR_PR) |
5287                    (1ull << MSR_FP) |
5288                    (1ull << MSR_ME) |
5289                    (1ull << MSR_FE0) |
5290                    (1ull << MSR_SE) |
5291                    (1ull << MSR_DE) |
5292                    (1ull << MSR_FE1) |
5293                    (1ull << MSR_EP) |
5294                    (1ull << MSR_IR) |
5295                    (1ull << MSR_DR) |
5296                    (1ull << MSR_PMM) |
5297                    (1ull << MSR_RI) |
5298                    (1ull << MSR_LE);
5299    pcc->mmu_model = POWERPC_MMU_32B;
5300    pcc->excp_model = POWERPC_EXCP_7x0;
5301    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5302    pcc->bfd_mach = bfd_mach_ppc_750;
5303    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5304                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5305}
5306
5307static void init_proc_750cx(CPUPPCState *env)
5308{
5309    register_ne_601_sprs(env);
5310    register_sdr1_sprs(env);
5311    register_7xx_sprs(env);
5312    /* XXX : not implemented */
5313    spr_register(env, SPR_L2CR, "L2CR",
5314                 SPR_NOACCESS, SPR_NOACCESS,
5315                 &spr_read_generic, spr_access_nop,
5316                 0x00000000);
5317    /* Time base */
5318    register_tbl(env);
5319    /* Thermal management */
5320    register_thrm_sprs(env);
5321    /* This register is not implemented but is present for compatibility */
5322    spr_register(env, SPR_SDA, "SDA",
5323                 SPR_NOACCESS, SPR_NOACCESS,
5324                 &spr_read_generic, &spr_write_generic,
5325                 0x00000000);
5326    /* Hardware implementation registers */
5327    /* XXX : not implemented */
5328    spr_register(env, SPR_HID0, "HID0",
5329                 SPR_NOACCESS, SPR_NOACCESS,
5330                 &spr_read_generic, &spr_write_generic,
5331                 0x00000000);
5332    /* XXX : not implemented */
5333    spr_register(env, SPR_HID1, "HID1",
5334                 SPR_NOACCESS, SPR_NOACCESS,
5335                 &spr_read_generic, &spr_write_generic,
5336                 0x00000000);
5337    /* Memory management */
5338    register_low_BATs(env);
5339    /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5340    register_high_BATs(env);
5341    init_excp_750cx(env);
5342    env->dcache_line_size = 32;
5343    env->icache_line_size = 32;
5344    /* Allocate hardware IRQ controller */
5345    ppc6xx_irq_init(env_archcpu(env));
5346}
5347
5348POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5349{
5350    DeviceClass *dc = DEVICE_CLASS(oc);
5351    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5352
5353    dc->desc = "PowerPC 750CX";
5354    pcc->init_proc = init_proc_750cx;
5355    pcc->check_pow = check_pow_hid0;
5356    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5357                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5358                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5359                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5360                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5361                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5362                       PPC_SEGMENT | PPC_EXTERN;
5363    pcc->msr_mask = (1ull << MSR_POW) |
5364                    (1ull << MSR_ILE) |
5365                    (1ull << MSR_EE) |
5366                    (1ull << MSR_PR) |
5367                    (1ull << MSR_FP) |
5368                    (1ull << MSR_ME) |
5369                    (1ull << MSR_FE0) |
5370                    (1ull << MSR_SE) |
5371                    (1ull << MSR_DE) |
5372                    (1ull << MSR_FE1) |
5373                    (1ull << MSR_EP) |
5374                    (1ull << MSR_IR) |
5375                    (1ull << MSR_DR) |
5376                    (1ull << MSR_PMM) |
5377                    (1ull << MSR_RI) |
5378                    (1ull << MSR_LE);
5379    pcc->mmu_model = POWERPC_MMU_32B;
5380    pcc->excp_model = POWERPC_EXCP_7x0;
5381    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5382    pcc->bfd_mach = bfd_mach_ppc_750;
5383    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5384                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5385}
5386
5387static void init_proc_750fx(CPUPPCState *env)
5388{
5389    register_ne_601_sprs(env);
5390    register_sdr1_sprs(env);
5391    register_7xx_sprs(env);
5392    /* XXX : not implemented */
5393    spr_register(env, SPR_L2CR, "L2CR",
5394                 SPR_NOACCESS, SPR_NOACCESS,
5395                 &spr_read_generic, spr_access_nop,
5396                 0x00000000);
5397    /* Time base */
5398    register_tbl(env);
5399    /* Thermal management */
5400    register_thrm_sprs(env);
5401    /* XXX : not implemented */
5402    spr_register(env, SPR_750_THRM4, "THRM4",
5403                 SPR_NOACCESS, SPR_NOACCESS,
5404                 &spr_read_generic, &spr_write_generic,
5405                 0x00000000);
5406    /* Hardware implementation registers */
5407    /* XXX : not implemented */
5408    spr_register(env, SPR_HID0, "HID0",
5409                 SPR_NOACCESS, SPR_NOACCESS,
5410                 &spr_read_generic, &spr_write_generic,
5411                 0x00000000);
5412    /* XXX : not implemented */
5413    spr_register(env, SPR_HID1, "HID1",
5414                 SPR_NOACCESS, SPR_NOACCESS,
5415                 &spr_read_generic, &spr_write_generic,
5416                 0x00000000);
5417    /* XXX : not implemented */
5418    spr_register(env, SPR_750FX_HID2, "HID2",
5419                 SPR_NOACCESS, SPR_NOACCESS,
5420                 &spr_read_generic, &spr_write_generic,
5421                 0x00000000);
5422    /* Memory management */
5423    register_low_BATs(env);
5424    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5425    register_high_BATs(env);
5426    init_excp_7x0(env);
5427    env->dcache_line_size = 32;
5428    env->icache_line_size = 32;
5429    /* Allocate hardware IRQ controller */
5430    ppc6xx_irq_init(env_archcpu(env));
5431}
5432
5433POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5434{
5435    DeviceClass *dc = DEVICE_CLASS(oc);
5436    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5437
5438    dc->desc = "PowerPC 750FX";
5439    pcc->init_proc = init_proc_750fx;
5440    pcc->check_pow = check_pow_hid0;
5441    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5442                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5443                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5444                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5445                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5446                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5447                       PPC_SEGMENT | PPC_EXTERN;
5448    pcc->msr_mask = (1ull << MSR_POW) |
5449                    (1ull << MSR_ILE) |
5450                    (1ull << MSR_EE) |
5451                    (1ull << MSR_PR) |
5452                    (1ull << MSR_FP) |
5453                    (1ull << MSR_ME) |
5454                    (1ull << MSR_FE0) |
5455                    (1ull << MSR_SE) |
5456                    (1ull << MSR_DE) |
5457                    (1ull << MSR_FE1) |
5458                    (1ull << MSR_EP) |
5459                    (1ull << MSR_IR) |
5460                    (1ull << MSR_DR) |
5461                    (1ull << MSR_PMM) |
5462                    (1ull << MSR_RI) |
5463                    (1ull << MSR_LE);
5464    pcc->mmu_model = POWERPC_MMU_32B;
5465    pcc->excp_model = POWERPC_EXCP_7x0;
5466    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5467    pcc->bfd_mach = bfd_mach_ppc_750;
5468    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5469                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5470}
5471
5472static void init_proc_750gx(CPUPPCState *env)
5473{
5474    register_ne_601_sprs(env);
5475    register_sdr1_sprs(env);
5476    register_7xx_sprs(env);
5477    /* XXX : not implemented (XXX: different from 750fx) */
5478    spr_register(env, SPR_L2CR, "L2CR",
5479                 SPR_NOACCESS, SPR_NOACCESS,
5480                 &spr_read_generic, spr_access_nop,
5481                 0x00000000);
5482    /* Time base */
5483    register_tbl(env);
5484    /* Thermal management */
5485    register_thrm_sprs(env);
5486    /* XXX : not implemented */
5487    spr_register(env, SPR_750_THRM4, "THRM4",
5488                 SPR_NOACCESS, SPR_NOACCESS,
5489                 &spr_read_generic, &spr_write_generic,
5490                 0x00000000);
5491    /* Hardware implementation registers */
5492    /* XXX : not implemented (XXX: different from 750fx) */
5493    spr_register(env, SPR_HID0, "HID0",
5494                 SPR_NOACCESS, SPR_NOACCESS,
5495                 &spr_read_generic, &spr_write_generic,
5496                 0x00000000);
5497    /* XXX : not implemented */
5498    spr_register(env, SPR_HID1, "HID1",
5499                 SPR_NOACCESS, SPR_NOACCESS,
5500                 &spr_read_generic, &spr_write_generic,
5501                 0x00000000);
5502    /* XXX : not implemented (XXX: different from 750fx) */
5503    spr_register(env, SPR_750FX_HID2, "HID2",
5504                 SPR_NOACCESS, SPR_NOACCESS,
5505                 &spr_read_generic, &spr_write_generic,
5506                 0x00000000);
5507    /* Memory management */
5508    register_low_BATs(env);
5509    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5510    register_high_BATs(env);
5511    init_excp_7x0(env);
5512    env->dcache_line_size = 32;
5513    env->icache_line_size = 32;
5514    /* Allocate hardware IRQ controller */
5515    ppc6xx_irq_init(env_archcpu(env));
5516}
5517
5518POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5519{
5520    DeviceClass *dc = DEVICE_CLASS(oc);
5521    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5522
5523    dc->desc = "PowerPC 750GX";
5524    pcc->init_proc = init_proc_750gx;
5525    pcc->check_pow = check_pow_hid0;
5526    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5527                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5528                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5529                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5530                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5531                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5532                       PPC_SEGMENT | PPC_EXTERN;
5533    pcc->msr_mask = (1ull << MSR_POW) |
5534                    (1ull << MSR_ILE) |
5535                    (1ull << MSR_EE) |
5536                    (1ull << MSR_PR) |
5537                    (1ull << MSR_FP) |
5538                    (1ull << MSR_ME) |
5539                    (1ull << MSR_FE0) |
5540                    (1ull << MSR_SE) |
5541                    (1ull << MSR_DE) |
5542                    (1ull << MSR_FE1) |
5543                    (1ull << MSR_EP) |
5544                    (1ull << MSR_IR) |
5545                    (1ull << MSR_DR) |
5546                    (1ull << MSR_PMM) |
5547                    (1ull << MSR_RI) |
5548                    (1ull << MSR_LE);
5549    pcc->mmu_model = POWERPC_MMU_32B;
5550    pcc->excp_model = POWERPC_EXCP_7x0;
5551    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5552    pcc->bfd_mach = bfd_mach_ppc_750;
5553    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5554                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5555}
5556
5557static void init_proc_745(CPUPPCState *env)
5558{
5559    register_ne_601_sprs(env);
5560    register_sdr1_sprs(env);
5561    register_7xx_sprs(env);
5562    register_G2_755_sprs(env);
5563    /* Time base */
5564    register_tbl(env);
5565    /* Thermal management */
5566    register_thrm_sprs(env);
5567    /* Hardware implementation registers */
5568    /* XXX : not implemented */
5569    spr_register(env, SPR_HID0, "HID0",
5570                 SPR_NOACCESS, SPR_NOACCESS,
5571                 &spr_read_generic, &spr_write_generic,
5572                 0x00000000);
5573    /* XXX : not implemented */
5574    spr_register(env, SPR_HID1, "HID1",
5575                 SPR_NOACCESS, SPR_NOACCESS,
5576                 &spr_read_generic, &spr_write_generic,
5577                 0x00000000);
5578    /* XXX : not implemented */
5579    spr_register(env, SPR_HID2, "HID2",
5580                 SPR_NOACCESS, SPR_NOACCESS,
5581                 &spr_read_generic, &spr_write_generic,
5582                 0x00000000);
5583    /* Memory management */
5584    register_low_BATs(env);
5585    register_high_BATs(env);
5586    register_6xx_7xx_soft_tlb(env, 64, 2);
5587    init_excp_7x5(env);
5588    env->dcache_line_size = 32;
5589    env->icache_line_size = 32;
5590    /* Allocate hardware IRQ controller */
5591    ppc6xx_irq_init(env_archcpu(env));
5592}
5593
5594POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5595{
5596    DeviceClass *dc = DEVICE_CLASS(oc);
5597    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5598
5599    dc->desc = "PowerPC 745";
5600    pcc->init_proc = init_proc_745;
5601    pcc->check_pow = check_pow_hid0;
5602    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5603                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5604                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5605                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5606                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5607                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5608                       PPC_SEGMENT | PPC_EXTERN;
5609    pcc->msr_mask = (1ull << MSR_POW) |
5610                    (1ull << MSR_ILE) |
5611                    (1ull << MSR_EE) |
5612                    (1ull << MSR_PR) |
5613                    (1ull << MSR_FP) |
5614                    (1ull << MSR_ME) |
5615                    (1ull << MSR_FE0) |
5616                    (1ull << MSR_SE) |
5617                    (1ull << MSR_DE) |
5618                    (1ull << MSR_FE1) |
5619                    (1ull << MSR_EP) |
5620                    (1ull << MSR_IR) |
5621                    (1ull << MSR_DR) |
5622                    (1ull << MSR_PMM) |
5623                    (1ull << MSR_RI) |
5624                    (1ull << MSR_LE);
5625    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5626    pcc->excp_model = POWERPC_EXCP_7x5;
5627    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5628    pcc->bfd_mach = bfd_mach_ppc_750;
5629    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5630                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5631}
5632
5633static void init_proc_755(CPUPPCState *env)
5634{
5635    register_ne_601_sprs(env);
5636    register_sdr1_sprs(env);
5637    register_7xx_sprs(env);
5638    register_G2_755_sprs(env);
5639    /* Time base */
5640    register_tbl(env);
5641    /* L2 cache control */
5642    /* XXX : not implemented */
5643    spr_register(env, SPR_L2CR, "L2CR",
5644                 SPR_NOACCESS, SPR_NOACCESS,
5645                 &spr_read_generic, spr_access_nop,
5646                 0x00000000);
5647    /* XXX : not implemented */
5648    spr_register(env, SPR_L2PMCR, "L2PMCR",
5649                 SPR_NOACCESS, SPR_NOACCESS,
5650                 &spr_read_generic, &spr_write_generic,
5651                 0x00000000);
5652    /* Thermal management */
5653    register_thrm_sprs(env);
5654    /* Hardware implementation registers */
5655    /* XXX : not implemented */
5656    spr_register(env, SPR_HID0, "HID0",
5657                 SPR_NOACCESS, SPR_NOACCESS,
5658                 &spr_read_generic, &spr_write_generic,
5659                 0x00000000);
5660    /* XXX : not implemented */
5661    spr_register(env, SPR_HID1, "HID1",
5662                 SPR_NOACCESS, SPR_NOACCESS,
5663                 &spr_read_generic, &spr_write_generic,
5664                 0x00000000);
5665    /* XXX : not implemented */
5666    spr_register(env, SPR_HID2, "HID2",
5667                 SPR_NOACCESS, SPR_NOACCESS,
5668                 &spr_read_generic, &spr_write_generic,
5669                 0x00000000);
5670    /* Memory management */
5671    register_low_BATs(env);
5672    register_high_BATs(env);
5673    register_6xx_7xx_soft_tlb(env, 64, 2);
5674    init_excp_7x5(env);
5675    env->dcache_line_size = 32;
5676    env->icache_line_size = 32;
5677    /* Allocate hardware IRQ controller */
5678    ppc6xx_irq_init(env_archcpu(env));
5679}
5680
5681POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5682{
5683    DeviceClass *dc = DEVICE_CLASS(oc);
5684    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5685
5686    dc->desc = "PowerPC 755";
5687    pcc->init_proc = init_proc_755;
5688    pcc->check_pow = check_pow_hid0;
5689    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5690                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5691                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5692                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5693                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5694                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5695                       PPC_SEGMENT | PPC_EXTERN;
5696    pcc->msr_mask = (1ull << MSR_POW) |
5697                    (1ull << MSR_ILE) |
5698                    (1ull << MSR_EE) |
5699                    (1ull << MSR_PR) |
5700                    (1ull << MSR_FP) |
5701                    (1ull << MSR_ME) |
5702                    (1ull << MSR_FE0) |
5703                    (1ull << MSR_SE) |
5704                    (1ull << MSR_DE) |
5705                    (1ull << MSR_FE1) |
5706                    (1ull << MSR_EP) |
5707                    (1ull << MSR_IR) |
5708                    (1ull << MSR_DR) |
5709                    (1ull << MSR_PMM) |
5710                    (1ull << MSR_RI) |
5711                    (1ull << MSR_LE);
5712    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5713    pcc->excp_model = POWERPC_EXCP_7x5;
5714    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5715    pcc->bfd_mach = bfd_mach_ppc_750;
5716    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5717                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5718}
5719
5720static void init_proc_7400(CPUPPCState *env)
5721{
5722    register_ne_601_sprs(env);
5723    register_sdr1_sprs(env);
5724    register_7xx_sprs(env);
5725    /* Time base */
5726    register_tbl(env);
5727    /* 74xx specific SPR */
5728    register_74xx_sprs(env);
5729    vscr_init(env, 0x00010000);
5730    /* XXX : not implemented */
5731    spr_register(env, SPR_UBAMR, "UBAMR",
5732                 &spr_read_ureg, SPR_NOACCESS,
5733                 &spr_read_ureg, SPR_NOACCESS,
5734                 0x00000000);
5735    /* XXX: this seems not implemented on all revisions. */
5736    /* XXX : not implemented */
5737    spr_register(env, SPR_MSSCR1, "MSSCR1",
5738                 SPR_NOACCESS, SPR_NOACCESS,
5739                 &spr_read_generic, &spr_write_generic,
5740                 0x00000000);
5741    /* Thermal management */
5742    register_thrm_sprs(env);
5743    /* Memory management */
5744    register_low_BATs(env);
5745    init_excp_7400(env);
5746    env->dcache_line_size = 32;
5747    env->icache_line_size = 32;
5748    /* Allocate hardware IRQ controller */
5749    ppc6xx_irq_init(env_archcpu(env));
5750}
5751
5752POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5753{
5754    DeviceClass *dc = DEVICE_CLASS(oc);
5755    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5756
5757    dc->desc = "PowerPC 7400 (aka G4)";
5758    pcc->init_proc = init_proc_7400;
5759    pcc->check_pow = check_pow_hid0;
5760    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5761                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5762                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5763                       PPC_FLOAT_STFIWX |
5764                       PPC_CACHE | PPC_CACHE_ICBI |
5765                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5766                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5767                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5768                       PPC_MEM_TLBIA |
5769                       PPC_SEGMENT | PPC_EXTERN |
5770                       PPC_ALTIVEC;
5771    pcc->msr_mask = (1ull << MSR_VR) |
5772                    (1ull << MSR_POW) |
5773                    (1ull << MSR_ILE) |
5774                    (1ull << MSR_EE) |
5775                    (1ull << MSR_PR) |
5776                    (1ull << MSR_FP) |
5777                    (1ull << MSR_ME) |
5778                    (1ull << MSR_FE0) |
5779                    (1ull << MSR_SE) |
5780                    (1ull << MSR_DE) |
5781                    (1ull << MSR_FE1) |
5782                    (1ull << MSR_EP) |
5783                    (1ull << MSR_IR) |
5784                    (1ull << MSR_DR) |
5785                    (1ull << MSR_PMM) |
5786                    (1ull << MSR_RI) |
5787                    (1ull << MSR_LE);
5788    pcc->mmu_model = POWERPC_MMU_32B;
5789    pcc->excp_model = POWERPC_EXCP_74xx;
5790    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5791    pcc->bfd_mach = bfd_mach_ppc_7400;
5792    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5793                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5794                 POWERPC_FLAG_BUS_CLK;
5795}
5796
5797static void init_proc_7410(CPUPPCState *env)
5798{
5799    register_ne_601_sprs(env);
5800    register_sdr1_sprs(env);
5801    register_7xx_sprs(env);
5802    /* Time base */
5803    register_tbl(env);
5804    /* 74xx specific SPR */
5805    register_74xx_sprs(env);
5806    vscr_init(env, 0x00010000);
5807    /* XXX : not implemented */
5808    spr_register(env, SPR_UBAMR, "UBAMR",
5809                 &spr_read_ureg, SPR_NOACCESS,
5810                 &spr_read_ureg, SPR_NOACCESS,
5811                 0x00000000);
5812    /* Thermal management */
5813    register_thrm_sprs(env);
5814    /* L2PMCR */
5815    /* XXX : not implemented */
5816    spr_register(env, SPR_L2PMCR, "L2PMCR",
5817                 SPR_NOACCESS, SPR_NOACCESS,
5818                 &spr_read_generic, &spr_write_generic,
5819                 0x00000000);
5820    /* LDSTDB */
5821    /* XXX : not implemented */
5822    spr_register(env, SPR_LDSTDB, "LDSTDB",
5823                 SPR_NOACCESS, SPR_NOACCESS,
5824                 &spr_read_generic, &spr_write_generic,
5825                 0x00000000);
5826    /* Memory management */
5827    register_low_BATs(env);
5828    init_excp_7400(env);
5829    env->dcache_line_size = 32;
5830    env->icache_line_size = 32;
5831    /* Allocate hardware IRQ controller */
5832    ppc6xx_irq_init(env_archcpu(env));
5833}
5834
5835POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5836{
5837    DeviceClass *dc = DEVICE_CLASS(oc);
5838    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5839
5840    dc->desc = "PowerPC 7410 (aka G4)";
5841    pcc->init_proc = init_proc_7410;
5842    pcc->check_pow = check_pow_hid0;
5843    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5844                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5845                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5846                       PPC_FLOAT_STFIWX |
5847                       PPC_CACHE | PPC_CACHE_ICBI |
5848                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5849                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5850                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5851                       PPC_MEM_TLBIA |
5852                       PPC_SEGMENT | PPC_EXTERN |
5853                       PPC_ALTIVEC;
5854    pcc->msr_mask = (1ull << MSR_VR) |
5855                    (1ull << MSR_POW) |
5856                    (1ull << MSR_ILE) |
5857                    (1ull << MSR_EE) |
5858                    (1ull << MSR_PR) |
5859                    (1ull << MSR_FP) |
5860                    (1ull << MSR_ME) |
5861                    (1ull << MSR_FE0) |
5862                    (1ull << MSR_SE) |
5863                    (1ull << MSR_DE) |
5864                    (1ull << MSR_FE1) |
5865                    (1ull << MSR_EP) |
5866                    (1ull << MSR_IR) |
5867                    (1ull << MSR_DR) |
5868                    (1ull << MSR_PMM) |
5869                    (1ull << MSR_RI) |
5870                    (1ull << MSR_LE);
5871    pcc->mmu_model = POWERPC_MMU_32B;
5872    pcc->excp_model = POWERPC_EXCP_74xx;
5873    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5874    pcc->bfd_mach = bfd_mach_ppc_7400;
5875    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5876                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5877                 POWERPC_FLAG_BUS_CLK;
5878}
5879
5880static void init_proc_7440(CPUPPCState *env)
5881{
5882    register_ne_601_sprs(env);
5883    register_sdr1_sprs(env);
5884    register_7xx_sprs(env);
5885    /* Time base */
5886    register_tbl(env);
5887    /* 74xx specific SPR */
5888    register_74xx_sprs(env);
5889    vscr_init(env, 0x00010000);
5890    /* XXX : not implemented */
5891    spr_register(env, SPR_UBAMR, "UBAMR",
5892                 &spr_read_ureg, SPR_NOACCESS,
5893                 &spr_read_ureg, SPR_NOACCESS,
5894                 0x00000000);
5895    /* LDSTCR */
5896    /* XXX : not implemented */
5897    spr_register(env, SPR_LDSTCR, "LDSTCR",
5898                 SPR_NOACCESS, SPR_NOACCESS,
5899                 &spr_read_generic, &spr_write_generic,
5900                 0x00000000);
5901    /* ICTRL */
5902    /* XXX : not implemented */
5903    spr_register(env, SPR_ICTRL, "ICTRL",
5904                 SPR_NOACCESS, SPR_NOACCESS,
5905                 &spr_read_generic, &spr_write_generic,
5906                 0x00000000);
5907    /* MSSSR0 */
5908    /* XXX : not implemented */
5909    spr_register(env, SPR_MSSSR0, "MSSSR0",
5910                 SPR_NOACCESS, SPR_NOACCESS,
5911                 &spr_read_generic, &spr_write_generic,
5912                 0x00000000);
5913    /* PMC */
5914    /* XXX : not implemented */
5915    spr_register(env, SPR_7XX_PMC5, "PMC5",
5916                 SPR_NOACCESS, SPR_NOACCESS,
5917                 &spr_read_generic, &spr_write_generic,
5918                 0x00000000);
5919    /* XXX : not implemented */
5920    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5921                 &spr_read_ureg, SPR_NOACCESS,
5922                 &spr_read_ureg, SPR_NOACCESS,
5923                 0x00000000);
5924    /* XXX : not implemented */
5925    spr_register(env, SPR_7XX_PMC6, "PMC6",
5926                 SPR_NOACCESS, SPR_NOACCESS,
5927                 &spr_read_generic, &spr_write_generic,
5928                 0x00000000);
5929    /* XXX : not implemented */
5930    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5931                 &spr_read_ureg, SPR_NOACCESS,
5932                 &spr_read_ureg, SPR_NOACCESS,
5933                 0x00000000);
5934    /* Memory management */
5935    register_low_BATs(env);
5936    register_74xx_soft_tlb(env, 128, 2);
5937    init_excp_7450(env);
5938    env->dcache_line_size = 32;
5939    env->icache_line_size = 32;
5940    /* Allocate hardware IRQ controller */
5941    ppc6xx_irq_init(env_archcpu(env));
5942}
5943
5944POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5945{
5946    DeviceClass *dc = DEVICE_CLASS(oc);
5947    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5948
5949    dc->desc = "PowerPC 7440 (aka G4)";
5950    pcc->init_proc = init_proc_7440;
5951    pcc->check_pow = check_pow_hid0_74xx;
5952    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5953                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5954                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5955                       PPC_FLOAT_STFIWX |
5956                       PPC_CACHE | PPC_CACHE_ICBI |
5957                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5958                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5959                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5960                       PPC_MEM_TLBIA | PPC_74xx_TLB |
5961                       PPC_SEGMENT | PPC_EXTERN |
5962                       PPC_ALTIVEC;
5963    pcc->msr_mask = (1ull << MSR_VR) |
5964                    (1ull << MSR_POW) |
5965                    (1ull << MSR_ILE) |
5966                    (1ull << MSR_EE) |
5967                    (1ull << MSR_PR) |
5968                    (1ull << MSR_FP) |
5969                    (1ull << MSR_ME) |
5970                    (1ull << MSR_FE0) |
5971                    (1ull << MSR_SE) |
5972                    (1ull << MSR_DE) |
5973                    (1ull << MSR_FE1) |
5974                    (1ull << MSR_EP) |
5975                    (1ull << MSR_IR) |
5976                    (1ull << MSR_DR) |
5977                    (1ull << MSR_PMM) |
5978                    (1ull << MSR_RI) |
5979                    (1ull << MSR_LE);
5980    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
5981    pcc->excp_model = POWERPC_EXCP_74xx;
5982    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5983    pcc->bfd_mach = bfd_mach_ppc_7400;
5984    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5985                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5986                 POWERPC_FLAG_BUS_CLK;
5987}
5988
5989static void init_proc_7450(CPUPPCState *env)
5990{
5991    register_ne_601_sprs(env);
5992    register_sdr1_sprs(env);
5993    register_7xx_sprs(env);
5994    /* Time base */
5995    register_tbl(env);
5996    /* 74xx specific SPR */
5997    register_74xx_sprs(env);
5998    vscr_init(env, 0x00010000);
5999    /* Level 3 cache control */
6000    register_l3_ctrl(env);

6001    /* L3ITCR1 */
6002    /* XXX : not implemented */
6003    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6004                 SPR_NOACCESS, SPR_NOACCESS,
6005                 &spr_read_generic, &spr_write_generic,
6006                 0x00000000);
6007    /* L3ITCR2 */
6008    /* XXX : not implemented */
6009    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6010                 SPR_NOACCESS, SPR_NOACCESS,
6011                 &spr_read_generic, &spr_write_generic,
6012                 0x00000000);
6013    /* L3ITCR3 */
6014    /* XXX : not implemented */
6015    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6016                 SPR_NOACCESS, SPR_NOACCESS,
6017                 &spr_read_generic, &spr_write_generic,
6018                 0x00000000);
6019    /* L3OHCR */
6020    /* XXX : not implemented */
6021    spr_register(env, SPR_L3OHCR, "L3OHCR",
6022                 SPR_NOACCESS, SPR_NOACCESS,
6023                 &spr_read_generic, &spr_write_generic,
6024                 0x00000000);
6025    /* XXX : not implemented */
6026    spr_register(env, SPR_UBAMR, "UBAMR",
6027                 &spr_read_ureg, SPR_NOACCESS,
6028                 &spr_read_ureg, SPR_NOACCESS,
6029                 0x00000000);
6030    /* LDSTCR */
6031    /* XXX : not implemented */
6032    spr_register(env, SPR_LDSTCR, "LDSTCR",
6033                 SPR_NOACCESS, SPR_NOACCESS,
6034                 &spr_read_generic, &spr_write_generic,
6035                 0x00000000);
6036    /* ICTRL */
6037    /* XXX : not implemented */
6038    spr_register(env, SPR_ICTRL, "ICTRL",
6039                 SPR_NOACCESS, SPR_NOACCESS,
6040                 &spr_read_generic, &spr_write_generic,
6041                 0x00000000);
6042    /* MSSSR0 */
6043    /* XXX : not implemented */
6044    spr_register(env, SPR_MSSSR0, "MSSSR0",
6045                 SPR_NOACCESS, SPR_NOACCESS,
6046                 &spr_read_generic, &spr_write_generic,
6047                 0x00000000);
6048    /* PMC */
6049    /* XXX : not implemented */
6050    spr_register(env, SPR_7XX_PMC5, "PMC5",
6051                 SPR_NOACCESS, SPR_NOACCESS,
6052                 &spr_read_generic, &spr_write_generic,
6053                 0x00000000);
6054    /* XXX : not implemented */
6055    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6056                 &spr_read_ureg, SPR_NOACCESS,
6057                 &spr_read_ureg, SPR_NOACCESS,
6058                 0x00000000);
6059    /* XXX : not implemented */
6060    spr_register(env, SPR_7XX_PMC6, "PMC6",
6061                 SPR_NOACCESS, SPR_NOACCESS,
6062                 &spr_read_generic, &spr_write_generic,
6063                 0x00000000);
6064    /* XXX : not implemented */
6065    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6066                 &spr_read_ureg, SPR_NOACCESS,
6067                 &spr_read_ureg, SPR_NOACCESS,
6068                 0x00000000);
6069    /* Memory management */
6070    register_low_BATs(env);
6071    register_74xx_soft_tlb(env, 128, 2);
6072    init_excp_7450(env);
6073    env->dcache_line_size = 32;
6074    env->icache_line_size = 32;
6075    /* Allocate hardware IRQ controller */
6076    ppc6xx_irq_init(env_archcpu(env));
6077}
6078
6079POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6080{
6081    DeviceClass *dc = DEVICE_CLASS(oc);
6082    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6083
6084    dc->desc = "PowerPC 7450 (aka G4)";
6085    pcc->init_proc = init_proc_7450;
6086    pcc->check_pow = check_pow_hid0_74xx;
6087    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6088                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6089                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6090                       PPC_FLOAT_STFIWX |
6091                       PPC_CACHE | PPC_CACHE_ICBI |
6092                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6093                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6094                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6095                       PPC_MEM_TLBIA | PPC_74xx_TLB |
6096                       PPC_SEGMENT | PPC_EXTERN |
6097                       PPC_ALTIVEC;
6098    pcc->msr_mask = (1ull << MSR_VR) |
6099                    (1ull << MSR_POW) |
6100                    (1ull << MSR_ILE) |
6101                    (1ull << MSR_EE) |
6102                    (1ull << MSR_PR) |
6103                    (1ull << MSR_FP) |
6104                    (1ull << MSR_ME) |
6105                    (1ull << MSR_FE0) |
6106                    (1ull << MSR_SE) |
6107                    (1ull << MSR_DE) |
6108                    (1ull << MSR_FE1) |
6109                    (1ull << MSR_EP) |
6110                    (1ull << MSR_IR) |
6111                    (1ull << MSR_DR) |
6112                    (1ull << MSR_PMM) |
6113                    (1ull << MSR_RI) |
6114                    (1ull << MSR_LE);
6115    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6116    pcc->excp_model = POWERPC_EXCP_74xx;
6117    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6118    pcc->bfd_mach = bfd_mach_ppc_7400;
6119    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6120                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6121                 POWERPC_FLAG_BUS_CLK;
6122}
6123
6124static void init_proc_7445(CPUPPCState *env)
6125{
6126    register_ne_601_sprs(env);
6127    register_sdr1_sprs(env);
6128    register_7xx_sprs(env);
6129    /* Time base */
6130    register_tbl(env);
6131    /* 74xx specific SPR */
6132    register_74xx_sprs(env);
6133    vscr_init(env, 0x00010000);
6134    /* LDSTCR */
6135    /* XXX : not implemented */
6136    spr_register(env, SPR_LDSTCR, "LDSTCR",
6137                 SPR_NOACCESS, SPR_NOACCESS,
6138                 &spr_read_generic, &spr_write_generic,
6139                 0x00000000);
6140    /* ICTRL */
6141    /* XXX : not implemented */
6142    spr_register(env, SPR_ICTRL, "ICTRL",
6143                 SPR_NOACCESS, SPR_NOACCESS,
6144                 &spr_read_generic, &spr_write_generic,
6145                 0x00000000);
6146    /* MSSSR0 */
6147    /* XXX : not implemented */
6148    spr_register(env, SPR_MSSSR0, "MSSSR0",
6149                 SPR_NOACCESS, SPR_NOACCESS,
6150                 &spr_read_generic, &spr_write_generic,
6151                 0x00000000);
6152    /* PMC */
6153    /* XXX : not implemented */
6154    spr_register(env, SPR_7XX_PMC5, "PMC5",
6155                 SPR_NOACCESS, SPR_NOACCESS,
6156                 &spr_read_generic, &spr_write_generic,
6157                 0x00000000);
6158    /* XXX : not implemented */
6159    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6160                 &spr_read_ureg, SPR_NOACCESS,
6161                 &spr_read_ureg, SPR_NOACCESS,
6162                 0x00000000);
6163    /* XXX : not implemented */
6164    spr_register(env, SPR_7XX_PMC6, "PMC6",
6165                 SPR_NOACCESS, SPR_NOACCESS,
6166                 &spr_read_generic, &spr_write_generic,
6167                 0x00000000);
6168    /* XXX : not implemented */
6169    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6170                 &spr_read_ureg, SPR_NOACCESS,
6171                 &spr_read_ureg, SPR_NOACCESS,
6172                 0x00000000);
6173    /* SPRGs */
6174    spr_register(env, SPR_SPRG4, "SPRG4",
6175                 SPR_NOACCESS, SPR_NOACCESS,
6176                 &spr_read_generic, &spr_write_generic,
6177                 0x00000000);
6178    spr_register(env, SPR_USPRG4, "USPRG4",
6179                 &spr_read_ureg, SPR_NOACCESS,
6180                 &spr_read_ureg, SPR_NOACCESS,
6181                 0x00000000);
6182    spr_register(env, SPR_SPRG5, "SPRG5",
6183                 SPR_NOACCESS, SPR_NOACCESS,
6184                 &spr_read_generic, &spr_write_generic,
6185                 0x00000000);
6186    spr_register(env, SPR_USPRG5, "USPRG5",
6187                 &spr_read_ureg, SPR_NOACCESS,
6188                 &spr_read_ureg, SPR_NOACCESS,
6189                 0x00000000);
6190    spr_register(env, SPR_SPRG6, "SPRG6",
6191                 SPR_NOACCESS, SPR_NOACCESS,
6192                 &spr_read_generic, &spr_write_generic,
6193                 0x00000000);
6194    spr_register(env, SPR_USPRG6, "USPRG6",
6195                 &spr_read_ureg, SPR_NOACCESS,
6196                 &spr_read_ureg, SPR_NOACCESS,
6197                 0x00000000);
6198    spr_register(env, SPR_SPRG7, "SPRG7",
6199                 SPR_NOACCESS, SPR_NOACCESS,
6200                 &spr_read_generic, &spr_write_generic,
6201                 0x00000000);
6202    spr_register(env, SPR_USPRG7, "USPRG7",
6203                 &spr_read_ureg, SPR_NOACCESS,
6204                 &spr_read_ureg, SPR_NOACCESS,
6205                 0x00000000);
6206    /* Memory management */
6207    register_low_BATs(env);
6208    register_high_BATs(env);
6209    register_74xx_soft_tlb(env, 128, 2);
6210    init_excp_7450(env);
6211    env->dcache_line_size = 32;
6212    env->icache_line_size = 32;
6213    /* Allocate hardware IRQ controller */
6214    ppc6xx_irq_init(env_archcpu(env));
6215}
6216
6217POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6218{
6219    DeviceClass *dc = DEVICE_CLASS(oc);
6220    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6221
6222    dc->desc = "PowerPC 7445 (aka G4)";
6223    pcc->init_proc = init_proc_7445;
6224    pcc->check_pow = check_pow_hid0_74xx;
6225    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6226                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6227                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6228                       PPC_FLOAT_STFIWX |
6229                       PPC_CACHE | PPC_CACHE_ICBI |
6230                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6231                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6232                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6233                       PPC_MEM_TLBIA | PPC_74xx_TLB |
6234                       PPC_SEGMENT | PPC_EXTERN |
6235                       PPC_ALTIVEC;
6236    pcc->msr_mask = (1ull << MSR_VR) |
6237                    (1ull << MSR_POW) |
6238                    (1ull << MSR_ILE) |
6239                    (1ull << MSR_EE) |
6240                    (1ull << MSR_PR) |
6241                    (1ull << MSR_FP) |
6242                    (1ull << MSR_ME) |
6243                    (1ull << MSR_FE0) |
6244                    (1ull << MSR_SE) |
6245                    (1ull << MSR_DE) |
6246                    (1ull << MSR_FE1) |
6247                    (1ull << MSR_EP) |
6248                    (1ull << MSR_IR) |
6249                    (1ull << MSR_DR) |
6250                    (1ull << MSR_PMM) |
6251                    (1ull << MSR_RI) |
6252                    (1ull << MSR_LE);
6253    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6254    pcc->excp_model = POWERPC_EXCP_74xx;
6255    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6256    pcc->bfd_mach = bfd_mach_ppc_7400;
6257    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6258                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6259                 POWERPC_FLAG_BUS_CLK;
6260}
6261
6262static void init_proc_7455(CPUPPCState *env)
6263{
6264    register_ne_601_sprs(env);
6265    register_sdr1_sprs(env);
6266    register_7xx_sprs(env);
6267    /* Time base */
6268    register_tbl(env);
6269    /* 74xx specific SPR */
6270    register_74xx_sprs(env);
6271    vscr_init(env, 0x00010000);
6272    /* Level 3 cache control */
6273    register_l3_ctrl(env);
6274    /* LDSTCR */
6275    /* XXX : not implemented */
6276    spr_register(env, SPR_LDSTCR, "LDSTCR",
6277                 SPR_NOACCESS, SPR_NOACCESS,
6278                 &spr_read_generic, &spr_write_generic,
6279                 0x00000000);
6280    /* ICTRL */
6281    /* XXX : not implemented */
6282    spr_register(env, SPR_ICTRL, "ICTRL",
6283                 SPR_NOACCESS, SPR_NOACCESS,
6284                 &spr_read_generic, &spr_write_generic,
6285                 0x00000000);
6286    /* MSSSR0 */
6287    /* XXX : not implemented */
6288    spr_register(env, SPR_MSSSR0, "MSSSR0",
6289                 SPR_NOACCESS, SPR_NOACCESS,
6290                 &spr_read_generic, &spr_write_generic,
6291                 0x00000000);
6292    /* PMC */
6293    /* XXX : not implemented */
6294    spr_register(env, SPR_7XX_PMC5, "PMC5",
6295                 SPR_NOACCESS, SPR_NOACCESS,
6296                 &spr_read_generic, &spr_write_generic,
6297                 0x00000000);
6298    /* XXX : not implemented */
6299    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6300                 &spr_read_ureg, SPR_NOACCESS,
6301                 &spr_read_ureg, SPR_NOACCESS,
6302                 0x00000000);
6303    /* XXX : not implemented */
6304    spr_register(env, SPR_7XX_PMC6, "PMC6",
6305                 SPR_NOACCESS, SPR_NOACCESS,
6306                 &spr_read_generic, &spr_write_generic,
6307                 0x00000000);
6308    /* XXX : not implemented */
6309    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6310                 &spr_read_ureg, SPR_NOACCESS,
6311                 &spr_read_ureg, SPR_NOACCESS,
6312                 0x00000000);
6313    /* SPRGs */
6314    spr_register(env, SPR_SPRG4, "SPRG4",
6315                 SPR_NOACCESS, SPR_NOACCESS,
6316                 &spr_read_generic, &spr_write_generic,
6317                 0x00000000);
6318    spr_register(env, SPR_USPRG4, "USPRG4",
6319                 &spr_read_ureg, SPR_NOACCESS,
6320                 &spr_read_ureg, SPR_NOACCESS,
6321                 0x00000000);
6322    spr_register(env, SPR_SPRG5, "SPRG5",
6323                 SPR_NOACCESS, SPR_NOACCESS,
6324                 &spr_read_generic, &spr_write_generic,
6325                 0x00000000);
6326    spr_register(env, SPR_USPRG5, "USPRG5",
6327                 &spr_read_ureg, SPR_NOACCESS,
6328                 &spr_read_ureg, SPR_NOACCESS,
6329                 0x00000000);
6330    spr_register(env, SPR_SPRG6, "SPRG6",
6331                 SPR_NOACCESS, SPR_NOACCESS,
6332                 &spr_read_generic, &spr_write_generic,
6333                 0x00000000);
6334    spr_register(env, SPR_USPRG6, "USPRG6",
6335                 &spr_read_ureg, SPR_NOACCESS,
6336                 &spr_read_ureg, SPR_NOACCESS,
6337                 0x00000000);
6338    spr_register(env, SPR_SPRG7, "SPRG7",
6339                 SPR_NOACCESS, SPR_NOACCESS,
6340                 &spr_read_generic, &spr_write_generic,
6341                 0x00000000);
6342    spr_register(env, SPR_USPRG7, "USPRG7",
6343                 &spr_read_ureg, SPR_NOACCESS,
6344                 &spr_read_ureg, SPR_NOACCESS,
6345                 0x00000000);
6346    /* Memory management */
6347    register_low_BATs(env);
6348    register_high_BATs(env);
6349    register_74xx_soft_tlb(env, 128, 2);
6350    init_excp_7450(env);
6351    env->dcache_line_size = 32;
6352    env->icache_line_size = 32;
6353    /* Allocate hardware IRQ controller */
6354    ppc6xx_irq_init(env_archcpu(env));
6355}
6356
6357POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6358{
6359    DeviceClass *dc = DEVICE_CLASS(oc);
6360    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6361
6362    dc->desc = "PowerPC 7455 (aka G4)";
6363    pcc->init_proc = init_proc_7455;
6364    pcc->check_pow = check_pow_hid0_74xx;
6365    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6366                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6367                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6368                       PPC_FLOAT_STFIWX |
6369                       PPC_CACHE | PPC_CACHE_ICBI |
6370                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6371                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6372                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6373                       PPC_MEM_TLBIA | PPC_74xx_TLB |
6374                       PPC_SEGMENT | PPC_EXTERN |
6375                       PPC_ALTIVEC;
6376    pcc->msr_mask = (1ull << MSR_VR) |
6377                    (1ull << MSR_POW) |
6378                    (1ull << MSR_ILE) |
6379                    (1ull << MSR_EE) |
6380                    (1ull << MSR_PR) |
6381                    (1ull << MSR_FP) |
6382                    (1ull << MSR_ME) |
6383                    (1ull << MSR_FE0) |
6384                    (1ull << MSR_SE) |
6385                    (1ull << MSR_DE) |
6386                    (1ull << MSR_FE1) |
6387                    (1ull << MSR_EP) |
6388                    (1ull << MSR_IR) |
6389                    (1ull << MSR_DR) |
6390                    (1ull << MSR_PMM) |
6391                    (1ull << MSR_RI) |
6392                    (1ull << MSR_LE);
6393    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6394    pcc->excp_model = POWERPC_EXCP_74xx;
6395    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6396    pcc->bfd_mach = bfd_mach_ppc_7400;
6397    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6398                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6399                 POWERPC_FLAG_BUS_CLK;
6400}
6401
6402static void init_proc_7457(CPUPPCState *env)
6403{
6404    register_ne_601_sprs(env);
6405    register_sdr1_sprs(env);
6406    register_7xx_sprs(env);
6407    /* Time base */
6408    register_tbl(env);
6409    /* 74xx specific SPR */
6410    register_74xx_sprs(env);
6411    vscr_init(env, 0x00010000);
6412    /* Level 3 cache control */
6413    register_l3_ctrl(env);
6414    /* L3ITCR1 */
6415    /* XXX : not implemented */
6416    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6417                 SPR_NOACCESS, SPR_NOACCESS,
6418                 &spr_read_generic, &spr_write_generic,
6419                 0x00000000);
6420    /* L3ITCR2 */
6421    /* XXX : not implemented */
6422    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6423                 SPR_NOACCESS, SPR_NOACCESS,
6424                 &spr_read_generic, &spr_write_generic,
6425                 0x00000000);
6426    /* L3ITCR3 */
6427    /* XXX : not implemented */
6428    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6429                 SPR_NOACCESS, SPR_NOACCESS,
6430                 &spr_read_generic, &spr_write_generic,
6431                 0x00000000);
6432    /* L3OHCR */
6433    /* XXX : not implemented */
6434    spr_register(env, SPR_L3OHCR, "L3OHCR",
6435                 SPR_NOACCESS, SPR_NOACCESS,
6436                 &spr_read_generic, &spr_write_generic,
6437                 0x00000000);
6438    /* LDSTCR */
6439    /* XXX : not implemented */
6440    spr_register(env, SPR_LDSTCR, "LDSTCR",
6441                 SPR_NOACCESS, SPR_NOACCESS,
6442                 &spr_read_generic, &spr_write_generic,
6443                 0x00000000);
6444    /* ICTRL */
6445    /* XXX : not implemented */
6446    spr_register(env, SPR_ICTRL, "ICTRL",
6447                 SPR_NOACCESS, SPR_NOACCESS,
6448                 &spr_read_generic, &spr_write_generic,
6449                 0x00000000);
6450    /* MSSSR0 */
6451    /* XXX : not implemented */
6452    spr_register(env, SPR_MSSSR0, "MSSSR0",
6453                 SPR_NOACCESS, SPR_NOACCESS,
6454                 &spr_read_generic, &spr_write_generic,
6455                 0x00000000);
6456    /* PMC */
6457    /* XXX : not implemented */
6458    spr_register(env, SPR_7XX_PMC5, "PMC5",
6459                 SPR_NOACCESS, SPR_NOACCESS,
6460                 &spr_read_generic, &spr_write_generic,
6461                 0x00000000);
6462    /* XXX : not implemented */
6463    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6464                 &spr_read_ureg, SPR_NOACCESS,
6465                 &spr_read_ureg, SPR_NOACCESS,
6466                 0x00000000);
6467    /* XXX : not implemented */
6468    spr_register(env, SPR_7XX_PMC6, "PMC6",
6469                 SPR_NOACCESS, SPR_NOACCESS,
6470                 &spr_read_generic, &spr_write_generic,
6471                 0x00000000);
6472    /* XXX : not implemented */
6473    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6474                 &spr_read_ureg, SPR_NOACCESS,
6475                 &spr_read_ureg, SPR_NOACCESS,
6476                 0x00000000);
6477    /* SPRGs */
6478    spr_register(env, SPR_SPRG4, "SPRG4",
6479                 SPR_NOACCESS, SPR_NOACCESS,
6480                 &spr_read_generic, &spr_write_generic,
6481                 0x00000000);
6482    spr_register(env, SPR_USPRG4, "USPRG4",
6483                 &spr_read_ureg, SPR_NOACCESS,
6484                 &spr_read_ureg, SPR_NOACCESS,
6485                 0x00000000);
6486    spr_register(env, SPR_SPRG5, "SPRG5",
6487                 SPR_NOACCESS, SPR_NOACCESS,
6488                 &spr_read_generic, &spr_write_generic,
6489                 0x00000000);
6490    spr_register(env, SPR_USPRG5, "USPRG5",
6491                 &spr_read_ureg, SPR_NOACCESS,
6492                 &spr_read_ureg, SPR_NOACCESS,
6493                 0x00000000);
6494    spr_register(env, SPR_SPRG6, "SPRG6",
6495                 SPR_NOACCESS, SPR_NOACCESS,
6496                 &spr_read_generic, &spr_write_generic,
6497                 0x00000000);
6498    spr_register(env, SPR_USPRG6, "USPRG6",
6499                 &spr_read_ureg, SPR_NOACCESS,
6500                 &spr_read_ureg, SPR_NOACCESS,
6501                 0x00000000);
6502    spr_register(env, SPR_SPRG7, "SPRG7",
6503                 SPR_NOACCESS, SPR_NOACCESS,
6504                 &spr_read_generic, &spr_write_generic,
6505                 0x00000000);
6506    spr_register(env, SPR_USPRG7, "USPRG7",
6507                 &spr_read_ureg, SPR_NOACCESS,
6508                 &spr_read_ureg, SPR_NOACCESS,
6509                 0x00000000);
6510    /* Memory management */
6511    register_low_BATs(env);
6512    register_high_BATs(env);
6513    register_74xx_soft_tlb(env, 128, 2);
6514    init_excp_7450(env);
6515    env->dcache_line_size = 32;
6516    env->icache_line_size = 32;
6517    /* Allocate hardware IRQ controller */
6518    ppc6xx_irq_init(env_archcpu(env));
6519}
6520
6521POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6522{
6523    DeviceClass *dc = DEVICE_CLASS(oc);
6524    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6525
6526    dc->desc = "PowerPC 7457 (aka G4)";
6527    pcc->init_proc = init_proc_7457;
6528    pcc->check_pow = check_pow_hid0_74xx;
6529    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6530                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6531                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6532                       PPC_FLOAT_STFIWX |
6533                       PPC_CACHE | PPC_CACHE_ICBI |
6534                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6535                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6536                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6537                       PPC_MEM_TLBIA | PPC_74xx_TLB |
6538                       PPC_SEGMENT | PPC_EXTERN |
6539                       PPC_ALTIVEC;
6540    pcc->msr_mask = (1ull << MSR_VR) |
6541                    (1ull << MSR_POW) |
6542                    (1ull << MSR_ILE) |
6543                    (1ull << MSR_EE) |
6544                    (1ull << MSR_PR) |
6545                    (1ull << MSR_FP) |
6546                    (1ull << MSR_ME) |
6547                    (1ull << MSR_FE0) |
6548                    (1ull << MSR_SE) |
6549                    (1ull << MSR_DE) |
6550                    (1ull << MSR_FE1) |
6551                    (1ull << MSR_EP) |
6552                    (1ull << MSR_IR) |
6553                    (1ull << MSR_DR) |
6554                    (1ull << MSR_PMM) |
6555                    (1ull << MSR_RI) |
6556                    (1ull << MSR_LE);
6557    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6558    pcc->excp_model = POWERPC_EXCP_74xx;
6559    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6560    pcc->bfd_mach = bfd_mach_ppc_7400;
6561    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6562                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6563                 POWERPC_FLAG_BUS_CLK;
6564}
6565
6566static void init_proc_e600(CPUPPCState *env)
6567{
6568    register_ne_601_sprs(env);
6569    register_sdr1_sprs(env);
6570    register_7xx_sprs(env);
6571    /* Time base */
6572    register_tbl(env);
6573    /* 74xx specific SPR */
6574    register_74xx_sprs(env);
6575    vscr_init(env, 0x00010000);
6576    /* XXX : not implemented */
6577    spr_register(env, SPR_UBAMR, "UBAMR",
6578                 &spr_read_ureg, SPR_NOACCESS,
6579                 &spr_read_ureg, SPR_NOACCESS,
6580                 0x00000000);
6581    /* XXX : not implemented */
6582    spr_register(env, SPR_LDSTCR, "LDSTCR",
6583                 SPR_NOACCESS, SPR_NOACCESS,
6584                 &spr_read_generic, &spr_write_generic,
6585                 0x00000000);
6586    /* XXX : not implemented */
6587    spr_register(env, SPR_ICTRL, "ICTRL",
6588                 SPR_NOACCESS, SPR_NOACCESS,
6589                 &spr_read_generic, &spr_write_generic,
6590                 0x00000000);
6591    /* XXX : not implemented */
6592    spr_register(env, SPR_MSSSR0, "MSSSR0",
6593                 SPR_NOACCESS, SPR_NOACCESS,
6594                 &spr_read_generic, &spr_write_generic,
6595                 0x00000000);
6596    /* XXX : not implemented */
6597    spr_register(env, SPR_7XX_PMC5, "PMC5",
6598                 SPR_NOACCESS, SPR_NOACCESS,
6599                 &spr_read_generic, &spr_write_generic,
6600                 0x00000000);
6601    /* XXX : not implemented */
6602    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6603                 &spr_read_ureg, SPR_NOACCESS,
6604                 &spr_read_ureg, SPR_NOACCESS,
6605                 0x00000000);
6606    /* XXX : not implemented */
6607    spr_register(env, SPR_7XX_PMC6, "PMC6",
6608                 SPR_NOACCESS, SPR_NOACCESS,
6609                 &spr_read_generic, &spr_write_generic,
6610                 0x00000000);
6611    /* XXX : not implemented */
6612    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6613                 &spr_read_ureg, SPR_NOACCESS,
6614                 &spr_read_ureg, SPR_NOACCESS,
6615                 0x00000000);
6616    /* SPRGs */
6617    spr_register(env, SPR_SPRG4, "SPRG4",
6618                 SPR_NOACCESS, SPR_NOACCESS,
6619                 &spr_read_generic, &spr_write_generic,
6620                 0x00000000);
6621    spr_register(env, SPR_USPRG4, "USPRG4",
6622                 &spr_read_ureg, SPR_NOACCESS,
6623                 &spr_read_ureg, SPR_NOACCESS,
6624                 0x00000000);
6625    spr_register(env, SPR_SPRG5, "SPRG5",
6626                 SPR_NOACCESS, SPR_NOACCESS,
6627                 &spr_read_generic, &spr_write_generic,
6628                 0x00000000);
6629    spr_register(env, SPR_USPRG5, "USPRG5",
6630                 &spr_read_ureg, SPR_NOACCESS,
6631                 &spr_read_ureg, SPR_NOACCESS,
6632                 0x00000000);
6633    spr_register(env, SPR_SPRG6, "SPRG6",
6634                 SPR_NOACCESS, SPR_NOACCESS,
6635                 &spr_read_generic, &spr_write_generic,
6636                 0x00000000);
6637    spr_register(env, SPR_USPRG6, "USPRG6",
6638                 &spr_read_ureg, SPR_NOACCESS,
6639                 &spr_read_ureg, SPR_NOACCESS,
6640                 0x00000000);
6641    spr_register(env, SPR_SPRG7, "SPRG7",
6642                 SPR_NOACCESS, SPR_NOACCESS,
6643                 &spr_read_generic, &spr_write_generic,
6644                 0x00000000);
6645    spr_register(env, SPR_USPRG7, "USPRG7",
6646                 &spr_read_ureg, SPR_NOACCESS,
6647                 &spr_read_ureg, SPR_NOACCESS,
6648                 0x00000000);
6649    /* Memory management */
6650    register_low_BATs(env);
6651    register_high_BATs(env);
6652    register_74xx_soft_tlb(env, 128, 2);
6653    init_excp_7450(env);
6654    env->dcache_line_size = 32;
6655    env->icache_line_size = 32;
6656    /* Allocate hardware IRQ controller */
6657    ppc6xx_irq_init(env_archcpu(env));
6658}
6659
6660POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
6661{
6662    DeviceClass *dc = DEVICE_CLASS(oc);
6663    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6664
6665    dc->desc = "PowerPC e600";
6666    pcc->init_proc = init_proc_e600;
6667    pcc->check_pow = check_pow_hid0_74xx;
6668    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6669                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6670                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6671                       PPC_FLOAT_STFIWX |
6672                       PPC_CACHE | PPC_CACHE_ICBI |
6673                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6674                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6675                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6676                       PPC_MEM_TLBIA | PPC_74xx_TLB |
6677                       PPC_SEGMENT | PPC_EXTERN |
6678                       PPC_ALTIVEC;
6679    pcc->insns_flags2 = PPC_NONE;
6680    pcc->msr_mask = (1ull << MSR_VR) |
6681                    (1ull << MSR_POW) |
6682                    (1ull << MSR_ILE) |
6683                    (1ull << MSR_EE) |
6684                    (1ull << MSR_PR) |
6685                    (1ull << MSR_FP) |
6686                    (1ull << MSR_ME) |
6687                    (1ull << MSR_FE0) |
6688                    (1ull << MSR_SE) |
6689                    (1ull << MSR_DE) |
6690                    (1ull << MSR_FE1) |
6691                    (1ull << MSR_EP) |
6692                    (1ull << MSR_IR) |
6693                    (1ull << MSR_DR) |
6694                    (1ull << MSR_PMM) |
6695                    (1ull << MSR_RI) |
6696                    (1ull << MSR_LE);
6697    pcc->mmu_model = POWERPC_MMU_32B;
6698    pcc->excp_model = POWERPC_EXCP_74xx;
6699    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6700    pcc->bfd_mach = bfd_mach_ppc_7400;
6701    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6702                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6703                 POWERPC_FLAG_BUS_CLK;
6704}
6705
6706#if defined(TARGET_PPC64)
6707#if defined(CONFIG_USER_ONLY)
6708#define POWERPC970_HID5_INIT 0x00000080
6709#else
6710#define POWERPC970_HID5_INIT 0x00000000
6711#endif
6712
6713static int check_pow_970(CPUPPCState *env)
6714{
6715    if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
6716        return 1;
6717    }
6718
6719    return 0;
6720}
6721
6722static void register_970_hid_sprs(CPUPPCState *env)
6723{
6724    /* Hardware implementation registers */
6725    /* XXX : not implemented */
6726    spr_register(env, SPR_HID0, "HID0",
6727                 SPR_NOACCESS, SPR_NOACCESS,
6728                 &spr_read_generic, &spr_write_clear,
6729                 0x60000000);
6730    spr_register(env, SPR_HID1, "HID1",
6731                 SPR_NOACCESS, SPR_NOACCESS,
6732                 &spr_read_generic, &spr_write_generic,
6733                 0x00000000);
6734    spr_register(env, SPR_970_HID5, "HID5",
6735                 SPR_NOACCESS, SPR_NOACCESS,
6736                 &spr_read_generic, &spr_write_generic,
6737                 POWERPC970_HID5_INIT);
6738}
6739
6740static void register_970_hior_sprs(CPUPPCState *env)
6741{
6742    spr_register(env, SPR_HIOR, "SPR_HIOR",
6743                 SPR_NOACCESS, SPR_NOACCESS,
6744                 &spr_read_hior, &spr_write_hior,
6745                 0x00000000);
6746}
6747
6748static void register_book3s_ctrl_sprs(CPUPPCState *env)
6749{
6750    spr_register(env, SPR_CTRL, "SPR_CTRL",
6751                 SPR_NOACCESS, SPR_NOACCESS,
6752                 SPR_NOACCESS, &spr_write_generic,
6753                 0x00000000);
6754    spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6755                 &spr_read_ureg, SPR_NOACCESS,
6756                 &spr_read_ureg, SPR_NOACCESS,
6757                 0x00000000);
6758}
6759
6760static void register_book3s_altivec_sprs(CPUPPCState *env)
6761{
6762    if (!(env->insns_flags & PPC_ALTIVEC)) {
6763        return;
6764    }
6765
6766    spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
6767                     &spr_read_generic, &spr_write_generic,
6768                     &spr_read_generic, &spr_write_generic,
6769                     KVM_REG_PPC_VRSAVE, 0x00000000);
6770
6771}
6772
6773static void register_book3s_dbg_sprs(CPUPPCState *env)
6774{
6775    /*
6776     * TODO: different specs define different scopes for these,
6777     * will have to address this:
6778     * 970: super/write and super/read
6779     * powerisa 2.03..2.04: hypv/write and super/read.
6780     * powerisa 2.05 and newer: hypv/write and hypv/read.
6781     */
6782    spr_register_kvm(env, SPR_DABR, "DABR",
6783                     SPR_NOACCESS, SPR_NOACCESS,
6784                     &spr_read_generic, &spr_write_generic,
6785                     KVM_REG_PPC_DABR, 0x00000000);
6786    spr_register_kvm(env, SPR_DABRX, "DABRX",
6787                     SPR_NOACCESS, SPR_NOACCESS,
6788                     &spr_read_generic, &spr_write_generic,
6789                     KVM_REG_PPC_DABRX, 0x00000000);
6790}
6791
6792static void register_book3s_207_dbg_sprs(CPUPPCState *env)
6793{
6794    spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
6795                        SPR_NOACCESS, SPR_NOACCESS,
6796                        SPR_NOACCESS, SPR_NOACCESS,
6797                        &spr_read_generic, &spr_write_generic,
6798                        KVM_REG_PPC_DAWR, 0x00000000);
6799    spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
6800                        SPR_NOACCESS, SPR_NOACCESS,
6801                        SPR_NOACCESS, SPR_NOACCESS,
6802                        &spr_read_generic, &spr_write_generic,
6803                        KVM_REG_PPC_DAWRX, 0x00000000);
6804    spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
6805                        SPR_NOACCESS, SPR_NOACCESS,
6806                        SPR_NOACCESS, SPR_NOACCESS,
6807                        &spr_read_generic, &spr_write_generic,
6808                        KVM_REG_PPC_CIABR, 0x00000000);
6809}
6810
6811static void register_970_dbg_sprs(CPUPPCState *env)
6812{
6813    /* Breakpoints */
6814    spr_register(env, SPR_IABR, "IABR",
6815                 SPR_NOACCESS, SPR_NOACCESS,
6816                 &spr_read_generic, &spr_write_generic,
6817                 0x00000000);
6818}
6819
6820static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
6821{
6822    spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
6823                     SPR_NOACCESS, SPR_NOACCESS,
6824                     &spr_read_generic, &spr_write_generic,
6825                     KVM_REG_PPC_MMCR0, 0x00000000);
6826    spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
6827                     SPR_NOACCESS, SPR_NOACCESS,
6828                     &spr_read_generic, &spr_write_generic,
6829                     KVM_REG_PPC_MMCR1, 0x00000000);
6830    spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
6831                     SPR_NOACCESS, SPR_NOACCESS,
6832                     &spr_read_generic, &spr_write_generic,
6833                     KVM_REG_PPC_MMCRA, 0x00000000);
6834    spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
6835                     SPR_NOACCESS, SPR_NOACCESS,
6836                     &spr_read_generic, &spr_write_generic,
6837                     KVM_REG_PPC_PMC1, 0x00000000);
6838    spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
6839                     SPR_NOACCESS, SPR_NOACCESS,
6840                     &spr_read_generic, &spr_write_generic,
6841                     KVM_REG_PPC_PMC2, 0x00000000);
6842    spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
6843                     SPR_NOACCESS, SPR_NOACCESS,
6844                     &spr_read_generic, &spr_write_generic,
6845                     KVM_REG_PPC_PMC3, 0x00000000);
6846    spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
6847                     SPR_NOACCESS, SPR_NOACCESS,
6848                     &spr_read_generic, &spr_write_generic,
6849                     KVM_REG_PPC_PMC4, 0x00000000);
6850    spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
6851                     SPR_NOACCESS, SPR_NOACCESS,
6852                     &spr_read_generic, &spr_write_generic,
6853                     KVM_REG_PPC_PMC5, 0x00000000);
6854    spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
6855                     SPR_NOACCESS, SPR_NOACCESS,
6856                     &spr_read_generic, &spr_write_generic,
6857                     KVM_REG_PPC_PMC6, 0x00000000);
6858    spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
6859                     SPR_NOACCESS, SPR_NOACCESS,
6860                     &spr_read_generic, &spr_write_generic,
6861                     KVM_REG_PPC_SIAR, 0x00000000);
6862    spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
6863                     SPR_NOACCESS, SPR_NOACCESS,
6864                     &spr_read_generic, &spr_write_generic,
6865                     KVM_REG_PPC_SDAR, 0x00000000);
6866}
6867
6868static void register_book3s_pmu_user_sprs(CPUPPCState *env)
6869{
6870    spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
6871                 &spr_read_ureg, SPR_NOACCESS,
6872                 &spr_read_ureg, &spr_write_ureg,
6873                 0x00000000);
6874    spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
6875                 &spr_read_ureg, SPR_NOACCESS,
6876                 &spr_read_ureg, &spr_write_ureg,
6877                 0x00000000);
6878    spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
6879                 &spr_read_ureg, SPR_NOACCESS,
6880                 &spr_read_ureg, &spr_write_ureg,
6881                 0x00000000);
6882    spr_register(env, SPR_POWER_UPMC1, "UPMC1",
6883                 &spr_read_ureg, SPR_NOACCESS,
6884                 &spr_read_ureg, &spr_write_ureg,
6885                 0x00000000);
6886    spr_register(env, SPR_POWER_UPMC2, "UPMC2",
6887                 &spr_read_ureg, SPR_NOACCESS,
6888                 &spr_read_ureg, &spr_write_ureg,
6889                 0x00000000);
6890    spr_register(env, SPR_POWER_UPMC3, "UPMC3",
6891                 &spr_read_ureg, SPR_NOACCESS,
6892                 &spr_read_ureg, &spr_write_ureg,
6893                 0x00000000);
6894    spr_register(env, SPR_POWER_UPMC4, "UPMC4",
6895                 &spr_read_ureg, SPR_NOACCESS,
6896                 &spr_read_ureg, &spr_write_ureg,
6897                 0x00000000);
6898    spr_register(env, SPR_POWER_UPMC5, "UPMC5",
6899                 &spr_read_ureg, SPR_NOACCESS,
6900                 &spr_read_ureg, &spr_write_ureg,
6901                 0x00000000);
6902    spr_register(env, SPR_POWER_UPMC6, "UPMC6",
6903                 &spr_read_ureg, SPR_NOACCESS,
6904                 &spr_read_ureg, &spr_write_ureg,
6905                 0x00000000);
6906    spr_register(env, SPR_POWER_USIAR, "USIAR",
6907                 &spr_read_ureg, SPR_NOACCESS,
6908                 &spr_read_ureg, &spr_write_ureg,
6909                 0x00000000);
6910    spr_register(env, SPR_POWER_USDAR, "USDAR",
6911                 &spr_read_ureg, SPR_NOACCESS,
6912                 &spr_read_ureg, &spr_write_ureg,
6913                 0x00000000);
6914}
6915
6916static void register_970_pmu_sup_sprs(CPUPPCState *env)
6917{
6918    spr_register_kvm(env, SPR_970_PMC7, "PMC7",
6919                     SPR_NOACCESS, SPR_NOACCESS,
6920                     &spr_read_generic, &spr_write_generic,
6921                     KVM_REG_PPC_PMC7, 0x00000000);
6922    spr_register_kvm(env, SPR_970_PMC8, "PMC8",
6923                     SPR_NOACCESS, SPR_NOACCESS,
6924                     &spr_read_generic, &spr_write_generic,
6925                     KVM_REG_PPC_PMC8, 0x00000000);
6926}
6927
6928static void register_970_pmu_user_sprs(CPUPPCState *env)
6929{
6930    spr_register(env, SPR_970_UPMC7, "UPMC7",
6931                 &spr_read_ureg, SPR_NOACCESS,
6932                 &spr_read_ureg, &spr_write_ureg,
6933                 0x00000000);
6934    spr_register(env, SPR_970_UPMC8, "UPMC8",
6935                 &spr_read_ureg, SPR_NOACCESS,
6936                 &spr_read_ureg, &spr_write_ureg,
6937                 0x00000000);
6938}
6939
6940static void register_power8_pmu_sup_sprs(CPUPPCState *env)
6941{
6942    spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
6943                     SPR_NOACCESS, SPR_NOACCESS,
6944                     &spr_read_generic, &spr_write_generic,
6945                     KVM_REG_PPC_MMCR2, 0x00000000);
6946    spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
6947                     SPR_NOACCESS, SPR_NOACCESS,
6948                     &spr_read_generic, &spr_write_generic,
6949                     KVM_REG_PPC_MMCRS, 0x00000000);
6950    spr_register_kvm(env, SPR_POWER_SIER, "SIER",
6951                     SPR_NOACCESS, SPR_NOACCESS,
6952                     &spr_read_generic, &spr_write_generic,
6953                     KVM_REG_PPC_SIER, 0x00000000);
6954    spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
6955                     SPR_NOACCESS, SPR_NOACCESS,
6956                     &spr_read_generic, &spr_write_generic,
6957                     KVM_REG_PPC_SPMC1, 0x00000000);
6958    spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
6959                     SPR_NOACCESS, SPR_NOACCESS,
6960                     &spr_read_generic, &spr_write_generic,
6961                     KVM_REG_PPC_SPMC2, 0x00000000);
6962    spr_register_kvm(env, SPR_TACR, "TACR",
6963                     SPR_NOACCESS, SPR_NOACCESS,
6964                     &spr_read_generic, &spr_write_generic,
6965                     KVM_REG_PPC_TACR, 0x00000000);
6966    spr_register_kvm(env, SPR_TCSCR, "TCSCR",
6967                     SPR_NOACCESS, SPR_NOACCESS,
6968                     &spr_read_generic, &spr_write_generic,
6969                     KVM_REG_PPC_TCSCR, 0x00000000);
6970    spr_register_kvm(env, SPR_CSIGR, "CSIGR",
6971                     SPR_NOACCESS, SPR_NOACCESS,
6972                     &spr_read_generic, &spr_write_generic,
6973                     KVM_REG_PPC_CSIGR, 0x00000000);
6974}
6975
6976static void register_power8_pmu_user_sprs(CPUPPCState *env)
6977{
6978    spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
6979                 &spr_read_ureg, SPR_NOACCESS,
6980                 &spr_read_ureg, &spr_write_ureg,
6981                 0x00000000);
6982    spr_register(env, SPR_POWER_USIER, "USIER",
6983                 &spr_read_generic, SPR_NOACCESS,
6984                 &spr_read_generic, &spr_write_generic,
6985                 0x00000000);
6986}
6987
6988static void register_power5p_ear_sprs(CPUPPCState *env)
6989{
6990    /* External access control */
6991    spr_register(env, SPR_EAR, "EAR",
6992                 SPR_NOACCESS, SPR_NOACCESS,
6993                 &spr_read_generic, &spr_write_generic,
6994                 0x00000000);
6995}
6996
6997static void register_power5p_tb_sprs(CPUPPCState *env)
6998{
6999    /* TBU40 (High 40 bits of the Timebase register */
7000    spr_register_hv(env, SPR_TBU40, "TBU40",

7001                    SPR_NOACCESS, SPR_NOACCESS,
7002                    SPR_NOACCESS, SPR_NOACCESS,
7003                    SPR_NOACCESS, &spr_write_tbu40,
7004                    0x00000000);
7005}
7006
7007static void register_970_lpar_sprs(CPUPPCState *env)
7008{
7009#if !defined(CONFIG_USER_ONLY)
7010    /*
7011     * PPC970: HID4 covers things later controlled by the LPCR and
7012     * RMOR in later CPUs, but with a different encoding.  We only
7013     * support the 970 in "Apple mode" which has all hypervisor
7014     * facilities disabled by strapping, so we can basically just
7015     * ignore it
7016     */
7017    spr_register(env, SPR_970_HID4, "HID4",
7018                 SPR_NOACCESS, SPR_NOACCESS,
7019                 &spr_read_generic, &spr_write_generic,
7020                 0x00000000);
7021#endif
7022}
7023
7024static void register_power5p_lpar_sprs(CPUPPCState *env)
7025{
7026#if !defined(CONFIG_USER_ONLY)
7027    /* Logical partitionning */
7028    spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7029                        SPR_NOACCESS, SPR_NOACCESS,
7030                        SPR_NOACCESS, SPR_NOACCESS,
7031                        &spr_read_generic, &spr_write_lpcr,
7032                        KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
7033    spr_register_hv(env, SPR_HDEC, "HDEC",
7034                    SPR_NOACCESS, SPR_NOACCESS,
7035                    SPR_NOACCESS, SPR_NOACCESS,
7036                    &spr_read_hdecr, &spr_write_hdecr, 0);
7037#endif
7038}
7039
7040static void register_book3s_ids_sprs(CPUPPCState *env)
7041{
7042    /* FIXME: Will need to deal with thread vs core only SPRs */
7043
7044    /* Processor identification */
7045    spr_register_hv(env, SPR_PIR, "PIR",
7046                 SPR_NOACCESS, SPR_NOACCESS,
7047                 &spr_read_generic, SPR_NOACCESS,
7048                 &spr_read_generic, NULL,
7049                 0x00000000);
7050    spr_register_hv(env, SPR_HID0, "HID0",
7051                 SPR_NOACCESS, SPR_NOACCESS,
7052                 SPR_NOACCESS, SPR_NOACCESS,
7053                 &spr_read_generic, &spr_write_generic,
7054                 0x00000000);
7055    spr_register_hv(env, SPR_TSCR, "TSCR",
7056                 SPR_NOACCESS, SPR_NOACCESS,
7057                 SPR_NOACCESS, SPR_NOACCESS,
7058                 &spr_read_generic, &spr_write_generic,
7059                 0x00000000);
7060    spr_register_hv(env, SPR_HMER, "HMER",
7061                 SPR_NOACCESS, SPR_NOACCESS,
7062                 SPR_NOACCESS, SPR_NOACCESS,
7063                 &spr_read_generic, &spr_write_hmer,
7064                 0x00000000);
7065    spr_register_hv(env, SPR_HMEER, "HMEER",
7066                 SPR_NOACCESS, SPR_NOACCESS,
7067                 SPR_NOACCESS, SPR_NOACCESS,
7068                 &spr_read_generic, &spr_write_generic,
7069                 0x00000000);
7070    spr_register_hv(env, SPR_TFMR, "TFMR",
7071                 SPR_NOACCESS, SPR_NOACCESS,
7072                 SPR_NOACCESS, SPR_NOACCESS,
7073                 &spr_read_generic, &spr_write_generic,
7074                 0x00000000);
7075    spr_register_hv(env, SPR_LPIDR, "LPIDR",
7076                 SPR_NOACCESS, SPR_NOACCESS,
7077                 SPR_NOACCESS, SPR_NOACCESS,
7078                 &spr_read_generic, &spr_write_lpidr,
7079                 0x00000000);
7080    spr_register_hv(env, SPR_HFSCR, "HFSCR",
7081                 SPR_NOACCESS, SPR_NOACCESS,
7082                 SPR_NOACCESS, SPR_NOACCESS,
7083                 &spr_read_generic, &spr_write_generic,
7084                 0x00000000);
7085    spr_register_hv(env, SPR_MMCRC, "MMCRC",
7086                 SPR_NOACCESS, SPR_NOACCESS,
7087                 SPR_NOACCESS, SPR_NOACCESS,
7088                 &spr_read_generic, &spr_write_generic,
7089                 0x00000000);
7090    spr_register_hv(env, SPR_MMCRH, "MMCRH",
7091                 SPR_NOACCESS, SPR_NOACCESS,
7092                 SPR_NOACCESS, SPR_NOACCESS,
7093                 &spr_read_generic, &spr_write_generic,
7094                 0x00000000);
7095    spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7096                 SPR_NOACCESS, SPR_NOACCESS,
7097                 SPR_NOACCESS, SPR_NOACCESS,
7098                 &spr_read_generic, &spr_write_generic,
7099                 0x00000000);
7100    spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7101                 SPR_NOACCESS, SPR_NOACCESS,
7102                 SPR_NOACCESS, SPR_NOACCESS,
7103                 &spr_read_generic, &spr_write_generic,
7104                 0x00000000);
7105    spr_register_hv(env, SPR_HSRR0, "HSRR0",
7106                 SPR_NOACCESS, SPR_NOACCESS,
7107                 SPR_NOACCESS, SPR_NOACCESS,
7108                 &spr_read_generic, &spr_write_generic,
7109                 0x00000000);
7110    spr_register_hv(env, SPR_HSRR1, "HSRR1",
7111                 SPR_NOACCESS, SPR_NOACCESS,
7112                 SPR_NOACCESS, SPR_NOACCESS,
7113                 &spr_read_generic, &spr_write_generic,
7114                 0x00000000);
7115    spr_register_hv(env, SPR_HDAR, "HDAR",
7116                 SPR_NOACCESS, SPR_NOACCESS,
7117                 SPR_NOACCESS, SPR_NOACCESS,
7118                 &spr_read_generic, &spr_write_generic,
7119                 0x00000000);
7120    spr_register_hv(env, SPR_HDSISR, "HDSISR",
7121                 SPR_NOACCESS, SPR_NOACCESS,
7122                 SPR_NOACCESS, SPR_NOACCESS,
7123                 &spr_read_generic, &spr_write_generic,
7124                 0x00000000);
7125    spr_register_hv(env, SPR_HRMOR, "HRMOR",
7126                 SPR_NOACCESS, SPR_NOACCESS,
7127                 SPR_NOACCESS, SPR_NOACCESS,
7128                 &spr_read_generic, &spr_write_generic,
7129                 0x00000000);
7130}
7131
7132static void register_rmor_sprs(CPUPPCState *env)
7133{
7134    spr_register_hv(env, SPR_RMOR, "RMOR",
7135                 SPR_NOACCESS, SPR_NOACCESS,
7136                 SPR_NOACCESS, SPR_NOACCESS,
7137                 &spr_read_generic, &spr_write_generic,
7138                 0x00000000);
7139}
7140
7141static void register_power8_ids_sprs(CPUPPCState *env)
7142{
7143    /* Thread identification */
7144    spr_register(env, SPR_TIR, "TIR",
7145                 SPR_NOACCESS, SPR_NOACCESS,
7146                 &spr_read_generic, SPR_NOACCESS,
7147                 0x00000000);
7148}
7149
7150static void register_book3s_purr_sprs(CPUPPCState *env)
7151{
7152#if !defined(CONFIG_USER_ONLY)
7153    /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7154    spr_register_kvm_hv(env, SPR_PURR,   "PURR",
7155                        &spr_read_purr, SPR_NOACCESS,
7156                        &spr_read_purr, SPR_NOACCESS,
7157                        &spr_read_purr, &spr_write_purr,
7158                        KVM_REG_PPC_PURR, 0x00000000);
7159    spr_register_kvm_hv(env, SPR_SPURR,   "SPURR",
7160                        &spr_read_purr, SPR_NOACCESS,
7161                        &spr_read_purr, SPR_NOACCESS,
7162                        &spr_read_purr, &spr_write_purr,
7163                        KVM_REG_PPC_SPURR, 0x00000000);
7164#endif
7165}
7166
7167static void register_power6_dbg_sprs(CPUPPCState *env)
7168{
7169#if !defined(CONFIG_USER_ONLY)
7170    spr_register(env, SPR_CFAR, "SPR_CFAR",
7171                 SPR_NOACCESS, SPR_NOACCESS,
7172                 &spr_read_cfar, &spr_write_cfar,
7173                 0x00000000);
7174#endif
7175}
7176
7177static void register_power5p_common_sprs(CPUPPCState *env)
7178{
7179    spr_register_kvm(env, SPR_PPR, "PPR",
7180                     &spr_read_generic, &spr_write_generic,
7181                     &spr_read_generic, &spr_write_generic,
7182                     KVM_REG_PPC_PPR, 0x00000000);
7183}
7184
7185static void register_power6_common_sprs(CPUPPCState *env)
7186{
7187#if !defined(CONFIG_USER_ONLY)
7188    spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7189                     SPR_NOACCESS, SPR_NOACCESS,
7190                     &spr_read_generic, &spr_write_generic,
7191                     KVM_REG_PPC_DSCR, 0x00000000);
7192#endif
7193    /*
7194     * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7195     * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
7196     */
7197    spr_register_hv(env, SPR_PCR, "PCR",
7198                 SPR_NOACCESS, SPR_NOACCESS,
7199                 SPR_NOACCESS, SPR_NOACCESS,
7200                 &spr_read_generic, &spr_write_pcr,
7201                 0x00000000);
7202}
7203
7204static void register_power8_tce_address_control_sprs(CPUPPCState *env)
7205{
7206    spr_register_kvm(env, SPR_TAR, "TAR",
7207                     &spr_read_tar, &spr_write_tar,
7208                     &spr_read_generic, &spr_write_generic,
7209                     KVM_REG_PPC_TAR, 0x00000000);
7210}
7211
7212static void register_power8_tm_sprs(CPUPPCState *env)
7213{
7214    spr_register_kvm(env, SPR_TFHAR, "TFHAR",
7215                     &spr_read_tm, &spr_write_tm,
7216                     &spr_read_tm, &spr_write_tm,
7217                     KVM_REG_PPC_TFHAR, 0x00000000);
7218    spr_register_kvm(env, SPR_TFIAR, "TFIAR",
7219                     &spr_read_tm, &spr_write_tm,
7220                     &spr_read_tm, &spr_write_tm,
7221                     KVM_REG_PPC_TFIAR, 0x00000000);
7222    spr_register_kvm(env, SPR_TEXASR, "TEXASR",
7223                     &spr_read_tm, &spr_write_tm,
7224                     &spr_read_tm, &spr_write_tm,
7225                     KVM_REG_PPC_TEXASR, 0x00000000);
7226    spr_register(env, SPR_TEXASRU, "TEXASRU",
7227                 &spr_read_tm_upper32, &spr_write_tm_upper32,
7228                 &spr_read_tm_upper32, &spr_write_tm_upper32,
7229                 0x00000000);
7230}
7231
7232static void register_power8_ebb_sprs(CPUPPCState *env)
7233{
7234    spr_register(env, SPR_BESCRS, "BESCRS",
7235                 &spr_read_ebb, &spr_write_ebb,
7236                 &spr_read_generic, &spr_write_generic,
7237                 0x00000000);
7238    spr_register(env, SPR_BESCRSU, "BESCRSU",
7239                 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7240                 &spr_read_prev_upper32, &spr_write_prev_upper32,
7241                 0x00000000);
7242    spr_register(env, SPR_BESCRR, "BESCRR",
7243                 &spr_read_ebb, &spr_write_ebb,
7244                 &spr_read_generic, &spr_write_generic,
7245                 0x00000000);
7246    spr_register(env, SPR_BESCRRU, "BESCRRU",
7247                 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7248                 &spr_read_prev_upper32, &spr_write_prev_upper32,
7249                 0x00000000);
7250    spr_register_kvm(env, SPR_EBBHR, "EBBHR",
7251                     &spr_read_ebb, &spr_write_ebb,
7252                     &spr_read_generic, &spr_write_generic,
7253                     KVM_REG_PPC_EBBHR, 0x00000000);
7254    spr_register_kvm(env, SPR_EBBRR, "EBBRR",
7255                     &spr_read_ebb, &spr_write_ebb,
7256                     &spr_read_generic, &spr_write_generic,
7257                     KVM_REG_PPC_EBBRR, 0x00000000);
7258    spr_register_kvm(env, SPR_BESCR, "BESCR",
7259                     &spr_read_ebb, &spr_write_ebb,
7260                     &spr_read_generic, &spr_write_generic,
7261                     KVM_REG_PPC_BESCR, 0x00000000);
7262}
7263
7264/* Virtual Time Base */
7265static void register_vtb_sprs(CPUPPCState *env)
7266{
7267    spr_register_kvm_hv(env, SPR_VTB, "VTB",
7268                        SPR_NOACCESS, SPR_NOACCESS,
7269                        &spr_read_vtb, SPR_NOACCESS,
7270                        &spr_read_vtb, &spr_write_vtb,
7271                        KVM_REG_PPC_VTB, 0x00000000);
7272}
7273
7274static void register_power8_fscr_sprs(CPUPPCState *env)
7275{
7276#if defined(CONFIG_USER_ONLY)
7277    target_ulong initval = 1ULL << FSCR_TAR;
7278#else
7279    target_ulong initval = 0;
7280#endif
7281    spr_register_kvm(env, SPR_FSCR, "FSCR",
7282                     SPR_NOACCESS, SPR_NOACCESS,
7283                     &spr_read_generic, &spr_write_generic,
7284                     KVM_REG_PPC_FSCR, initval);
7285}
7286
7287static void register_power8_pspb_sprs(CPUPPCState *env)
7288{
7289    spr_register_kvm(env, SPR_PSPB, "PSPB",
7290                     SPR_NOACCESS, SPR_NOACCESS,
7291                     &spr_read_generic, &spr_write_generic32,
7292                     KVM_REG_PPC_PSPB, 0);
7293}
7294
7295static void register_power8_dpdes_sprs(CPUPPCState *env)
7296{
7297#if !defined(CONFIG_USER_ONLY)
7298    /* Directed Privileged Door-bell Exception State, used for IPI */
7299    spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
7300                        SPR_NOACCESS, SPR_NOACCESS,
7301                        &spr_read_dpdes, SPR_NOACCESS,
7302                        &spr_read_dpdes, &spr_write_dpdes,
7303                        KVM_REG_PPC_DPDES, 0x00000000);
7304#endif
7305}
7306
7307static void register_power8_ic_sprs(CPUPPCState *env)
7308{
7309#if !defined(CONFIG_USER_ONLY)
7310    spr_register_hv(env, SPR_IC, "IC",
7311                    SPR_NOACCESS, SPR_NOACCESS,
7312                    &spr_read_generic, SPR_NOACCESS,
7313                    &spr_read_generic, &spr_write_generic,
7314                    0);
7315#endif
7316}
7317
7318static void register_power8_book4_sprs(CPUPPCState *env)
7319{
7320    /* Add a number of P8 book4 registers */
7321#if !defined(CONFIG_USER_ONLY)
7322    spr_register_kvm(env, SPR_ACOP, "ACOP",
7323                     SPR_NOACCESS, SPR_NOACCESS,
7324                     &spr_read_generic, &spr_write_generic,
7325                     KVM_REG_PPC_ACOP, 0);
7326    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
7327                     SPR_NOACCESS, SPR_NOACCESS,
7328                     &spr_read_generic, &spr_write_pidr,
7329                     KVM_REG_PPC_PID, 0);
7330    spr_register_kvm(env, SPR_WORT, "WORT",
7331                     SPR_NOACCESS, SPR_NOACCESS,
7332                     &spr_read_generic, &spr_write_generic,
7333                     KVM_REG_PPC_WORT, 0);
7334#endif
7335}
7336
7337static void register_power7_book4_sprs(CPUPPCState *env)
7338{
7339    /* Add a number of P7 book4 registers */
7340#if !defined(CONFIG_USER_ONLY)
7341    spr_register_kvm(env, SPR_ACOP, "ACOP",
7342                     SPR_NOACCESS, SPR_NOACCESS,
7343                     &spr_read_generic, &spr_write_generic,
7344                     KVM_REG_PPC_ACOP, 0);
7345    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
7346                     SPR_NOACCESS, SPR_NOACCESS,
7347                     &spr_read_generic, &spr_write_generic,
7348                     KVM_REG_PPC_PID, 0);
7349#endif
7350}
7351
7352static void register_power8_rpr_sprs(CPUPPCState *env)
7353{
7354#if !defined(CONFIG_USER_ONLY)
7355    spr_register_hv(env, SPR_RPR, "RPR",
7356                    SPR_NOACCESS, SPR_NOACCESS,
7357                    SPR_NOACCESS, SPR_NOACCESS,
7358                    &spr_read_generic, &spr_write_generic,
7359                    0x00000103070F1F3F);
7360#endif
7361}
7362
7363static void register_power9_mmu_sprs(CPUPPCState *env)
7364{
7365#if !defined(CONFIG_USER_ONLY)
7366    /* Partition Table Control */
7367    spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
7368                        SPR_NOACCESS, SPR_NOACCESS,
7369                        SPR_NOACCESS, SPR_NOACCESS,
7370                        &spr_read_generic, &spr_write_ptcr,
7371                        KVM_REG_PPC_PTCR, 0x00000000);
7372    /* Address Segment Descriptor Register */
7373    spr_register_hv(env, SPR_ASDR, "ASDR",
7374                    SPR_NOACCESS, SPR_NOACCESS,
7375                    SPR_NOACCESS, SPR_NOACCESS,
7376                    &spr_read_generic, &spr_write_generic,
7377                    0x0000000000000000);
7378#endif
7379}
7380
7381static void init_proc_book3s_common(CPUPPCState *env)
7382{
7383    register_ne_601_sprs(env);
7384    register_tbl(env);
7385    register_usprg3_sprs(env);
7386    register_book3s_altivec_sprs(env);
7387    register_book3s_pmu_sup_sprs(env);
7388    register_book3s_pmu_user_sprs(env);
7389    register_book3s_ctrl_sprs(env);
7390    /*
7391     * Can't find information on what this should be on reset.  This
7392     * value is the one used by 74xx processors.
7393     */
7394    vscr_init(env, 0x00010000);
7395}
7396
7397static void init_proc_970(CPUPPCState *env)
7398{
7399    /* Common Registers */
7400    init_proc_book3s_common(env);
7401    register_sdr1_sprs(env);
7402    register_book3s_dbg_sprs(env);
7403
7404    /* 970 Specific Registers */
7405    register_970_hid_sprs(env);
7406    register_970_hior_sprs(env);
7407    register_low_BATs(env);
7408    register_970_pmu_sup_sprs(env);
7409    register_970_pmu_user_sprs(env);
7410    register_970_lpar_sprs(env);
7411    register_970_dbg_sprs(env);
7412
7413    /* env variables */
7414    env->dcache_line_size = 128;
7415    env->icache_line_size = 128;
7416
7417    /* Allocate hardware IRQ controller */
7418    init_excp_970(env);
7419    ppc970_irq_init(env_archcpu(env));
7420}
7421
7422POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7423{
7424    DeviceClass *dc = DEVICE_CLASS(oc);
7425    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7426
7427    dc->desc = "PowerPC 970";
7428    pcc->init_proc = init_proc_970;
7429    pcc->check_pow = check_pow_970;
7430    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7431                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7432                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7433                       PPC_FLOAT_STFIWX |
7434                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7435                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7436                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7437                       PPC_64B | PPC_ALTIVEC |
7438                       PPC_SEGMENT_64B | PPC_SLBI;
7439    pcc->insns_flags2 = PPC2_FP_CVT_S64;
7440    pcc->msr_mask = (1ull << MSR_SF) |
7441                    (1ull << MSR_VR) |
7442                    (1ull << MSR_POW) |
7443                    (1ull << MSR_EE) |
7444                    (1ull << MSR_PR) |
7445                    (1ull << MSR_FP) |
7446                    (1ull << MSR_ME) |
7447                    (1ull << MSR_FE0) |
7448                    (1ull << MSR_SE) |
7449                    (1ull << MSR_DE) |
7450                    (1ull << MSR_FE1) |
7451                    (1ull << MSR_IR) |
7452                    (1ull << MSR_DR) |
7453                    (1ull << MSR_PMM) |
7454                    (1ull << MSR_RI);
7455    pcc->mmu_model = POWERPC_MMU_64B;
7456#if defined(CONFIG_SOFTMMU)
7457    pcc->hash64_opts = &ppc_hash64_opts_basic;
7458#endif
7459    pcc->excp_model = POWERPC_EXCP_970;
7460    pcc->bus_model = PPC_FLAGS_INPUT_970;
7461    pcc->bfd_mach = bfd_mach_ppc64;
7462    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7463                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7464                 POWERPC_FLAG_BUS_CLK;
7465    pcc->l1_dcache_size = 0x8000;
7466    pcc->l1_icache_size = 0x10000;
7467}
7468
7469static void init_proc_power5plus(CPUPPCState *env)
7470{
7471    /* Common Registers */
7472    init_proc_book3s_common(env);
7473    register_sdr1_sprs(env);
7474    register_book3s_dbg_sprs(env);
7475
7476    /* POWER5+ Specific Registers */
7477    register_970_hid_sprs(env);
7478    register_970_hior_sprs(env);
7479    register_low_BATs(env);
7480    register_970_pmu_sup_sprs(env);
7481    register_970_pmu_user_sprs(env);
7482    register_power5p_common_sprs(env);
7483    register_power5p_lpar_sprs(env);
7484    register_power5p_ear_sprs(env);
7485    register_power5p_tb_sprs(env);
7486
7487    /* env variables */
7488    env->dcache_line_size = 128;
7489    env->icache_line_size = 128;
7490
7491    /* Allocate hardware IRQ controller */
7492    init_excp_970(env);
7493    ppc970_irq_init(env_archcpu(env));
7494}
7495
7496POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
7497{
7498    DeviceClass *dc = DEVICE_CLASS(oc);
7499    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7500
7501    dc->fw_name = "PowerPC,POWER5";
7502    dc->desc = "POWER5+";
7503    pcc->init_proc = init_proc_power5plus;
7504    pcc->check_pow = check_pow_970;
7505    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7506                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7507                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7508                       PPC_FLOAT_STFIWX |
7509                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7510                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7511                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7512                       PPC_64B |
7513                       PPC_SEGMENT_64B | PPC_SLBI;
7514    pcc->insns_flags2 = PPC2_FP_CVT_S64;
7515    pcc->msr_mask = (1ull << MSR_SF) |
7516                    (1ull << MSR_VR) |
7517                    (1ull << MSR_POW) |
7518                    (1ull << MSR_EE) |
7519                    (1ull << MSR_PR) |
7520                    (1ull << MSR_FP) |
7521                    (1ull << MSR_ME) |
7522                    (1ull << MSR_FE0) |
7523                    (1ull << MSR_SE) |
7524                    (1ull << MSR_DE) |
7525                    (1ull << MSR_FE1) |
7526                    (1ull << MSR_IR) |
7527                    (1ull << MSR_DR) |
7528                    (1ull << MSR_PMM) |
7529                    (1ull << MSR_RI);
7530    pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
7531        LPCR_RMI | LPCR_HDICE;
7532    pcc->mmu_model = POWERPC_MMU_2_03;
7533#if defined(CONFIG_SOFTMMU)
7534    pcc->hash64_opts = &ppc_hash64_opts_basic;
7535    pcc->lrg_decr_bits = 32;
7536#endif
7537    pcc->excp_model = POWERPC_EXCP_970;
7538    pcc->bus_model = PPC_FLAGS_INPUT_970;
7539    pcc->bfd_mach = bfd_mach_ppc64;
7540    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7541                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7542                 POWERPC_FLAG_BUS_CLK;
7543    pcc->l1_dcache_size = 0x8000;
7544    pcc->l1_icache_size = 0x10000;
7545}
7546
7547static void init_proc_POWER7(CPUPPCState *env)
7548{
7549    /* Common Registers */
7550    init_proc_book3s_common(env);
7551    register_sdr1_sprs(env);
7552    register_book3s_dbg_sprs(env);
7553
7554    /* POWER7 Specific Registers */
7555    register_book3s_ids_sprs(env);
7556    register_rmor_sprs(env);
7557    register_amr_sprs(env);
7558    register_book3s_purr_sprs(env);
7559    register_power5p_common_sprs(env);
7560    register_power5p_lpar_sprs(env);
7561    register_power5p_ear_sprs(env);
7562    register_power5p_tb_sprs(env);
7563    register_power6_common_sprs(env);
7564    register_power6_dbg_sprs(env);
7565    register_power7_book4_sprs(env);
7566
7567    /* env variables */
7568    env->dcache_line_size = 128;
7569    env->icache_line_size = 128;
7570
7571    /* Allocate hardware IRQ controller */
7572    init_excp_POWER7(env);
7573    ppcPOWER7_irq_init(env_archcpu(env));
7574}
7575
7576static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
7577{
7578    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
7579        return true;
7580    }
7581    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
7582        return true;
7583    }
7584    return false;
7585}
7586
7587static bool cpu_has_work_POWER7(CPUState *cs)
7588{
7589    PowerPCCPU *cpu = POWERPC_CPU(cs);
7590    CPUPPCState *env = &cpu->env;
7591
7592    if (cs->halted) {
7593        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7594            return false;
7595        }
7596        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7597            (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
7598            return true;
7599        }
7600        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7601            (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
7602            return true;
7603        }
7604        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7605            (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7606            return true;
7607        }
7608        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7609            (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7610            return true;
7611        }
7612        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7613            return true;
7614        }
7615        return false;
7616    } else {
7617        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7618    }
7619}
7620
7621POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7622{
7623    DeviceClass *dc = DEVICE_CLASS(oc);
7624    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7625    CPUClass *cc = CPU_CLASS(oc);
7626
7627    dc->fw_name = "PowerPC,POWER7";
7628    dc->desc = "POWER7";
7629    pcc->pvr_match = ppc_pvr_match_power7;
7630    pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
7631    pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7632    pcc->init_proc = init_proc_POWER7;
7633    pcc->check_pow = check_pow_nocheck;
7634    cc->has_work = cpu_has_work_POWER7;
7635    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7636                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7637                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7638                       PPC_FLOAT_FRSQRTES |
7639                       PPC_FLOAT_STFIWX |
7640                       PPC_FLOAT_EXT |
7641                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7642                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7643                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7644                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7645                       PPC_SEGMENT_64B | PPC_SLBI |
7646                       PPC_POPCNTB | PPC_POPCNTWD |
7647                       PPC_CILDST;
7648    pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7649                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7650                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7651                        PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
7652                        PPC2_PM_ISA206;
7653    pcc->msr_mask = (1ull << MSR_SF) |
7654                    (1ull << MSR_VR) |
7655                    (1ull << MSR_VSX) |
7656                    (1ull << MSR_EE) |
7657                    (1ull << MSR_PR) |
7658                    (1ull << MSR_FP) |
7659                    (1ull << MSR_ME) |
7660                    (1ull << MSR_FE0) |
7661                    (1ull << MSR_SE) |
7662                    (1ull << MSR_DE) |
7663                    (1ull << MSR_FE1) |
7664                    (1ull << MSR_IR) |
7665                    (1ull << MSR_DR) |
7666                    (1ull << MSR_PMM) |
7667                    (1ull << MSR_RI) |
7668                    (1ull << MSR_LE);
7669    pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
7670        LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7671        LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
7672        LPCR_MER | LPCR_TC |
7673        LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
7674    pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
7675    pcc->mmu_model = POWERPC_MMU_2_06;
7676#if defined(CONFIG_SOFTMMU)
7677    pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7678    pcc->lrg_decr_bits = 32;
7679#endif
7680    pcc->excp_model = POWERPC_EXCP_POWER7;
7681    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7682    pcc->bfd_mach = bfd_mach_ppc64;
7683    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7684                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7685                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7686                 POWERPC_FLAG_VSX;
7687    pcc->l1_dcache_size = 0x8000;
7688    pcc->l1_icache_size = 0x8000;
7689}
7690
7691static void init_proc_POWER8(CPUPPCState *env)
7692{
7693    /* Common Registers */
7694    init_proc_book3s_common(env);
7695    register_sdr1_sprs(env);
7696    register_book3s_207_dbg_sprs(env);
7697
7698    /* POWER8 Specific Registers */
7699    register_book3s_ids_sprs(env);
7700    register_rmor_sprs(env);
7701    register_amr_sprs(env);
7702    register_iamr_sprs(env);
7703    register_book3s_purr_sprs(env);
7704    register_power5p_common_sprs(env);
7705    register_power5p_lpar_sprs(env);
7706    register_power5p_ear_sprs(env);
7707    register_power5p_tb_sprs(env);
7708    register_power6_common_sprs(env);
7709    register_power6_dbg_sprs(env);
7710    register_power8_tce_address_control_sprs(env);
7711    register_power8_ids_sprs(env);
7712    register_power8_ebb_sprs(env);
7713    register_power8_fscr_sprs(env);
7714    register_power8_pmu_sup_sprs(env);
7715    register_power8_pmu_user_sprs(env);
7716    register_power8_tm_sprs(env);
7717    register_power8_pspb_sprs(env);
7718    register_power8_dpdes_sprs(env);
7719    register_vtb_sprs(env);
7720    register_power8_ic_sprs(env);
7721    register_power8_book4_sprs(env);
7722    register_power8_rpr_sprs(env);
7723
7724    /* env variables */
7725    env->dcache_line_size = 128;
7726    env->icache_line_size = 128;
7727
7728    /* Allocate hardware IRQ controller */
7729    init_excp_POWER8(env);
7730    ppcPOWER7_irq_init(env_archcpu(env));
7731}
7732
7733static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
7734{
7735    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
7736        return true;
7737    }
7738    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
7739        return true;
7740    }
7741    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
7742        return true;
7743    }
7744    return false;
7745}
7746
7747static bool cpu_has_work_POWER8(CPUState *cs)
7748{
7749    PowerPCCPU *cpu = POWERPC_CPU(cs);
7750    CPUPPCState *env = &cpu->env;
7751
7752    if (cs->halted) {
7753        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7754            return false;
7755        }
7756        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7757            (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
7758            return true;
7759        }
7760        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7761            (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
7762            return true;
7763        }
7764        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7765            (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7766            return true;
7767        }
7768        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7769            (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7770            return true;
7771        }
7772        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7773            (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
7774            return true;
7775        }
7776        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7777            (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
7778            return true;
7779        }
7780        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7781            return true;
7782        }
7783        return false;
7784    } else {
7785        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7786    }
7787}
7788
7789POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7790{
7791    DeviceClass *dc = DEVICE_CLASS(oc);
7792    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7793    CPUClass *cc = CPU_CLASS(oc);
7794
7795    dc->fw_name = "PowerPC,POWER8";
7796    dc->desc = "POWER8";
7797    pcc->pvr_match = ppc_pvr_match_power8;
7798    pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7799    pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7800    pcc->init_proc = init_proc_POWER8;
7801    pcc->check_pow = check_pow_nocheck;
7802    cc->has_work = cpu_has_work_POWER8;
7803    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7804                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7805                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7806                       PPC_FLOAT_FRSQRTES |
7807                       PPC_FLOAT_STFIWX |
7808                       PPC_FLOAT_EXT |
7809                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7810                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7811                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7812                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7813                       PPC_SEGMENT_64B | PPC_SLBI |
7814                       PPC_POPCNTB | PPC_POPCNTWD |
7815                       PPC_CILDST;
7816    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7817                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7818                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7819                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7820                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7821                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7822                        PPC2_TM | PPC2_PM_ISA206;
7823    pcc->msr_mask = (1ull << MSR_SF) |
7824                    (1ull << MSR_HV) |
7825                    (1ull << MSR_TM) |
7826                    (1ull << MSR_VR) |
7827                    (1ull << MSR_VSX) |
7828                    (1ull << MSR_EE) |
7829                    (1ull << MSR_PR) |
7830                    (1ull << MSR_FP) |
7831                    (1ull << MSR_ME) |
7832                    (1ull << MSR_FE0) |
7833                    (1ull << MSR_SE) |
7834                    (1ull << MSR_DE) |
7835                    (1ull << MSR_FE1) |
7836                    (1ull << MSR_IR) |
7837                    (1ull << MSR_DR) |
7838                    (1ull << MSR_PMM) |
7839                    (1ull << MSR_RI) |
7840                    (1ull << MSR_TS0) |
7841                    (1ull << MSR_TS1) |
7842                    (1ull << MSR_LE);
7843    pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
7844        LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7845        LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
7846        LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
7847        LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
7848    pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
7849                   LPCR_P8_PECE3 | LPCR_P8_PECE4;
7850    pcc->mmu_model = POWERPC_MMU_2_07;
7851#if defined(CONFIG_SOFTMMU)
7852    pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7853    pcc->lrg_decr_bits = 32;
7854    pcc->n_host_threads = 8;
7855#endif
7856    pcc->excp_model = POWERPC_EXCP_POWER8;
7857    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7858    pcc->bfd_mach = bfd_mach_ppc64;
7859    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7860                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7861                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7862                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
7863    pcc->l1_dcache_size = 0x8000;
7864    pcc->l1_icache_size = 0x8000;
7865}
7866
7867#ifdef CONFIG_SOFTMMU
7868/*
7869 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
7870 * Encoded as array of int_32s in the form:
7871 *  0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
7872 *  x -> AP encoding
7873 *  y -> radix mode supported page size (encoded as a shift)
7874 */
7875static struct ppc_radix_page_info POWER9_radix_page_info = {
7876    .count = 4,
7877    .entries = {
7878        0x0000000c, /*  4K - enc: 0x0 */
7879        0xa0000010, /* 64K - enc: 0x5 */
7880        0x20000015, /*  2M - enc: 0x1 */
7881        0x4000001e  /*  1G - enc: 0x2 */
7882    }
7883};
7884#endif /* CONFIG_SOFTMMU */
7885
7886static void init_proc_POWER9(CPUPPCState *env)
7887{
7888    /* Common Registers */
7889    init_proc_book3s_common(env);
7890    register_book3s_207_dbg_sprs(env);
7891
7892    /* POWER8 Specific Registers */
7893    register_book3s_ids_sprs(env);
7894    register_amr_sprs(env);
7895    register_iamr_sprs(env);
7896    register_book3s_purr_sprs(env);
7897    register_power5p_common_sprs(env);
7898    register_power5p_lpar_sprs(env);
7899    register_power5p_ear_sprs(env);
7900    register_power5p_tb_sprs(env);
7901    register_power6_common_sprs(env);
7902    register_power6_dbg_sprs(env);
7903    register_power8_tce_address_control_sprs(env);
7904    register_power8_ids_sprs(env);
7905    register_power8_ebb_sprs(env);
7906    register_power8_fscr_sprs(env);
7907    register_power8_pmu_sup_sprs(env);
7908    register_power8_pmu_user_sprs(env);
7909    register_power8_tm_sprs(env);
7910    register_power8_pspb_sprs(env);
7911    register_power8_dpdes_sprs(env);
7912    register_vtb_sprs(env);
7913    register_power8_ic_sprs(env);
7914    register_power8_book4_sprs(env);
7915    register_power8_rpr_sprs(env);
7916    register_power9_mmu_sprs(env);
7917
7918    /* POWER9 Specific registers */
7919    spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
7920                     spr_read_generic, spr_write_generic,
7921                     KVM_REG_PPC_TIDR, 0);
7922
7923    /* FIXME: Filter fields properly based on privilege level */
7924    spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
7925                        spr_read_generic, spr_write_generic,
7926                        KVM_REG_PPC_PSSCR, 0);
7927
7928    /* env variables */
7929    env->dcache_line_size = 128;
7930    env->icache_line_size = 128;
7931
7932    /* Allocate hardware IRQ controller */
7933    init_excp_POWER9(env);
7934    ppcPOWER9_irq_init(env_archcpu(env));
7935}
7936
7937static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
7938{
7939    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
7940        return true;
7941    }
7942    return false;
7943}
7944
7945static bool cpu_has_work_POWER9(CPUState *cs)
7946{
7947    PowerPCCPU *cpu = POWERPC_CPU(cs);
7948    CPUPPCState *env = &cpu->env;
7949
7950    if (cs->halted) {
7951        uint64_t psscr = env->spr[SPR_PSSCR];
7952
7953        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7954            return false;
7955        }
7956
7957        /* If EC is clear, just return true on any pending interrupt */
7958        if (!(psscr & PSSCR_EC)) {
7959            return true;
7960        }
7961        /* External Exception */
7962        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7963            (env->spr[SPR_LPCR] & LPCR_EEE)) {
7964            bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
7965            if (heic == 0 || !msr_hv || msr_pr) {
7966                return true;
7967            }
7968        }
7969        /* Decrementer Exception */
7970        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7971            (env->spr[SPR_LPCR] & LPCR_DEE)) {
7972            return true;
7973        }
7974        /* Machine Check or Hypervisor Maintenance Exception */
7975        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
7976            1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
7977            return true;
7978        }
7979        /* Privileged Doorbell Exception */
7980        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7981            (env->spr[SPR_LPCR] & LPCR_PDEE)) {
7982            return true;
7983        }
7984        /* Hypervisor Doorbell Exception */
7985        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7986            (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7987            return true;
7988        }
7989        /* Hypervisor virtualization exception */
7990        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7991            (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7992            return true;
7993        }
7994        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7995            return true;
7996        }
7997        return false;
7998    } else {
7999        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8000    }

8001}
8002
8003POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8004{
8005    DeviceClass *dc = DEVICE_CLASS(oc);
8006    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8007    CPUClass *cc = CPU_CLASS(oc);
8008
8009    dc->fw_name = "PowerPC,POWER9";
8010    dc->desc = "POWER9";
8011    pcc->pvr_match = ppc_pvr_match_power9;
8012    pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
8013    pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8014                         PCR_COMPAT_2_05;
8015    pcc->init_proc = init_proc_POWER9;
8016    pcc->check_pow = check_pow_nocheck;
8017    cc->has_work = cpu_has_work_POWER9;
8018    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8019                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8020                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8021                       PPC_FLOAT_FRSQRTES |
8022                       PPC_FLOAT_STFIWX |
8023                       PPC_FLOAT_EXT |
8024                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8025                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8026                       PPC_MEM_TLBSYNC |
8027                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8028                       PPC_SEGMENT_64B | PPC_SLBI |
8029                       PPC_POPCNTB | PPC_POPCNTWD |
8030                       PPC_CILDST;
8031    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8032                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8033                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8034                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8035                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8036                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8037                        PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
8038    pcc->msr_mask = (1ull << MSR_SF) |
8039                    (1ull << MSR_HV) |
8040                    (1ull << MSR_TM) |
8041                    (1ull << MSR_VR) |
8042                    (1ull << MSR_VSX) |
8043                    (1ull << MSR_EE) |
8044                    (1ull << MSR_PR) |
8045                    (1ull << MSR_FP) |
8046                    (1ull << MSR_ME) |
8047                    (1ull << MSR_FE0) |
8048                    (1ull << MSR_SE) |
8049                    (1ull << MSR_DE) |
8050                    (1ull << MSR_FE1) |
8051                    (1ull << MSR_IR) |
8052                    (1ull << MSR_DR) |
8053                    (1ull << MSR_PMM) |
8054                    (1ull << MSR_RI) |
8055                    (1ull << MSR_LE);
8056    pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
8057        (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
8058        LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
8059        (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
8060                             LPCR_DEE | LPCR_OEE))
8061        | LPCR_MER | LPCR_GTSE | LPCR_TC |
8062        LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
8063    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8064    pcc->mmu_model = POWERPC_MMU_3_00;
8065#if defined(CONFIG_SOFTMMU)
8066    /* segment page size remain the same */
8067    pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8068    pcc->radix_page_info = &POWER9_radix_page_info;
8069    pcc->lrg_decr_bits = 56;
8070    pcc->n_host_threads = 4;
8071#endif
8072    pcc->excp_model = POWERPC_EXCP_POWER9;
8073    pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8074    pcc->bfd_mach = bfd_mach_ppc64;
8075    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8076                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8077                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8078                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
8079    pcc->l1_dcache_size = 0x8000;
8080    pcc->l1_icache_size = 0x8000;
8081}
8082
8083#ifdef CONFIG_SOFTMMU
8084/*
8085 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8086 * Encoded as array of int_32s in the form:
8087 *  0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8088 *  x -> AP encoding
8089 *  y -> radix mode supported page size (encoded as a shift)
8090 */
8091static struct ppc_radix_page_info POWER10_radix_page_info = {
8092    .count = 4,
8093    .entries = {
8094        0x0000000c, /*  4K - enc: 0x0 */
8095        0xa0000010, /* 64K - enc: 0x5 */
8096        0x20000015, /*  2M - enc: 0x1 */
8097        0x4000001e  /*  1G - enc: 0x2 */
8098    }
8099};
8100#endif /* CONFIG_SOFTMMU */
8101
8102static void init_proc_POWER10(CPUPPCState *env)
8103{
8104    /* Common Registers */
8105    init_proc_book3s_common(env);
8106    register_book3s_207_dbg_sprs(env);
8107
8108    /* POWER8 Specific Registers */
8109    register_book3s_ids_sprs(env);
8110    register_amr_sprs(env);
8111    register_iamr_sprs(env);
8112    register_book3s_purr_sprs(env);
8113    register_power5p_common_sprs(env);
8114    register_power5p_lpar_sprs(env);
8115    register_power5p_ear_sprs(env);
8116    register_power6_common_sprs(env);
8117    register_power6_dbg_sprs(env);
8118    register_power8_tce_address_control_sprs(env);
8119    register_power8_ids_sprs(env);
8120    register_power8_ebb_sprs(env);
8121    register_power8_fscr_sprs(env);
8122    register_power8_pmu_sup_sprs(env);
8123    register_power8_pmu_user_sprs(env);
8124    register_power8_tm_sprs(env);
8125    register_power8_pspb_sprs(env);
8126    register_vtb_sprs(env);
8127    register_power8_ic_sprs(env);
8128    register_power8_book4_sprs(env);
8129    register_power8_rpr_sprs(env);
8130    register_power9_mmu_sprs(env);
8131
8132    /* FIXME: Filter fields properly based on privilege level */
8133    spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8134                        spr_read_generic, spr_write_generic,
8135                        KVM_REG_PPC_PSSCR, 0);
8136
8137    /* env variables */
8138    env->dcache_line_size = 128;
8139    env->icache_line_size = 128;
8140
8141    /* Allocate hardware IRQ controller */
8142    init_excp_POWER10(env);
8143    ppcPOWER9_irq_init(env_archcpu(env));
8144}
8145
8146static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
8147{
8148    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
8149        return true;
8150    }
8151    return false;
8152}
8153
8154static bool cpu_has_work_POWER10(CPUState *cs)
8155{
8156    PowerPCCPU *cpu = POWERPC_CPU(cs);
8157    CPUPPCState *env = &cpu->env;
8158
8159    if (cs->halted) {
8160        uint64_t psscr = env->spr[SPR_PSSCR];
8161
8162        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8163            return false;
8164        }
8165
8166        /* If EC is clear, just return true on any pending interrupt */
8167        if (!(psscr & PSSCR_EC)) {
8168            return true;
8169        }
8170        /* External Exception */
8171        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8172            (env->spr[SPR_LPCR] & LPCR_EEE)) {
8173            bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
8174            if (heic == 0 || !msr_hv || msr_pr) {
8175                return true;
8176            }
8177        }
8178        /* Decrementer Exception */
8179        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8180            (env->spr[SPR_LPCR] & LPCR_DEE)) {
8181            return true;
8182        }
8183        /* Machine Check or Hypervisor Maintenance Exception */
8184        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8185            1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8186            return true;
8187        }
8188        /* Privileged Doorbell Exception */
8189        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8190            (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8191            return true;
8192        }
8193        /* Hypervisor Doorbell Exception */
8194        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8195            (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8196            return true;
8197        }
8198        /* Hypervisor virtualization exception */
8199        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
8200            (env->spr[SPR_LPCR] & LPCR_HVEE)) {
8201            return true;
8202        }
8203        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8204            return true;
8205        }
8206        return false;
8207    } else {
8208        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8209    }
8210}
8211
8212POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
8213{
8214    DeviceClass *dc = DEVICE_CLASS(oc);
8215    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8216    CPUClass *cc = CPU_CLASS(oc);
8217
8218    dc->fw_name = "PowerPC,POWER10";
8219    dc->desc = "POWER10";
8220    pcc->pvr_match = ppc_pvr_match_power10;
8221    pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
8222                    PCR_COMPAT_3_00;
8223    pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
8224                         PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8225    pcc->init_proc = init_proc_POWER10;
8226    pcc->check_pow = check_pow_nocheck;
8227    cc->has_work = cpu_has_work_POWER10;
8228    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8229                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8230                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8231                       PPC_FLOAT_FRSQRTES |
8232                       PPC_FLOAT_STFIWX |
8233                       PPC_FLOAT_EXT |
8234                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8235                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8236                       PPC_MEM_TLBSYNC |
8237                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8238                       PPC_SEGMENT_64B | PPC_SLBI |
8239                       PPC_POPCNTB | PPC_POPCNTWD |
8240                       PPC_CILDST;
8241    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8242                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8243                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8244                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8245                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8246                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8247                        PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
8248    pcc->msr_mask = (1ull << MSR_SF) |
8249                    (1ull << MSR_HV) |
8250                    (1ull << MSR_TM) |
8251                    (1ull << MSR_VR) |
8252                    (1ull << MSR_VSX) |
8253                    (1ull << MSR_EE) |
8254                    (1ull << MSR_PR) |
8255                    (1ull << MSR_FP) |
8256                    (1ull << MSR_ME) |
8257                    (1ull << MSR_FE0) |
8258                    (1ull << MSR_SE) |
8259                    (1ull << MSR_DE) |
8260                    (1ull << MSR_FE1) |
8261                    (1ull << MSR_IR) |
8262                    (1ull << MSR_DR) |
8263                    (1ull << MSR_PMM) |
8264                    (1ull << MSR_RI) |
8265                    (1ull << MSR_LE);
8266    pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
8267        (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
8268        LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
8269        (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
8270                             LPCR_DEE | LPCR_OEE))
8271        | LPCR_MER | LPCR_GTSE | LPCR_TC |
8272        LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
8273    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8274    pcc->mmu_model = POWERPC_MMU_3_00;
8275#if defined(CONFIG_SOFTMMU)
8276    /* segment page size remain the same */
8277    pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8278    pcc->radix_page_info = &POWER10_radix_page_info;
8279    pcc->lrg_decr_bits = 56;
8280#endif
8281    pcc->excp_model = POWERPC_EXCP_POWER10;
8282    pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8283    pcc->bfd_mach = bfd_mach_ppc64;
8284    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8285                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8286                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8287                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
8288    pcc->l1_dcache_size = 0x8000;
8289    pcc->l1_icache_size = 0x8000;
8290}
8291
8292#if !defined(CONFIG_USER_ONLY)
8293void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
8294{
8295    CPUPPCState *env = &cpu->env;
8296
8297    cpu->vhyp = vhyp;
8298
8299    /*
8300     * With a virtual hypervisor mode we never allow the CPU to go
8301     * hypervisor mode itself
8302     */
8303    env->msr_mask &= ~MSR_HVB;
8304}
8305
8306#endif /* !defined(CONFIG_USER_ONLY) */
8307
8308#endif /* defined(TARGET_PPC64) */
8309
8310/*****************************************************************************/
8311/* Generic CPU instantiation routine                                         */
8312static void init_ppc_proc(PowerPCCPU *cpu)
8313{
8314    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8315    CPUPPCState *env = &cpu->env;
8316#if !defined(CONFIG_USER_ONLY)
8317    int i;
8318
8319    env->irq_inputs = NULL;
8320    /* Set all exception vectors to an invalid address */
8321    for (i = 0; i < POWERPC_EXCP_NB; i++) {
8322        env->excp_vectors[i] = (target_ulong)(-1ULL);
8323    }
8324    env->ivor_mask = 0x00000000;
8325    env->ivpr_mask = 0x00000000;
8326    /* Default MMU definitions */
8327    env->nb_BATs = 0;
8328    env->nb_tlb = 0;
8329    env->nb_ways = 0;
8330    env->tlb_type = TLB_NONE;
8331#endif
8332    /* Register SPR common to all PowerPC implementations */
8333    register_generic_sprs(env);
8334    spr_register(env, SPR_PVR, "PVR",
8335                 /* Linux permits userspace to read PVR */
8336#if defined(CONFIG_LINUX_USER)
8337                 &spr_read_generic,
8338#else
8339                 SPR_NOACCESS,
8340#endif
8341                 SPR_NOACCESS,
8342                 &spr_read_generic, SPR_NOACCESS,
8343                 pcc->pvr);
8344    /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8345    if (pcc->svr != POWERPC_SVR_NONE) {
8346        if (pcc->svr & POWERPC_SVR_E500) {
8347            spr_register(env, SPR_E500_SVR, "SVR",
8348                         SPR_NOACCESS, SPR_NOACCESS,
8349                         &spr_read_generic, SPR_NOACCESS,
8350                         pcc->svr & ~POWERPC_SVR_E500);
8351        } else {
8352            spr_register(env, SPR_SVR, "SVR",
8353                         SPR_NOACCESS, SPR_NOACCESS,
8354                         &spr_read_generic, SPR_NOACCESS,
8355                         pcc->svr);
8356        }
8357    }
8358    /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8359    (*pcc->init_proc)(env);
8360
8361#if !defined(CONFIG_USER_ONLY)
8362    ppc_gdb_gen_spr_xml(cpu);
8363#endif
8364
8365    /* MSR bits & flags consistency checks */
8366    if (env->msr_mask & (1 << 25)) {
8367        switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8368        case POWERPC_FLAG_SPE:
8369        case POWERPC_FLAG_VRE:
8370            break;
8371        default:
8372            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8373                    "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8374            exit(1);
8375        }
8376    } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8377        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8378                "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8379        exit(1);
8380    }
8381    if (env->msr_mask & (1 << 17)) {
8382        switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8383        case POWERPC_FLAG_TGPR:
8384        case POWERPC_FLAG_CE:
8385            break;
8386        default:
8387            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8388                    "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8389            exit(1);
8390        }
8391    } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8392        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8393                "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8394        exit(1);
8395    }
8396    if (env->msr_mask & (1 << 10)) {
8397        switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8398                              POWERPC_FLAG_UBLE)) {
8399        case POWERPC_FLAG_SE:
8400        case POWERPC_FLAG_DWE:
8401        case POWERPC_FLAG_UBLE:
8402            break;
8403        default:
8404            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8405                    "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8406                    "POWERPC_FLAG_UBLE\n");
8407            exit(1);
8408        }
8409    } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8410                             POWERPC_FLAG_UBLE)) {
8411        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8412                "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8413                "POWERPC_FLAG_UBLE\n");
8414            exit(1);
8415    }
8416    if (env->msr_mask & (1 << 9)) {
8417        switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8418        case POWERPC_FLAG_BE:
8419        case POWERPC_FLAG_DE:
8420            break;
8421        default:
8422            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8423                    "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8424            exit(1);
8425        }
8426    } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8427        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8428                "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8429        exit(1);
8430    }
8431    if (env->msr_mask & (1 << 2)) {
8432        switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8433        case POWERPC_FLAG_PX:
8434        case POWERPC_FLAG_PMM:
8435            break;
8436        default:
8437            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8438                    "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8439            exit(1);
8440        }
8441    } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8442        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8443                "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8444        exit(1);
8445    }
8446    if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8447        fprintf(stderr, "PowerPC flags inconsistency\n"
8448                "Should define the time-base and decrementer clock source\n");
8449        exit(1);
8450    }
8451    /* Allocate TLBs buffer when needed */
8452#if !defined(CONFIG_USER_ONLY)
8453    if (env->nb_tlb != 0) {
8454        int nb_tlb = env->nb_tlb;
8455        if (env->id_tlbs != 0) {
8456            nb_tlb *= 2;
8457        }
8458        switch (env->tlb_type) {
8459        case TLB_6XX:
8460            env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
8461            break;
8462        case TLB_EMB:
8463            env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
8464            break;
8465        case TLB_MAS:
8466            env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
8467            break;
8468        }
8469        /* Pre-compute some useful values */
8470        env->tlb_per_way = env->nb_tlb / env->nb_ways;
8471    }
8472    if (env->irq_inputs == NULL) {
8473        warn_report("no internal IRQ controller registered."
8474                    " Attempt QEMU to crash very soon !");
8475    }
8476#endif
8477    if (env->check_pow == NULL) {
8478        warn_report("no power management check handler registered."
8479                    " Attempt QEMU to crash very soon !");
8480    }
8481}
8482
8483
8484static void ppc_cpu_realize(DeviceState *dev, Error **errp)
8485{
8486    CPUState *cs = CPU(dev);
8487    PowerPCCPU *cpu = POWERPC_CPU(dev);
8488    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8489    Error *local_err = NULL;
8490
8491    cpu_exec_realizefn(cs, &local_err);
8492    if (local_err != NULL) {
8493        error_propagate(errp, local_err);
8494        return;
8495    }
8496    if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
8497        cpu->vcpu_id = cs->cpu_index;
8498    }
8499
8500    if (tcg_enabled()) {
8501        if (ppc_fixup_cpu(cpu) != 0) {
8502            error_setg(errp, "Unable to emulate selected CPU with TCG");
8503            goto unrealize;
8504        }
8505    }
8506
8507    create_ppc_opcodes(cpu, &local_err);
8508    if (local_err != NULL) {
8509        error_propagate(errp, local_err);
8510        goto unrealize;
8511    }
8512    init_ppc_proc(cpu);
8513
8514    ppc_gdb_init(cs, pcc);
8515    qemu_init_vcpu(cs);
8516
8517    pcc->parent_realize(dev, errp);
8518
8519    return;
8520
8521unrealize:
8522    cpu_exec_unrealizefn(cs);
8523}
8524
8525static void ppc_cpu_unrealize(DeviceState *dev)
8526{
8527    PowerPCCPU *cpu = POWERPC_CPU(dev);
8528    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8529
8530    pcc->parent_unrealize(dev);
8531
8532    cpu_remove_sync(CPU(cpu));
8533
8534    destroy_ppc_opcodes(cpu);
8535}
8536
8537static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8538{
8539    ObjectClass *oc = (ObjectClass *)a;
8540    uint32_t pvr = *(uint32_t *)b;
8541    PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8542
8543    /* -cpu host does a PVR lookup during construction */
8544    if (unlikely(strcmp(object_class_get_name(oc),
8545                        TYPE_HOST_POWERPC_CPU) == 0)) {
8546        return -1;
8547    }
8548
8549    return pcc->pvr == pvr ? 0 : -1;
8550}
8551
8552PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8553{
8554    GSList *list, *item;
8555    PowerPCCPUClass *pcc = NULL;
8556
8557    list = object_class_get_list(TYPE_POWERPC_CPU, false);
8558    item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8559    if (item != NULL) {
8560        pcc = POWERPC_CPU_CLASS(item->data);
8561    }
8562    g_slist_free(list);
8563
8564    return pcc;
8565}
8566
8567static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
8568{
8569    ObjectClass *oc = (ObjectClass *)a;
8570    uint32_t pvr = *(uint32_t *)b;
8571    PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8572
8573    /* -cpu host does a PVR lookup during construction */
8574    if (unlikely(strcmp(object_class_get_name(oc),
8575                        TYPE_HOST_POWERPC_CPU) == 0)) {
8576        return -1;
8577    }
8578
8579    if (pcc->pvr_match(pcc, pvr)) {
8580        return 0;
8581    }
8582
8583    return -1;
8584}
8585
8586PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
8587{
8588    GSList *list, *item;
8589    PowerPCCPUClass *pcc = NULL;
8590
8591    list = object_class_get_list(TYPE_POWERPC_CPU, true);
8592    item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
8593    if (item != NULL) {
8594        pcc = POWERPC_CPU_CLASS(item->data);
8595    }
8596    g_slist_free(list);
8597
8598    return pcc;
8599}
8600
8601static const char *ppc_cpu_lookup_alias(const char *alias)
8602{
8603    int ai;
8604
8605    for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
8606        if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
8607            return ppc_cpu_aliases[ai].model;
8608        }
8609    }
8610
8611    return NULL;
8612}
8613
8614static ObjectClass *ppc_cpu_class_by_name(const char *name)
8615{
8616    char *cpu_model, *typename;
8617    ObjectClass *oc;
8618    const char *p;
8619    unsigned long pvr;
8620
8621    /*
8622     * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
8623     * 0x prefix if present)
8624     */
8625    if (!qemu_strtoul(name, &p, 16, &pvr)) {
8626        int len = p - name;
8627        len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
8628        if ((len == 8) && (*p == '\0')) {
8629            return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
8630        }
8631    }
8632
8633    cpu_model = g_ascii_strdown(name, -1);
8634    p = ppc_cpu_lookup_alias(cpu_model);
8635    if (p) {
8636        g_free(cpu_model);
8637        cpu_model = g_strdup(p);
8638    }
8639
8640    typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
8641    oc = object_class_by_name(typename);
8642    g_free(typename);
8643    g_free(cpu_model);
8644
8645    return oc;
8646}
8647
8648PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
8649{
8650    ObjectClass *oc = OBJECT_CLASS(pcc);
8651
8652    while (oc && !object_class_is_abstract(oc)) {
8653        oc = object_class_get_parent(oc);
8654    }
8655    assert(oc);
8656
8657    return POWERPC_CPU_CLASS(oc);
8658}
8659
8660/* Sort by PVR, ordering special case "host" last. */
8661static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8662{
8663    ObjectClass *oc_a = (ObjectClass *)a;
8664    ObjectClass *oc_b = (ObjectClass *)b;
8665    PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8666    PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8667    const char *name_a = object_class_get_name(oc_a);
8668    const char *name_b = object_class_get_name(oc_b);
8669
8670    if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8671        return 1;
8672    } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8673        return -1;
8674    } else {
8675        /* Avoid an integer overflow during subtraction */
8676        if (pcc_a->pvr < pcc_b->pvr) {
8677            return -1;
8678        } else if (pcc_a->pvr > pcc_b->pvr) {
8679            return 1;
8680        } else {
8681            return 0;
8682        }
8683    }
8684}
8685
8686static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8687{
8688    ObjectClass *oc = data;
8689    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8690    DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
8691    const char *typename = object_class_get_name(oc);
8692    char *name;
8693    int i;
8694
8695    if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8696        return;
8697    }
8698
8699    name = g_strndup(typename,
8700                     strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
8701    qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
8702    for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8703        PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8704        ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8705
8706        if (alias_oc != oc) {
8707            continue;
8708        }
8709        /*
8710         * If running with KVM, we might update the family alias later, so
8711         * avoid printing the wrong alias here and use "preferred" instead
8712         */
8713        if (strcmp(alias->alias, family->desc) == 0) {
8714            qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
8715                        alias->alias, family->desc);
8716        } else {
8717            qemu_printf("PowerPC %-16s (alias for %s)\n",
8718                        alias->alias, name);
8719        }
8720    }
8721    g_free(name);
8722}
8723
8724void ppc_cpu_list(void)
8725{
8726    GSList *list;
8727
8728    list = object_class_get_list(TYPE_POWERPC_CPU, false);
8729    list = g_slist_sort(list, ppc_cpu_list_compare);
8730    g_slist_foreach(list, ppc_cpu_list_entry, NULL);
8731    g_slist_free(list);
8732
8733#ifdef CONFIG_KVM
8734    qemu_printf("\n");
8735    qemu_printf("PowerPC %-16s\n", "host");
8736#endif
8737}
8738
8739static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8740{
8741    ObjectClass *oc = data;
8742    CpuDefinitionInfoList **first = user_data;
8743    const char *typename;
8744    CpuDefinitionInfo *info;
8745
8746    typename = object_class_get_name(oc);
8747    info = g_malloc0(sizeof(*info));
8748    info->name = g_strndup(typename,
8749                           strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
8750
8751    QAPI_LIST_PREPEND(*first, info);
8752}
8753
8754CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
8755{
8756    CpuDefinitionInfoList *cpu_list = NULL;
8757    GSList *list;
8758    int i;
8759
8760    list = object_class_get_list(TYPE_POWERPC_CPU, false);
8761    g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8762    g_slist_free(list);
8763
8764    for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8765        PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8766        ObjectClass *oc;
8767        CpuDefinitionInfo *info;
8768
8769        oc = ppc_cpu_class_by_name(alias->model);
8770        if (oc == NULL) {
8771            continue;
8772        }
8773
8774        info = g_malloc0(sizeof(*info));
8775        info->name = g_strdup(alias->alias);
8776        info->q_typename = g_strdup(object_class_get_name(oc));
8777
8778        QAPI_LIST_PREPEND(cpu_list, info);
8779    }
8780
8781    return cpu_list;
8782}
8783
8784static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
8785{
8786    PowerPCCPU *cpu = POWERPC_CPU(cs);
8787
8788    cpu->env.nip = value;
8789}
8790
8791static bool ppc_cpu_has_work(CPUState *cs)
8792{
8793    PowerPCCPU *cpu = POWERPC_CPU(cs);
8794    CPUPPCState *env = &cpu->env;
8795
8796    return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8797}
8798
8799static void ppc_cpu_reset(DeviceState *dev)
8800{
8801    CPUState *s = CPU(dev);
8802    PowerPCCPU *cpu = POWERPC_CPU(s);
8803    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8804    CPUPPCState *env = &cpu->env;
8805    target_ulong msr;
8806    int i;
8807
8808    pcc->parent_reset(dev);
8809
8810    msr = (target_ulong)0;
8811    msr |= (target_ulong)MSR_HVB;
8812    msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8813    msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8814    msr |= (target_ulong)1 << MSR_EP;
8815#if defined(DO_SINGLE_STEP) && 0
8816    /* Single step trace mode */
8817    msr |= (target_ulong)1 << MSR_SE;
8818    msr |= (target_ulong)1 << MSR_BE;
8819#endif
8820#if defined(CONFIG_USER_ONLY)
8821    msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8822    msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
8823    msr |= (target_ulong)1 << MSR_FE1;
8824    msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8825    msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
8826    msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8827    msr |= (target_ulong)1 << MSR_PR;
8828#if defined(TARGET_PPC64)
8829    msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
8830#endif
8831#if !defined(TARGET_WORDS_BIGENDIAN)
8832    msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
8833    if (!((env->msr_mask >> MSR_LE) & 1)) {
8834        fprintf(stderr, "Selected CPU does not support little-endian.\n");
8835        exit(1);
8836    }
8837#endif
8838#endif
8839
8840#if defined(TARGET_PPC64)
8841    if (mmu_is_64bit(env->mmu_model)) {
8842        msr |= (1ULL << MSR_SF);
8843    }
8844#endif
8845
8846    hreg_store_msr(env, msr, 1);
8847
8848#if !defined(CONFIG_USER_ONLY)
8849    env->nip = env->hreset_vector | env->excp_prefix;
8850#if defined(CONFIG_TCG)
8851    if (env->mmu_model != POWERPC_MMU_REAL) {
8852        ppc_tlb_invalidate_all(env);
8853    }
8854#endif /* CONFIG_TCG */
8855#endif
8856
8857    hreg_compute_hflags(env);
8858    env->reserve_addr = (target_ulong)-1ULL;
8859    /* Be sure no exception or interrupt is pending */
8860    env->pending_interrupts = 0;
8861    s->exception_index = POWERPC_EXCP_NONE;
8862    env->error_code = 0;
8863    ppc_irq_reset(cpu);
8864
8865    /* tininess for underflow is detected before rounding */
8866    set_float_detect_tininess(float_tininess_before_rounding,
8867                              &env->fp_status);
8868
8869    for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
8870        ppc_spr_t *spr = &env->spr_cb[i];
8871
8872        if (!spr->name) {
8873            continue;
8874        }
8875        env->spr[i] = spr->default_value;
8876    }
8877}
8878
8879#ifndef CONFIG_USER_ONLY
8880
8881static bool ppc_cpu_is_big_endian(CPUState *cs)
8882{
8883    PowerPCCPU *cpu = POWERPC_CPU(cs);
8884    CPUPPCState *env = &cpu->env;
8885
8886    cpu_synchronize_state(cs);
8887
8888    return !msr_le;
8889}
8890
8891#ifdef CONFIG_TCG
8892static void ppc_cpu_exec_enter(CPUState *cs)
8893{
8894    PowerPCCPU *cpu = POWERPC_CPU(cs);
8895
8896    if (cpu->vhyp) {
8897        PPCVirtualHypervisorClass *vhc =
8898            PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
8899        vhc->cpu_exec_enter(cpu->vhyp, cpu);
8900    }
8901}
8902
8903static void ppc_cpu_exec_exit(CPUState *cs)
8904{
8905    PowerPCCPU *cpu = POWERPC_CPU(cs);
8906
8907    if (cpu->vhyp) {
8908        PPCVirtualHypervisorClass *vhc =
8909            PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
8910        vhc->cpu_exec_exit(cpu->vhyp, cpu);
8911    }
8912}
8913#endif /* CONFIG_TCG */
8914
8915#endif /* !CONFIG_USER_ONLY */
8916
8917static void ppc_cpu_instance_init(Object *obj)
8918{
8919    PowerPCCPU *cpu = POWERPC_CPU(obj);
8920    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8921    CPUPPCState *env = &cpu->env;
8922
8923    cpu_set_cpustate_pointers(cpu);
8924    cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
8925
8926    env->msr_mask = pcc->msr_mask;
8927    env->mmu_model = pcc->mmu_model;
8928    env->excp_model = pcc->excp_model;
8929    env->bus_model = pcc->bus_model;
8930    env->insns_flags = pcc->insns_flags;
8931    env->insns_flags2 = pcc->insns_flags2;
8932    env->flags = pcc->flags;
8933    env->bfd_mach = pcc->bfd_mach;
8934    env->check_pow = pcc->check_pow;
8935
8936    /*
8937     * Mark HV mode as supported if the CPU has an MSR_HV bit in the
8938     * msr_mask. The mask can later be cleared by PAPR mode but the hv
8939     * mode support will remain, thus enforcing that we cannot use
8940     * priv. instructions in guest in PAPR mode. For 970 we currently
8941     * simply don't set HV in msr_mask thus simulating an "Apple mode"
8942     * 970. If we ever want to support 970 HV mode, we'll have to add
8943     * a processor attribute of some sort.
8944     */
8945#if !defined(CONFIG_USER_ONLY)
8946    env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
8947#endif
8948
8949    ppc_hash64_init(cpu);
8950}
8951
8952static void ppc_cpu_instance_finalize(Object *obj)
8953{
8954    PowerPCCPU *cpu = POWERPC_CPU(obj);
8955
8956    ppc_hash64_finalize(cpu);
8957}
8958
8959static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
8960{
8961    return pcc->pvr == pvr;
8962}
8963
8964static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
8965{
8966    PowerPCCPU *cpu = POWERPC_CPU(cs);
8967    CPUPPCState *env = &cpu->env;
8968
8969    if ((env->hflags >> MSR_LE) & 1) {
8970        info->endian = BFD_ENDIAN_LITTLE;
8971    }
8972    info->mach = env->bfd_mach;
8973    if (!env->bfd_mach) {
8974#ifdef TARGET_PPC64
8975        info->mach = bfd_mach_ppc64;
8976#else
8977        info->mach = bfd_mach_ppc;
8978#endif
8979    }
8980    info->disassembler_options = (char *)"any";
8981    info->print_insn = print_insn_ppc;
8982
8983    info->cap_arch = CS_ARCH_PPC;
8984#ifdef TARGET_PPC64
8985    info->cap_mode = CS_MODE_64;
8986#endif
8987}
8988
8989static Property ppc_cpu_properties[] = {
8990    DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
8991    DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
8992                     false),
8993    DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
8994                     false),
8995    DEFINE_PROP_END_OF_LIST(),
8996};
8997
8998#ifndef CONFIG_USER_ONLY
8999#include "hw/core/sysemu-cpu-ops.h"
9000

9001static const struct SysemuCPUOps ppc_sysemu_ops = {
9002    .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
9003    .write_elf32_note = ppc32_cpu_write_elf32_note,
9004    .write_elf64_note = ppc64_cpu_write_elf64_note,
9005    .virtio_is_big_endian = ppc_cpu_is_big_endian,
9006    .legacy_vmsd = &vmstate_ppc_cpu,
9007};
9008#endif
9009
9010#ifdef CONFIG_TCG
9011#include "hw/core/tcg-cpu-ops.h"
9012
9013static const struct TCGCPUOps ppc_tcg_ops = {
9014  .initialize = ppc_translate_init,
9015  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
9016  .tlb_fill = ppc_cpu_tlb_fill,
9017
9018#ifndef CONFIG_USER_ONLY
9019  .do_interrupt = ppc_cpu_do_interrupt,
9020  .cpu_exec_enter = ppc_cpu_exec_enter,
9021  .cpu_exec_exit = ppc_cpu_exec_exit,
9022  .do_unaligned_access = ppc_cpu_do_unaligned_access,
9023#endif /* !CONFIG_USER_ONLY */
9024};
9025#endif /* CONFIG_TCG */
9026
9027static void ppc_cpu_class_init(ObjectClass *oc, void *data)
9028{
9029    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9030    CPUClass *cc = CPU_CLASS(oc);
9031    DeviceClass *dc = DEVICE_CLASS(oc);
9032
9033    device_class_set_parent_realize(dc, ppc_cpu_realize,
9034                                    &pcc->parent_realize);
9035    device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
9036                                      &pcc->parent_unrealize);
9037    pcc->pvr_match = ppc_pvr_match_default;
9038    device_class_set_props(dc, ppc_cpu_properties);
9039
9040    device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
9041
9042    cc->class_by_name = ppc_cpu_class_by_name;
9043    cc->has_work = ppc_cpu_has_work;
9044    cc->dump_state = ppc_cpu_dump_state;
9045    cc->set_pc = ppc_cpu_set_pc;
9046    cc->gdb_read_register = ppc_cpu_gdb_read_register;
9047    cc->gdb_write_register = ppc_cpu_gdb_write_register;
9048#ifndef CONFIG_USER_ONLY
9049    cc->sysemu_ops = &ppc_sysemu_ops;
9050#endif
9051
9052    cc->gdb_num_core_regs = 71;
9053#ifndef CONFIG_USER_ONLY
9054    cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
9055#endif
9056#ifdef USE_APPLE_GDB
9057    cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
9058    cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
9059    cc->gdb_num_core_regs = 71 + 32;
9060#endif
9061
9062    cc->gdb_arch_name = ppc_gdb_arch_name;
9063#if defined(TARGET_PPC64)
9064    cc->gdb_core_xml_file = "power64-core.xml";
9065#else
9066    cc->gdb_core_xml_file = "power-core.xml";
9067#endif
9068    cc->disas_set_info = ppc_disas_set_info;
9069
9070    dc->fw_name = "PowerPC,UNKNOWN";
9071
9072#ifdef CONFIG_TCG
9073    cc->tcg_ops = &ppc_tcg_ops;
9074#endif /* CONFIG_TCG */
9075}
9076
9077static const TypeInfo ppc_cpu_type_info = {
9078    .name = TYPE_POWERPC_CPU,
9079    .parent = TYPE_CPU,
9080    .instance_size = sizeof(PowerPCCPU),
9081    .instance_align = __alignof__(PowerPCCPU),
9082    .instance_init = ppc_cpu_instance_init,
9083    .instance_finalize = ppc_cpu_instance_finalize,
9084    .abstract = true,
9085    .class_size = sizeof(PowerPCCPUClass),
9086    .class_init = ppc_cpu_class_init,
9087};
9088
9089#ifndef CONFIG_USER_ONLY
9090static const TypeInfo ppc_vhyp_type_info = {
9091    .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
9092    .parent = TYPE_INTERFACE,
9093    .class_size = sizeof(PPCVirtualHypervisorClass),
9094};
9095#endif
9096
9097static void ppc_cpu_register_types(void)
9098{
9099    type_register_static(&ppc_cpu_type_info);
9100#ifndef CONFIG_USER_ONLY
9101    type_register_static(&ppc_vhyp_type_info);
9102#endif
9103}
9104
9105void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
9106{
9107#define RGPL  4
9108#define RFPL  4
9109
9110    PowerPCCPU *cpu = POWERPC_CPU(cs);
9111    CPUPPCState *env = &cpu->env;
9112    int i;
9113
9114    qemu_fprintf(f, "NIP " TARGET_FMT_lx "   LR " TARGET_FMT_lx " CTR "
9115                 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
9116                 env->nip, env->lr, env->ctr, cpu_read_xer(env),
9117                 cs->cpu_index);
9118    qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx "  HF "
9119                 "%08x iidx %d didx %d\n",
9120                 env->msr, env->spr[SPR_HID0], env->hflags,
9121                 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
9122#if !defined(NO_TIMER_DUMP)
9123    qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9124#if !defined(CONFIG_USER_ONLY)
9125                 " DECR " TARGET_FMT_lu
9126#endif
9127                 "\n",
9128                 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9129#if !defined(CONFIG_USER_ONLY)
9130                 , cpu_ppc_load_decr(env)
9131#endif
9132        );
9133#endif
9134    for (i = 0; i < 32; i++) {
9135        if ((i & (RGPL - 1)) == 0) {
9136            qemu_fprintf(f, "GPR%02d", i);
9137        }
9138        qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9139        if ((i & (RGPL - 1)) == (RGPL - 1)) {
9140            qemu_fprintf(f, "\n");
9141        }
9142    }
9143    qemu_fprintf(f, "CR ");
9144    for (i = 0; i < 8; i++)
9145        qemu_fprintf(f, "%01x", env->crf[i]);
9146    qemu_fprintf(f, "  [");
9147    for (i = 0; i < 8; i++) {
9148        char a = '-';
9149        if (env->crf[i] & 0x08) {
9150            a = 'L';
9151        } else if (env->crf[i] & 0x04) {
9152            a = 'G';
9153        } else if (env->crf[i] & 0x02) {
9154            a = 'E';
9155        }
9156        qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9157    }
9158    qemu_fprintf(f, " ]             RES " TARGET_FMT_lx "\n",
9159                 env->reserve_addr);
9160
9161    if (flags & CPU_DUMP_FPU) {
9162        for (i = 0; i < 32; i++) {
9163            if ((i & (RFPL - 1)) == 0) {
9164                qemu_fprintf(f, "FPR%02d", i);
9165            }
9166            qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
9167            if ((i & (RFPL - 1)) == (RFPL - 1)) {
9168                qemu_fprintf(f, "\n");
9169            }
9170        }
9171        qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9172    }
9173
9174#if !defined(CONFIG_USER_ONLY)
9175    qemu_fprintf(f, " SRR0 " TARGET_FMT_lx "  SRR1 " TARGET_FMT_lx
9176                 "    PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9177                 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9178                 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9179
9180    qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9181                 "  SPRG2 " TARGET_FMT_lx "  SPRG3 " TARGET_FMT_lx "\n",
9182                 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9183                 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9184
9185    qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9186                 "  SPRG6 " TARGET_FMT_lx "  SPRG7 " TARGET_FMT_lx "\n",
9187                 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9188                 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9189
9190#if defined(TARGET_PPC64)
9191    if (env->excp_model == POWERPC_EXCP_POWER7 ||
9192        env->excp_model == POWERPC_EXCP_POWER8 ||
9193        env->excp_model == POWERPC_EXCP_POWER9 ||
9194        env->excp_model == POWERPC_EXCP_POWER10)  {
9195        qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
9196                     env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
9197    }
9198#endif
9199    if (env->excp_model == POWERPC_EXCP_BOOKE) {
9200        qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9201                     " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9202                     env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9203                     env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9204
9205        qemu_fprintf(f, "  TCR " TARGET_FMT_lx "   TSR " TARGET_FMT_lx
9206                     "    ESR " TARGET_FMT_lx "   DEAR " TARGET_FMT_lx "\n",
9207                     env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9208                     env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9209
9210        qemu_fprintf(f, "  PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9211                     "   IVPR " TARGET_FMT_lx "   EPCR " TARGET_FMT_lx "\n",
9212                     env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9213                     env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9214
9215        qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9216                     "    EPR " TARGET_FMT_lx "\n",
9217                     env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9218                     env->spr[SPR_BOOKE_EPR]);
9219
9220        /* FSL-specific */
9221        qemu_fprintf(f, " MCAR " TARGET_FMT_lx "  PID1 " TARGET_FMT_lx
9222                     "   PID2 " TARGET_FMT_lx "    SVR " TARGET_FMT_lx "\n",
9223                     env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9224                     env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9225
9226        /*
9227         * IVORs are left out as they are large and do not change often --
9228         * they can be read with "p $ivor0", "p $ivor1", etc.
9229         */
9230    }
9231
9232#if defined(TARGET_PPC64)
9233    if (env->flags & POWERPC_FLAG_CFAR) {
9234        qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9235    }
9236#endif
9237
9238    if (env->spr_cb[SPR_LPCR].name) {
9239        qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
9240    }
9241
9242    switch (env->mmu_model) {
9243    case POWERPC_MMU_32B:
9244    case POWERPC_MMU_601:
9245    case POWERPC_MMU_SOFT_6xx:
9246    case POWERPC_MMU_SOFT_74xx:
9247#if defined(TARGET_PPC64)
9248    case POWERPC_MMU_64B:
9249    case POWERPC_MMU_2_03:
9250    case POWERPC_MMU_2_06:
9251    case POWERPC_MMU_2_07:
9252    case POWERPC_MMU_3_00:
9253#endif
9254        if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
9255            qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
9256        }
9257        if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
9258            qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
9259        }
9260        qemu_fprintf(f, "  DAR " TARGET_FMT_lx "  DSISR " TARGET_FMT_lx "\n",
9261                     env->spr[SPR_DAR], env->spr[SPR_DSISR]);
9262        break;
9263    case POWERPC_MMU_BOOKE206:
9264        qemu_fprintf(f, " MAS0 " TARGET_FMT_lx "  MAS1 " TARGET_FMT_lx
9265                     "   MAS2 " TARGET_FMT_lx "   MAS3 " TARGET_FMT_lx "\n",
9266                     env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9267                     env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9268
9269        qemu_fprintf(f, " MAS4 " TARGET_FMT_lx "  MAS6 " TARGET_FMT_lx
9270                     "   MAS7 " TARGET_FMT_lx "    PID " TARGET_FMT_lx "\n",
9271                     env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9272                     env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9273
9274        qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9275                     " TLB1CFG " TARGET_FMT_lx "\n",
9276                     env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9277                     env->spr[SPR_BOOKE_TLB1CFG]);
9278        break;
9279    default:
9280        break;
9281    }
9282#endif
9283
9284#undef RGPL
9285#undef RFPL
9286}
9287type_init(ppc_cpu_register_types)
9288