1#ifndef MMU_HASH64_H
2#define MMU_HASH64_H
3
4#ifndef CONFIG_USER_ONLY
5
6#ifdef TARGET_PPC64
7void dump_slb(PowerPCCPU *cpu);
8int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
9 target_ulong esid, target_ulong vsid);
10bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
11 hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
12 bool guest_visible);
13void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
14 target_ulong pte_index,
15 target_ulong pte0, target_ulong pte1);
16unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
17 uint64_t pte0, uint64_t pte1);
18void ppc_hash64_init(PowerPCCPU *cpu);
19void ppc_hash64_finalize(PowerPCCPU *cpu);
20#endif
21
22
23
24
25
26
27#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
28#define SLB_ESID_V 0x0000000008000000ULL
29
30
31#define SLB_VSID_SHIFT 12
32#define SLB_VSID_SHIFT_1T 24
33#define SLB_VSID_SSIZE_SHIFT 62
34#define SLB_VSID_B 0xc000000000000000ULL
35#define SLB_VSID_B_256M 0x0000000000000000ULL
36#define SLB_VSID_B_1T 0x4000000000000000ULL
37#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
38#define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
39#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
40#define SLB_VSID_KS 0x0000000000000800ULL
41#define SLB_VSID_KP 0x0000000000000400ULL
42#define SLB_VSID_N 0x0000000000000200ULL
43#define SLB_VSID_L 0x0000000000000100ULL
44#define SLB_VSID_C 0x0000000000000080ULL
45#define SLB_VSID_LP 0x0000000000000030ULL
46#define SLB_VSID_ATTR 0x0000000000000FFFULL
47#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
48#define SLB_VSID_4K 0x0000000000000000ULL
49#define SLB_VSID_64K 0x0000000000000110ULL
50#define SLB_VSID_16M 0x0000000000000100ULL
51#define SLB_VSID_16G 0x0000000000000120ULL
52
53
54
55
56
57#define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL
58#define SDR_64_HTABSIZE 0x000000000000001FULL
59
60#define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
61#define HPTES_PER_GROUP 8
62#define HASH_PTE_SIZE_64 16
63#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
64
65#define HPTE64_V_SSIZE SLB_VSID_B
66#define HPTE64_V_SSIZE_256M SLB_VSID_B_256M
67#define HPTE64_V_SSIZE_1T SLB_VSID_B_1T
68#define HPTE64_V_SSIZE_SHIFT 62
69#define HPTE64_V_AVPN_SHIFT 7
70#define HPTE64_V_AVPN 0x3fffffffffffff80ULL
71#define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
72#define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
73#define HPTE64_V_BOLTED 0x0000000000000010ULL
74#define HPTE64_V_LARGE 0x0000000000000004ULL
75#define HPTE64_V_SECONDARY 0x0000000000000002ULL
76#define HPTE64_V_VALID 0x0000000000000001ULL
77
78#define HPTE64_R_PP0 0x8000000000000000ULL
79#define HPTE64_R_TS 0x4000000000000000ULL
80#define HPTE64_R_KEY_HI 0x3000000000000000ULL
81#define HPTE64_R_RPN_SHIFT 12
82#define HPTE64_R_RPN 0x0ffffffffffff000ULL
83#define HPTE64_R_FLAGS 0x00000000000003ffULL
84#define HPTE64_R_PP 0x0000000000000003ULL
85#define HPTE64_R_N 0x0000000000000004ULL
86#define HPTE64_R_G 0x0000000000000008ULL
87#define HPTE64_R_M 0x0000000000000010ULL
88#define HPTE64_R_I 0x0000000000000020ULL
89#define HPTE64_R_W 0x0000000000000040ULL
90#define HPTE64_R_WIMG 0x0000000000000078ULL
91#define HPTE64_R_C 0x0000000000000080ULL
92#define HPTE64_R_R 0x0000000000000100ULL
93#define HPTE64_R_KEY_LO 0x0000000000000e00ULL
94#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 57) | \
95 (((x) & HPTE64_R_KEY_LO) >> 9))
96
97#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
98#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
99
100
101#define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL
102#define HPTE64_R_3_0_SSIZE_SHIFT 58
103#define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)
104
105struct ppc_hash_pte64 {
106 uint64_t pte0, pte1;
107};
108
109const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
110 hwaddr ptex, int n);
111void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
112 hwaddr ptex, int n);
113
114static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu,
115 const ppc_hash_pte64_t *hptes, int i)
116{
117 return ldq_p(&(hptes[i].pte0));
118}
119
120static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
121 const ppc_hash_pte64_t *hptes, int i)
122{
123 return ldq_p(&(hptes[i].pte1));
124}
125
126
127
128
129
130struct PPCHash64PageSize {
131 uint32_t page_shift;
132 uint32_t pte_enc;
133};
134typedef struct PPCHash64PageSize PPCHash64PageSize;
135
136struct PPCHash64SegmentPageSizes {
137 uint32_t page_shift;
138 uint32_t slb_enc;
139 PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ];
140};
141
142struct PPCHash64Options {
143#define PPC_HASH64_1TSEG 0x00001
144#define PPC_HASH64_AMR 0x00002
145#define PPC_HASH64_CI_LARGEPAGE 0x00004
146 unsigned flags;
147 unsigned slb_size;
148 PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
149};
150
151extern const PPCHash64Options ppc_hash64_opts_basic;
152extern const PPCHash64Options ppc_hash64_opts_POWER7;
153
154static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature)
155{
156 return !!(cpu->hash64_opts->flags & feature);
157}
158
159#endif
160
161#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
162static inline void ppc_hash64_init(PowerPCCPU *cpu)
163{
164}
165static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
166{
167}
168#endif
169
170#endif
171
