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19#ifndef RX_CPU_H
20#define RX_CPU_H
21
22#include "qemu/bitops.h"
23#include "qemu-common.h"
24#include "hw/registerfields.h"
25#include "cpu-qom.h"
26
27#include "exec/cpu-defs.h"
28
29
30REG32(PSW, 0)
31FIELD(PSW, C, 0, 1)
32FIELD(PSW, Z, 1, 1)
33FIELD(PSW, S, 2, 1)
34FIELD(PSW, O, 3, 1)
35FIELD(PSW, I, 16, 1)
36FIELD(PSW, U, 17, 1)
37FIELD(PSW, PM, 20, 1)
38FIELD(PSW, IPL, 24, 4)
39
40
41REG32(FPSW, 0)
42FIELD(FPSW, RM, 0, 2)
43FIELD(FPSW, CV, 2, 1)
44FIELD(FPSW, CO, 3, 1)
45FIELD(FPSW, CZ, 4, 1)
46FIELD(FPSW, CU, 5, 1)
47FIELD(FPSW, CX, 6, 1)
48FIELD(FPSW, CE, 7, 1)
49FIELD(FPSW, CAUSE, 2, 6)
50FIELD(FPSW, DN, 8, 1)
51FIELD(FPSW, EV, 10, 1)
52FIELD(FPSW, EO, 11, 1)
53FIELD(FPSW, EZ, 12, 1)
54FIELD(FPSW, EU, 13, 1)
55FIELD(FPSW, EX, 14, 1)
56FIELD(FPSW, ENABLE, 10, 5)
57FIELD(FPSW, FV, 26, 1)
58FIELD(FPSW, FO, 27, 1)
59FIELD(FPSW, FZ, 28, 1)
60FIELD(FPSW, FU, 29, 1)
61FIELD(FPSW, FX, 30, 1)
62FIELD(FPSW, FLAGS, 26, 4)
63FIELD(FPSW, FS, 31, 1)
64
65enum {
66 NUM_REGS = 16,
67};
68
69typedef struct CPURXState {
70
71 uint32_t regs[NUM_REGS];
72 uint32_t psw_o;
73 uint32_t psw_s;
74 uint32_t psw_z;
75 uint32_t psw_c;
76 uint32_t psw_u;
77 uint32_t psw_i;
78 uint32_t psw_pm;
79 uint32_t psw_ipl;
80 uint32_t bpsw;
81 uint32_t bpc;
82 uint32_t isp;
83 uint32_t usp;
84 uint32_t pc;
85 uint32_t intb;
86 uint32_t fintv;
87 uint32_t fpsw;
88 uint64_t acc;
89
90
91 struct {} end_reset_fields;
92
93
94 uint32_t in_sleep;
95 uint32_t req_irq;
96 uint32_t req_ipl;
97 uint32_t ack_irq;
98 uint32_t ack_ipl;
99 float_status fp_status;
100 qemu_irq ack;
101} CPURXState;
102
103
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105
106
107
108
109struct RXCPU {
110
111 CPUState parent_obj;
112
113
114 CPUNegativeOffsetState neg;
115 CPURXState env;
116};
117
118typedef RXCPU ArchCPU;
119
120#define ENV_OFFSET offsetof(RXCPU, env)
121
122#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
123#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
124#define CPU_RESOLVING_TYPE TYPE_RX_CPU
125
126const char *rx_crname(uint8_t cr);
127void rx_cpu_do_interrupt(CPUState *cpu);
128bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
129void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
130int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
131int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
132hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
133
134void rx_translate_init(void);
135int cpu_rx_signal_handler(int host_signum, void *pinfo,
136 void *puc);
137
138void rx_cpu_list(void);
139void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
140
141#define cpu_signal_handler cpu_rx_signal_handler
142#define cpu_list rx_cpu_list
143
144#include "exec/cpu-all.h"
145
146#define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0
147#define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1
148
149#define RX_CPU_IRQ 0
150#define RX_CPU_FIR 1
151
152static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc,
153 target_ulong *cs_base, uint32_t *flags)
154{
155 *pc = env->pc;
156 *cs_base = 0;
157 *flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
158}
159
160static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
161{
162 return 0;
163}
164
165static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
166{
167 uint32_t psw = 0;
168 psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl);
169 psw = FIELD_DP32(psw, PSW, PM, env->psw_pm);
170 psw = FIELD_DP32(psw, PSW, U, env->psw_u);
171 psw = FIELD_DP32(psw, PSW, I, env->psw_i);
172 psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31);
173 psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31);
174 psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0);
175 psw = FIELD_DP32(psw, PSW, C, env->psw_c);
176 return psw;
177}
178
179#endif
180