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20#ifndef SH4_CPU_H
21#define SH4_CPU_H
22
23#include "cpu-qom.h"
24#include "exec/cpu-defs.h"
25
26
27#define SH_CPU_SH7750 (1 << 0)
28#define SH_CPU_SH7750S (1 << 1)
29#define SH_CPU_SH7750R (1 << 2)
30#define SH_CPU_SH7751 (1 << 3)
31#define SH_CPU_SH7751R (1 << 4)
32#define SH_CPU_SH7785 (1 << 5)
33#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
34#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
35
36#define SR_MD 30
37#define SR_RB 29
38#define SR_BL 28
39#define SR_FD 15
40#define SR_M 9
41#define SR_Q 8
42#define SR_I3 7
43#define SR_I2 6
44#define SR_I1 5
45#define SR_I0 4
46#define SR_S 1
47#define SR_T 0
48
49#define FPSCR_MASK (0x003fffff)
50#define FPSCR_FR (1 << 21)
51#define FPSCR_SZ (1 << 20)
52#define FPSCR_PR (1 << 19)
53#define FPSCR_DN (1 << 18)
54#define FPSCR_CAUSE_MASK (0x3f << 12)
55#define FPSCR_CAUSE_SHIFT (12)
56#define FPSCR_CAUSE_E (1 << 17)
57#define FPSCR_CAUSE_V (1 << 16)
58#define FPSCR_CAUSE_Z (1 << 15)
59#define FPSCR_CAUSE_O (1 << 14)
60#define FPSCR_CAUSE_U (1 << 13)
61#define FPSCR_CAUSE_I (1 << 12)
62#define FPSCR_ENABLE_MASK (0x1f << 7)
63#define FPSCR_ENABLE_SHIFT (7)
64#define FPSCR_ENABLE_V (1 << 11)
65#define FPSCR_ENABLE_Z (1 << 10)
66#define FPSCR_ENABLE_O (1 << 9)
67#define FPSCR_ENABLE_U (1 << 8)
68#define FPSCR_ENABLE_I (1 << 7)
69#define FPSCR_FLAG_MASK (0x1f << 2)
70#define FPSCR_FLAG_SHIFT (2)
71#define FPSCR_FLAG_V (1 << 6)
72#define FPSCR_FLAG_Z (1 << 5)
73#define FPSCR_FLAG_O (1 << 4)
74#define FPSCR_FLAG_U (1 << 3)
75#define FPSCR_FLAG_I (1 << 2)
76#define FPSCR_RM_MASK (0x03 << 0)
77#define FPSCR_RM_NEAREST (0 << 0)
78#define FPSCR_RM_ZERO (1 << 0)
79
80#define DELAY_SLOT_MASK 0x7
81#define DELAY_SLOT (1 << 0)
82#define DELAY_SLOT_CONDITIONAL (1 << 1)
83#define DELAY_SLOT_RTE (1 << 2)
84
85#define TB_FLAG_PENDING_MOVCA (1 << 3)
86
87#define GUSA_SHIFT 4
88#ifdef CONFIG_USER_ONLY
89#define GUSA_EXCLUSIVE (1 << 12)
90#define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
91#else
92
93
94#define GUSA_EXCLUSIVE 0
95#define GUSA_MASK 0
96#endif
97
98#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK)
99
100typedef struct tlb_t {
101 uint32_t vpn;
102 uint32_t ppn;
103 uint32_t size;
104 uint8_t asid;
105 uint8_t v:1;
106 uint8_t sz:2;
107 uint8_t sh:1;
108 uint8_t c:1;
109 uint8_t pr:2;
110 uint8_t d:1;
111 uint8_t wt:1;
112 uint8_t sa:3;
113 uint8_t tc:1;
114} tlb_t;
115
116#define UTLB_SIZE 64
117#define ITLB_SIZE 4
118
119#define TARGET_INSN_START_EXTRA_WORDS 1
120
121enum sh_features {
122 SH_FEATURE_SH4A = 1,
123 SH_FEATURE_BCR3_AND_BCR4 = 2,
124};
125
126typedef struct memory_content {
127 uint32_t address;
128 uint32_t value;
129 struct memory_content *next;
130} memory_content;
131
132typedef struct CPUSH4State {
133 uint32_t flags;
134 uint32_t gregs[24];
135 float32 fregs[32];
136 uint32_t sr;
137 uint32_t sr_m;
138 uint32_t sr_q;
139 uint32_t sr_t;
140 uint32_t ssr;
141 uint32_t spc;
142 uint32_t gbr;
143 uint32_t vbr;
144 uint32_t sgr;
145 uint32_t dbr;
146 uint32_t pc;
147 uint32_t delayed_pc;
148 uint32_t delayed_cond;
149 uint32_t mach;
150 uint32_t macl;
151 uint32_t pr;
152 uint32_t fpscr;
153 uint32_t fpul;
154
155
156 float_status fp_status;
157
158
159 uint32_t mmucr;
160 uint32_t pteh;
161 uint32_t ptel;
162 uint32_t ptea;
163 uint32_t ttb;
164 uint32_t tea;
165 uint32_t tra;
166 uint32_t expevt;
167 uint32_t intevt;
168
169 tlb_t itlb[ITLB_SIZE];
170 tlb_t utlb[UTLB_SIZE];
171
172
173 uint32_t lock_addr;
174 uint32_t lock_value;
175
176
177 struct {} end_reset_fields;
178
179
180 int id;
181
182
183 uint32_t features;
184
185 void *intc_handle;
186 int in_sleep;
187 memory_content *movcal_backup;
188 memory_content **movcal_backup_tail;
189} CPUSH4State;
190
191
192
193
194
195
196
197struct SuperHCPU {
198
199 CPUState parent_obj;
200
201
202 CPUNegativeOffsetState neg;
203 CPUSH4State env;
204};
205
206
207void superh_cpu_do_interrupt(CPUState *cpu);
208bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
209void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
210hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
211int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
212int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
213void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
214 MMUAccessType access_type,
215 int mmu_idx, uintptr_t retaddr);
216
217void sh4_translate_init(void);
218int cpu_sh4_signal_handler(int host_signum, void *pinfo,
219 void *puc);
220bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
221 MMUAccessType access_type, int mmu_idx,
222 bool probe, uintptr_t retaddr);
223
224void sh4_cpu_list(void);
225#if !defined(CONFIG_USER_ONLY)
226void cpu_sh4_invalidate_tlb(CPUSH4State *s);
227uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
228 hwaddr addr);
229void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
230 uint32_t mem_value);
231uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
232 hwaddr addr);
233void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
234 uint32_t mem_value);
235uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
236 hwaddr addr);
237void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
238 uint32_t mem_value);
239uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
240 hwaddr addr);
241void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
242 uint32_t mem_value);
243#endif
244
245int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
246
247void cpu_load_tlb(CPUSH4State * env);
248
249#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
250#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
251#define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
252
253#define cpu_signal_handler cpu_sh4_signal_handler
254#define cpu_list sh4_cpu_list
255
256
257#define MMU_USER_IDX 1
258static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
259{
260
261
262 if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
263 return 0;
264 } else {
265 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
266 }
267}
268
269typedef CPUSH4State CPUArchState;
270typedef SuperHCPU ArchCPU;
271
272#include "exec/cpu-all.h"
273
274
275#define MMUCR 0x1F000010
276#define MMUCR_AT (1<<0)
277#define MMUCR_TI (1<<2)
278#define MMUCR_SV (1<<8)
279#define MMUCR_URC_BITS (6)
280#define MMUCR_URC_OFFSET (10)
281#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
282#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
283static inline int cpu_mmucr_urc (uint32_t mmucr)
284{
285 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
286}
287
288
289#define PTEH_ASID_BITS (8)
290#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
291#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
292#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
293#define PTEH_VPN_BITS (22)
294#define PTEH_VPN_OFFSET (10)
295#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
296#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
297static inline int cpu_pteh_vpn (uint32_t pteh)
298{
299 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
300}
301
302
303#define PTEL_V (1 << 8)
304#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
305#define PTEL_C (1 << 3)
306#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
307#define PTEL_D (1 << 2)
308#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
309#define PTEL_SH (1 << 1)
310#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
311#define PTEL_WT (1 << 0)
312#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
313
314#define PTEL_SZ_HIGH_OFFSET (7)
315#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
316#define PTEL_SZ_LOW_OFFSET (4)
317#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
318static inline int cpu_ptel_sz (uint32_t ptel)
319{
320 int sz;
321 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
322 sz <<= 1;
323 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
324 return sz;
325}
326
327#define PTEL_PPN_BITS (19)
328#define PTEL_PPN_OFFSET (10)
329#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
330#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
331static inline int cpu_ptel_ppn (uint32_t ptel)
332{
333 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
334}
335
336#define PTEL_PR_BITS (2)
337#define PTEL_PR_OFFSET (5)
338#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
339#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
340static inline int cpu_ptel_pr (uint32_t ptel)
341{
342 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
343}
344
345
346#define PTEA_SA_BITS (3)
347#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
348#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
349#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
350#define PTEA_TC (1 << 3)
351#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
352
353static inline target_ulong cpu_read_sr(CPUSH4State *env)
354{
355 return env->sr | (env->sr_m << SR_M) |
356 (env->sr_q << SR_Q) |
357 (env->sr_t << SR_T);
358}
359
360static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
361{
362 env->sr_m = (sr >> SR_M) & 1;
363 env->sr_q = (sr >> SR_Q) & 1;
364 env->sr_t = (sr >> SR_T) & 1;
365 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
366}
367
368static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
369 target_ulong *cs_base, uint32_t *flags)
370{
371 *pc = env->pc;
372
373 *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
374 *flags = env->flags
375 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))
376 | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))
377 | (env->sr & (1u << SR_FD))
378 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0);
379}
380
381#endif
382