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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "hw/pci/pci_bridge.h"
24#include "hw/pci/pcie.h"
25#include "hw/pci/msix.h"
26#include "hw/pci/msi.h"
27#include "hw/pci/pci_bus.h"
28#include "hw/pci/pcie_regs.h"
29#include "hw/pci/pcie_port.h"
30#include "qemu/range.h"
31
32
33#ifdef DEBUG_PCIE
34# define PCIE_DPRINTF(fmt, ...) \
35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
36#else
37# define PCIE_DPRINTF(fmt, ...) do {} while (0)
38#endif
39#define PCIE_DEV_PRINTF(dev, fmt, ...) \
40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
41
42
43
44
45
46
47static void
48pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version)
49{
50 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
51 uint8_t *cmask = dev->cmask + dev->exp.exp_cap;
52
53
54
55 pci_set_word(exp_cap + PCI_EXP_FLAGS,
56 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
57 version);
58
59
60
61
62
63
64
65
66 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
67
68 pci_set_long(exp_cap + PCI_EXP_LNKCAP,
69 (port << PCI_EXP_LNKCAP_PN_SHIFT) |
70 PCI_EXP_LNKCAP_ASPMS_0S |
71 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) |
72 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT));
73
74 pci_set_word(exp_cap + PCI_EXP_LNKSTA,
75 QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) |
76 QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT));
77
78
79
80
81
82 pci_set_word(cmask + PCI_EXP_LNKSTA, 0);
83}
84
85static void pcie_cap_fill_slot_lnk(PCIDevice *dev)
86{
87 PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT);
88 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
89
90
91 if (!s) {
92 return;
93 }
94
95
96 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP,
97 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS);
98 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
99 QEMU_PCI_EXP_LNKCAP_MLW(s->width) |
100 QEMU_PCI_EXP_LNKCAP_MLS(s->speed));
101
102
103
104
105
106
107 if (s->width > QEMU_PCI_EXP_LNK_X1 ||
108 s->speed > QEMU_PCI_EXP_LNK_2_5GT) {
109 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
110 PCI_EXP_LNKCAP_LBNC);
111 }
112
113 if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) {
114
115
116
117
118
119
120
121 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
122 PCI_EXP_LNKCAP_DLLLARC);
123
124
125
126
127
128
129 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2,
130 PCI_EXP_LNKCTL2_TLS);
131 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2,
132 QEMU_PCI_EXP_LNKCAP_MLS(s->speed) &
133 PCI_EXP_LNKCTL2_TLS);
134 }
135
136
137
138
139
140
141 if (s->speed > QEMU_PCI_EXP_LNK_5GT) {
142 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U);
143 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
144 PCI_EXP_LNKCAP2_SLS_2_5GB |
145 PCI_EXP_LNKCAP2_SLS_5_0GB |
146 PCI_EXP_LNKCAP2_SLS_8_0GB);
147 if (s->speed > QEMU_PCI_EXP_LNK_8GT) {
148 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
149 PCI_EXP_LNKCAP2_SLS_16_0GB);
150 }
151 }
152}
153
154int pcie_cap_init(PCIDevice *dev, uint8_t offset,
155 uint8_t type, uint8_t port,
156 Error **errp)
157{
158
159 int pos;
160 uint8_t *exp_cap;
161
162 assert(pci_is_express(dev));
163
164 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
165 PCI_EXP_VER2_SIZEOF, errp);
166 if (pos < 0) {
167 return pos;
168 }
169 dev->exp.exp_cap = pos;
170 exp_cap = dev->config + pos;
171
172
173 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2);
174
175
176 pcie_cap_fill_slot_lnk(dev);
177
178
179 pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
180 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
181
182 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
183
184 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
185
186 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
187 }
188
189 return pos;
190}
191
192int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
193 uint8_t port)
194{
195
196 int pos;
197 Error *local_err = NULL;
198
199 assert(pci_is_express(dev));
200
201 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
202 PCI_EXP_VER1_SIZEOF, &local_err);
203 if (pos < 0) {
204 error_report_err(local_err);
205 return pos;
206 }
207 dev->exp.exp_cap = pos;
208
209 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1);
210
211 return pos;
212}
213
214static int
215pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
216{
217 uint8_t type = PCI_EXP_TYPE_ENDPOINT;
218 Error *local_err = NULL;
219 int ret;
220
221
222
223
224
225
226 if (pci_bus_is_express(pci_get_bus(dev))
227 && pci_bus_is_root(pci_get_bus(dev))) {
228 type = PCI_EXP_TYPE_RC_END;
229 }
230
231 if (cap_size == PCI_EXP_VER1_SIZEOF) {
232 return pcie_cap_v1_init(dev, offset, type, 0);
233 } else {
234 ret = pcie_cap_init(dev, offset, type, 0, &local_err);
235
236 if (ret < 0) {
237 error_report_err(local_err);
238 }
239
240 return ret;
241 }
242}
243
244int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
245{
246 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF);
247}
248
249int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset)
250{
251 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF);
252}
253
254void pcie_cap_exit(PCIDevice *dev)
255{
256 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
257}
258
259void pcie_cap_v1_exit(PCIDevice *dev)
260{
261 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF);
262}
263
264uint8_t pcie_cap_get_type(const PCIDevice *dev)
265{
266 uint32_t pos = dev->exp.exp_cap;
267 assert(pos > 0);
268 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
269 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
270}
271
272
273
274
275void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
276{
277 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
278 assert(vector < 32);
279 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
280 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
281 vector << PCI_EXP_FLAGS_IRQ_SHIFT);
282}
283
284uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
285{
286 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
287 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
288}
289
290void pcie_cap_deverr_init(PCIDevice *dev)
291{
292 uint32_t pos = dev->exp.exp_cap;
293 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
294 PCI_EXP_DEVCAP_RBER);
295 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
296 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
297 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
298 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
299 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
300 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
301}
302
303void pcie_cap_deverr_reset(PCIDevice *dev)
304{
305 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
306 pci_long_test_and_clear_mask(devctl,
307 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
308 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
309}
310
311void pcie_cap_lnkctl_init(PCIDevice *dev)
312{
313 uint32_t pos = dev->exp.exp_cap;
314 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL,
315 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
316}
317
318void pcie_cap_lnkctl_reset(PCIDevice *dev)
319{
320 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL;
321 pci_long_test_and_clear_mask(lnkctl,
322 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
323}
324
325static void hotplug_event_update_event_status(PCIDevice *dev)
326{
327 uint32_t pos = dev->exp.exp_cap;
328 uint8_t *exp_cap = dev->config + pos;
329 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
330 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
331
332 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
333 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
334}
335
336static void hotplug_event_notify(PCIDevice *dev)
337{
338 bool prev = dev->exp.hpev_notified;
339
340 hotplug_event_update_event_status(dev);
341
342 if (prev == dev->exp.hpev_notified) {
343 return;
344 }
345
346
347
348
349
350
351
352 if (msix_enabled(dev)) {
353 msix_notify(dev, pcie_cap_flags_get_vector(dev));
354 } else if (msi_enabled(dev)) {
355 msi_notify(dev, pcie_cap_flags_get_vector(dev));
356 } else {
357 pci_set_irq(dev, dev->exp.hpev_notified);
358 }
359}
360
361static void hotplug_event_clear(PCIDevice *dev)
362{
363 hotplug_event_update_event_status(dev);
364 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
365 pci_irq_deassert(dev);
366 }
367}
368
369
370
371
372
373
374
375
376static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
377{
378
379 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
380 PCI_EXP_SLTSTA, event) == event) {
381 return;
382 }
383 hotplug_event_notify(dev);
384}
385
386static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev,
387 Error **errp)
388{
389 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
390 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
391
392 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta);
393 if (sltsta & PCI_EXP_SLTSTA_EIS) {
394
395
396
397 error_setg_errno(errp, EBUSY, "slot is electromechanically locked");
398 }
399}
400
401void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
402 Error **errp)
403{
404 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
405 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
406 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP);
407
408
409 if (dev->hotplugged && (sltcap & PCI_EXP_SLTCAP_HPC) == 0) {
410 error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'",
411 DEVICE(hotplug_pdev)->id);
412 return;
413 }
414
415 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp);
416}
417
418void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
419 Error **errp)
420{
421 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
422 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
423 PCIDevice *pci_dev = PCI_DEVICE(dev);
424 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP);
425
426
427
428
429 if (!dev->hotplugged) {
430 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
431 PCI_EXP_SLTSTA_PDS);
432 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA ||
433 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) {
434 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
435 PCI_EXP_LNKSTA_DLLLA);
436 }
437 return;
438 }
439
440
441
442
443
444 if (pci_get_function_0(pci_dev)) {
445 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
446 PCI_EXP_SLTSTA_PDS);
447 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA ||
448 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) {
449 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
450 PCI_EXP_LNKSTA_DLLLA);
451 }
452 pcie_cap_slot_event(hotplug_pdev,
453 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
454 }
455}
456
457void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
458 Error **errp)
459{
460 qdev_unrealize(dev);
461}
462
463static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
464{
465 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev));
466
467 if (dev->partially_hotplugged) {
468 dev->qdev.pending_deleted_event = false;
469 return;
470 }
471 hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort);
472 object_unparent(OBJECT(dev));
473}
474
475void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
476 DeviceState *dev, Error **errp)
477{
478 Error *local_err = NULL;
479 PCIDevice *pci_dev = PCI_DEVICE(dev);
480 PCIBus *bus = pci_get_bus(pci_dev);
481 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
482 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
483 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP);
484
485
486 if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) {
487 error_setg(errp, "Hot-unplug failed: "
488 "unsupported by the port device '%s'",
489 DEVICE(hotplug_pdev)->id);
490 return;
491 }
492
493 pcie_cap_slot_plug_common(hotplug_pdev, dev, &local_err);
494 if (local_err) {
495 error_propagate(errp, local_err);
496 return;
497 }
498
499 dev->pending_deleted_event = true;
500
501
502
503
504
505 if (pci_dev->devfn &&
506 !bus->devices[0]) {
507 pcie_unplug_device(bus, pci_dev, NULL);
508
509 return;
510 }
511
512 pcie_cap_slot_push_attention_button(hotplug_pdev);
513}
514
515
516
517void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)
518{
519 uint32_t pos = dev->exp.exp_cap;
520
521 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
522 PCI_EXP_FLAGS_SLOT);
523
524 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
525 ~PCI_EXP_SLTCAP_PSN);
526 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
527 (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
528 PCI_EXP_SLTCAP_EIP |
529 PCI_EXP_SLTCAP_PIP |
530 PCI_EXP_SLTCAP_AIP |
531 PCI_EXP_SLTCAP_ABP);
532
533
534
535
536
537 if (s->hotplug &&
538 (s->native_hotplug || DEVICE(dev)->hotplugged)) {
539 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
540 PCI_EXP_SLTCAP_HPS |
541 PCI_EXP_SLTCAP_HPC);
542 }
543
544 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
545 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
546 PCI_EXP_SLTCAP_PCP);
547 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
548 PCI_EXP_SLTCTL_PCC);
549 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
550 PCI_EXP_SLTCTL_PCC);
551 }
552
553 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
554 PCI_EXP_SLTCTL_PIC |
555 PCI_EXP_SLTCTL_AIC);
556 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
557 PCI_EXP_SLTCTL_PIC_OFF |
558 PCI_EXP_SLTCTL_AIC_OFF);
559 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
560 PCI_EXP_SLTCTL_PIC |
561 PCI_EXP_SLTCTL_AIC |
562 PCI_EXP_SLTCTL_HPIE |
563 PCI_EXP_SLTCTL_CCIE |
564 PCI_EXP_SLTCTL_PDCE |
565 PCI_EXP_SLTCTL_ABPE);
566
567
568
569
570
571 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
572 PCI_EXP_SLTCTL_EIC);
573
574 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
575 PCI_EXP_HP_EV_SUPPORTED);
576
577 dev->exp.hpev_notified = false;
578
579 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))),
580 OBJECT(dev));
581}
582
583void pcie_cap_slot_reset(PCIDevice *dev)
584{
585 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
586 uint8_t port_type = pcie_cap_get_type(dev);
587
588 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
589 port_type == PCI_EXP_TYPE_ROOT_PORT);
590
591 PCIE_DEV_PRINTF(dev, "reset\n");
592
593 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
594 PCI_EXP_SLTCTL_EIC |
595 PCI_EXP_SLTCTL_PIC |
596 PCI_EXP_SLTCTL_AIC |
597 PCI_EXP_SLTCTL_HPIE |
598 PCI_EXP_SLTCTL_CCIE |
599 PCI_EXP_SLTCTL_PDCE |
600 PCI_EXP_SLTCTL_ABPE);
601 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
602 PCI_EXP_SLTCTL_AIC_OFF);
603
604 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
605
606 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
607 uint16_t pic;
608
609 if (populated) {
610 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
611 PCI_EXP_SLTCTL_PCC);
612 } else {
613 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
614 PCI_EXP_SLTCTL_PCC);
615 }
616
617 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;
618 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
619 }
620
621 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
622 PCI_EXP_SLTSTA_EIS |
623
624 PCI_EXP_SLTSTA_CC |
625 PCI_EXP_SLTSTA_PDC |
626 PCI_EXP_SLTSTA_ABP);
627
628 hotplug_event_update_event_status(dev);
629}
630
631void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta)
632{
633 uint32_t pos = dev->exp.exp_cap;
634 uint8_t *exp_cap = dev->config + pos;
635 *slt_ctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
636 *slt_sta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
637}
638
639void pcie_cap_slot_write_config(PCIDevice *dev,
640 uint16_t old_slt_ctl, uint16_t old_slt_sta,
641 uint32_t addr, uint32_t val, int len)
642{
643 uint32_t pos = dev->exp.exp_cap;
644 uint8_t *exp_cap = dev->config + pos;
645 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
646 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP);
647
648 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
649
650
651
652
653
654
655
656
657
658
659
660#define PCIE_SLOT_EVENTS (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | \
661 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | \
662 PCI_EXP_SLTSTA_CC)
663
664 if (val & ~old_slt_sta & PCIE_SLOT_EVENTS) {
665 sltsta = (sltsta & ~PCIE_SLOT_EVENTS) | (old_slt_sta & PCIE_SLOT_EVENTS);
666 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
667 }
668 hotplug_event_clear(dev);
669 }
670
671 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
672 return;
673 }
674
675 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
676 PCI_EXP_SLTCTL_EIC)) {
677 sltsta ^= PCI_EXP_SLTSTA_EIS;
678 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
679 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
680 "sltsta -> 0x%02"PRIx16"\n",
681 sltsta);
682 }
683
684
685
686
687
688
689
690
691
692 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) &&
693 (val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF &&
694 (!(old_slt_ctl & PCI_EXP_SLTCTL_PCC) ||
695 (old_slt_ctl & PCI_EXP_SLTCTL_PIC_OFF) != PCI_EXP_SLTCTL_PIC_OFF)) {
696 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
697 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
698 pcie_unplug_device, NULL);
699
700 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
701 PCI_EXP_SLTSTA_PDS);
702 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA ||
703 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) {
704 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
705 PCI_EXP_LNKSTA_DLLLA);
706 }
707 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
708 PCI_EXP_SLTSTA_PDC);
709 }
710
711 hotplug_event_notify(dev);
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
730}
731
732int pcie_cap_slot_post_load(void *opaque, int version_id)
733{
734 PCIDevice *dev = opaque;
735 hotplug_event_update_event_status(dev);
736 return 0;
737}
738
739void pcie_cap_slot_push_attention_button(PCIDevice *dev)
740{
741 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
742}
743
744
745void pcie_cap_root_init(PCIDevice *dev)
746{
747 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
748 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
749 PCI_EXP_RTCTL_SEFEE);
750}
751
752void pcie_cap_root_reset(PCIDevice *dev)
753{
754 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
755}
756
757
758void pcie_cap_flr_init(PCIDevice *dev)
759{
760 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
761 PCI_EXP_DEVCAP_FLR);
762
763
764
765
766
767
768 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
769 PCI_EXP_DEVCTL_BCR_FLR);
770}
771
772void pcie_cap_flr_write_config(PCIDevice *dev,
773 uint32_t addr, uint32_t val, int len)
774{
775 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
776 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
777
778
779 pci_device_reset(dev);
780 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
781 }
782}
783
784
785
786
787void pcie_cap_arifwd_init(PCIDevice *dev)
788{
789 uint32_t pos = dev->exp.exp_cap;
790 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
791 PCI_EXP_DEVCAP2_ARI);
792 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
793 PCI_EXP_DEVCTL2_ARI);
794}
795
796void pcie_cap_arifwd_reset(PCIDevice *dev)
797{
798 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
799 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
800}
801
802bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)
803{
804 if (!pci_is_express(dev)) {
805 return false;
806 }
807 if (!dev->exp.exp_cap) {
808 return false;
809 }
810
811 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
812 PCI_EXP_DEVCTL2_ARI;
813}
814
815
816
817
818
819
820
821
822
823
824static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id,
825 uint16_t *prev_p)
826{
827 uint16_t prev = 0;
828 uint16_t next;
829 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
830
831 if (!header) {
832
833 next = 0;
834 goto out;
835 }
836 for (next = PCI_CONFIG_SPACE_SIZE; next;
837 prev = next, next = PCI_EXT_CAP_NEXT(header)) {
838
839 assert(next >= PCI_CONFIG_SPACE_SIZE);
840 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
841
842 header = pci_get_long(dev->config + next);
843 if (PCI_EXT_CAP_ID(header) == cap_id) {
844 break;
845 }
846 }
847
848out:
849 if (prev_p) {
850 *prev_p = prev;
851 }
852 return next;
853}
854
855uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
856{
857 return pcie_find_capability_list(dev, cap_id, NULL);
858}
859
860static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
861{
862 uint32_t header = pci_get_long(dev->config + pos);
863 assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
864 header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
865 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
866 pci_set_long(dev->config + pos, header);
867}
868
869
870
871
872
873
874void pcie_add_capability(PCIDevice *dev,
875 uint16_t cap_id, uint8_t cap_ver,
876 uint16_t offset, uint16_t size)
877{
878 assert(offset >= PCI_CONFIG_SPACE_SIZE);
879 assert(offset < offset + size);
880 assert(offset + size <= PCIE_CONFIG_SPACE_SIZE);
881 assert(size >= 8);
882 assert(pci_is_express(dev));
883
884 if (offset != PCI_CONFIG_SPACE_SIZE) {
885 uint16_t prev;
886
887
888
889
890
891 pcie_find_capability_list(dev, 0xffffffff, &prev);
892 assert(prev >= PCI_CONFIG_SPACE_SIZE);
893 pcie_ext_cap_set_next(dev, prev, offset);
894 }
895 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0));
896
897
898 memset(dev->wmask + offset, 0, size);
899 memset(dev->w1cmask + offset, 0, size);
900
901 memset(dev->cmask + offset, 0xFF, size);
902}
903
904
905
906
907
908
909
910
911
912
913
914void pcie_sync_bridge_lnk(PCIDevice *bridge_dev)
915{
916 PCIBridge *br = PCI_BRIDGE(bridge_dev);
917 PCIBus *bus = pci_bridge_get_sec_bus(br);
918 PCIDevice *target = bus->devices[0];
919 uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap;
920 uint16_t lnksta, lnkcap = pci_get_word(exp_cap + PCI_EXP_LNKCAP);
921
922 if (!target || !target->exp.exp_cap) {
923 lnksta = lnkcap;
924 } else {
925 lnksta = target->config_read(target,
926 target->exp.exp_cap + PCI_EXP_LNKSTA,
927 sizeof(lnksta));
928
929 if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) {
930 lnksta &= ~PCI_EXP_LNKSTA_NLW;
931 lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW;
932 } else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) {
933 lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1);
934 }
935
936 if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) {
937 lnksta &= ~PCI_EXP_LNKSTA_CLS;
938 lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS;
939 } else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) {
940 lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT);
941 }
942 }
943
944 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
945 PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW);
946 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta &
947 (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW));
948}
949
950
951
952
953
954
955void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
956{
957 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
958 offset, PCI_ARI_SIZEOF);
959 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);
960}
961
962void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num)
963{
964 static const int pci_dsn_ver = 1;
965 static const int pci_dsn_cap = 4;
966
967 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset,
968 PCI_EXT_CAP_DSN_SIZEOF);
969 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num);
970}
971
972void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned)
973{
974 pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1,
975 offset, PCI_EXT_CAP_ATS_SIZEOF);
976
977 dev->exp.ats_cap = offset;
978
979
980 if (aligned) {
981 pci_set_word(dev->config + offset + PCI_ATS_CAP,
982 PCI_ATS_CAP_PAGE_ALIGNED);
983 }
984
985 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0);
986
987 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f);
988}
989
990
991void pcie_acs_init(PCIDevice *dev, uint16_t offset)
992{
993 bool is_downstream = pci_is_express_downstream_port(dev);
994 uint16_t cap_bits = 0;
995
996
997 assert(is_downstream ||
998 (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) ||
999 PCI_FUNC(dev->devfn));
1000
1001 pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset,
1002 PCI_ACS_SIZEOF);
1003 dev->exp.acs_cap = offset;
1004
1005 if (is_downstream) {
1006
1007
1008
1009
1010
1011
1012
1013 cap_bits = PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
1014 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT;
1015 }
1016
1017 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits);
1018 pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits);
1019}
1020
1021void pcie_acs_reset(PCIDevice *dev)
1022{
1023 if (dev->exp.acs_cap) {
1024 pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0);
1025 }
1026}
1027