1#ifndef QEMU_PCI_H
2#define QEMU_PCI_H
3
4#include "exec/memory.h"
5#include "sysemu/dma.h"
6
7
8#include "hw/isa/isa.h"
9
10#include "hw/pci/pcie.h"
11#include "qom/object.h"
12
13extern bool pci_available;
14
15
16
17#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
19#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
20#define PCI_FUNC(devfn) ((devfn) & 0x07)
21#define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
22#define PCI_BUS_MAX 256
23#define PCI_DEVFN_MAX 256
24#define PCI_SLOT_MAX 32
25#define PCI_FUNC_MAX 8
26
27
28#include "hw/pci/pci_ids.h"
29
30
31
32
33#define PCI_DEVICE_ID_IBM_440GX 0x027f
34#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
35
36
37#define PCI_VENDOR_ID_HITACHI 0x1054
38#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
39
40
41#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
42#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
43#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
44#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
45#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
46
47
48#define PCI_DEVICE_ID_REALTEK_8029 0x8029
49
50
51#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
52
53
54#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
55
56
57#define PCI_VENDOR_ID_QEMU 0x1234
58#define PCI_DEVICE_ID_QEMU_VGA 0x1111
59#define PCI_DEVICE_ID_QEMU_IPMI 0x1112
60
61
62#define PCI_VENDOR_ID_VMWARE 0x15ad
63#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
64#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
65#define PCI_DEVICE_ID_VMWARE_NET 0x0720
66#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
67#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
68#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
69#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
70
71
72#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
73#define PCI_DEVICE_ID_INTEL_82557 0x1229
74#define PCI_DEVICE_ID_INTEL_82801IR 0x2922
75
76
77#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
78#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
79#define PCI_SUBDEVICE_ID_QEMU 0x1100
80
81#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
82#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
83#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
84#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
85#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
86#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
87#define PCI_DEVICE_ID_VIRTIO_9P 0x1009
88#define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
89#define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013
90#define PCI_DEVICE_ID_VIRTIO_IOMMU 0x1014
91#define PCI_DEVICE_ID_VIRTIO_MEM 0x1015
92
93#define PCI_VENDOR_ID_REDHAT 0x1b36
94#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
95#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
96#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
97#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
98#define PCI_DEVICE_ID_REDHAT_TEST 0x0005
99#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
100#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
101#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
102#define PCI_DEVICE_ID_REDHAT_PXB 0x0009
103#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
104#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
105#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
106#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
107#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
108#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
109#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
110#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
111#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
112
113#define FMT_PCIBUS PRIx64
114
115typedef uint64_t pcibus_t;
116
117struct PCIHostDeviceAddress {
118 unsigned int domain;
119 unsigned int bus;
120 unsigned int slot;
121 unsigned int function;
122};
123
124typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
125 uint32_t address, uint32_t data, int len);
126typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
127 uint32_t address, int len);
128typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
129 pcibus_t addr, pcibus_t size, int type);
130typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
131
132typedef struct PCIIORegion {
133 pcibus_t addr;
134#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
135 pcibus_t size;
136 uint8_t type;
137 MemoryRegion *memory;
138 MemoryRegion *address_space;
139} PCIIORegion;
140
141#define PCI_ROM_SLOT 6
142#define PCI_NUM_REGIONS 7
143
144enum {
145 QEMU_PCI_VGA_MEM,
146 QEMU_PCI_VGA_IO_LO,
147 QEMU_PCI_VGA_IO_HI,
148 QEMU_PCI_VGA_NUM_REGIONS,
149};
150
151#define QEMU_PCI_VGA_MEM_BASE 0xa0000
152#define QEMU_PCI_VGA_MEM_SIZE 0x20000
153#define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
154#define QEMU_PCI_VGA_IO_LO_SIZE 0xc
155#define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
156#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
157
158#include "hw/pci/pci_regs.h"
159
160
161#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
162
163
164#define PCI_CONFIG_HEADER_SIZE 0x40
165
166#define PCI_CONFIG_SPACE_SIZE 0x100
167
168#define PCIE_CONFIG_SPACE_SIZE 0x1000
169
170#define PCI_NUM_PINS 4
171
172
173enum {
174 QEMU_PCI_CAP_MSI = 0x1,
175 QEMU_PCI_CAP_MSIX = 0x2,
176 QEMU_PCI_CAP_EXPRESS = 0x4,
177
178
179#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
180 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
181
182
183#define QEMU_PCI_CAP_SERR_BITNR 4
184 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
185
186#define QEMU_PCI_SHPC_BITNR 5
187 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
188#define QEMU_PCI_SLOTID_BITNR 6
189 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
190
191#define QEMU_PCIE_SLTCAP_PCP_BITNR 7
192 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
193
194#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
195 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
196#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
197 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
198};
199
200#define TYPE_PCI_DEVICE "pci-device"
201typedef struct PCIDeviceClass PCIDeviceClass;
202DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
203 PCI_DEVICE, TYPE_PCI_DEVICE)
204
205
206#define INTERFACE_PCIE_DEVICE "pci-express-device"
207
208
209#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
210
211typedef struct PCIINTxRoute {
212 enum {
213 PCI_INTX_ENABLED,
214 PCI_INTX_INVERTED,
215 PCI_INTX_DISABLED,
216 } mode;
217 int irq;
218} PCIINTxRoute;
219
220struct PCIDeviceClass {
221 DeviceClass parent_class;
222
223 void (*realize)(PCIDevice *dev, Error **errp);
224 PCIUnregisterFunc *exit;
225 PCIConfigReadFunc *config_read;
226 PCIConfigWriteFunc *config_write;
227
228 uint16_t vendor_id;
229 uint16_t device_id;
230 uint8_t revision;
231 uint16_t class_id;
232 uint16_t subsystem_vendor_id;
233 uint16_t subsystem_id;
234
235
236
237
238
239
240 bool is_bridge;
241
242
243 const char *romfile;
244};
245
246typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
247typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
248 MSIMessage msg);
249typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
250typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
251 unsigned int vector_start,
252 unsigned int vector_end);
253
254enum PCIReqIDType {
255 PCI_REQ_ID_INVALID = 0,
256 PCI_REQ_ID_BDF,
257 PCI_REQ_ID_SECONDARY_BUS,
258 PCI_REQ_ID_MAX,
259};
260typedef enum PCIReqIDType PCIReqIDType;
261
262struct PCIReqIDCache {
263 PCIDevice *dev;
264 PCIReqIDType type;
265};
266typedef struct PCIReqIDCache PCIReqIDCache;
267
268struct PCIDevice {
269 DeviceState qdev;
270 bool partially_hotplugged;
271
272
273 uint8_t *config;
274
275
276
277 uint8_t *cmask;
278
279
280 uint8_t *wmask;
281
282
283 uint8_t *w1cmask;
284
285
286 uint8_t *used;
287
288
289 int32_t devfn;
290
291
292
293
294 PCIReqIDCache requester_id_cache;
295 char name[64];
296 PCIIORegion io_regions[PCI_NUM_REGIONS];
297 AddressSpace bus_master_as;
298 MemoryRegion bus_master_container_region;
299 MemoryRegion bus_master_enable_region;
300
301
302 PCIConfigReadFunc *config_read;
303 PCIConfigWriteFunc *config_write;
304
305
306 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
307 bool has_vga;
308
309
310 uint8_t irq_state;
311
312
313 uint32_t cap_present;
314
315
316 uint8_t msix_cap;
317
318
319 int msix_entries_nr;
320
321
322 uint8_t *msix_table;
323 uint8_t *msix_pba;
324
325 MemoryRegion msix_exclusive_bar;
326
327 MemoryRegion msix_table_mmio;
328 MemoryRegion msix_pba_mmio;
329
330 unsigned *msix_entry_used;
331
332 bool msix_function_masked;
333
334 int32_t version_id;
335
336
337 uint8_t msi_cap;
338
339
340 PCIExpressDevice exp;
341
342
343 SHPCDevice *shpc;
344
345
346 char *romfile;
347 uint32_t romsize;
348 bool has_rom;
349 MemoryRegion rom;
350 uint32_t rom_bar;
351
352
353 PCIINTxRoutingNotifier intx_routing_notifier;
354
355
356 MSIVectorUseNotifier msix_vector_use_notifier;
357 MSIVectorReleaseNotifier msix_vector_release_notifier;
358 MSIVectorPollNotifier msix_vector_poll_notifier;
359
360
361 char *failover_pair_id;
362 uint32_t acpi_index;
363};
364
365void pci_register_bar(PCIDevice *pci_dev, int region_num,
366 uint8_t attr, MemoryRegion *memory);
367void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
368 MemoryRegion *io_lo, MemoryRegion *io_hi);
369void pci_unregister_vga(PCIDevice *pci_dev);
370pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
371
372int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
373 uint8_t offset, uint8_t size,
374 Error **errp);
375
376void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
377
378uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
379
380
381uint32_t pci_default_read_config(PCIDevice *d,
382 uint32_t address, int len);
383void pci_default_write_config(PCIDevice *d,
384 uint32_t address, uint32_t val, int len);
385void pci_device_save(PCIDevice *s, QEMUFile *f);
386int pci_device_load(PCIDevice *s, QEMUFile *f);
387MemoryRegion *pci_address_space(PCIDevice *dev);
388MemoryRegion *pci_address_space_io(PCIDevice *dev);
389
390
391
392
393
394int pci_bar(PCIDevice *d, int reg);
395
396typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
397typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
398typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
399
400#define TYPE_PCI_BUS "PCI"
401OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
402#define TYPE_PCIE_BUS "PCIE"
403
404bool pci_bus_is_express(PCIBus *bus);
405
406void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
407 const char *name,
408 MemoryRegion *address_space_mem,
409 MemoryRegion *address_space_io,
410 uint8_t devfn_min, const char *typename);
411PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
412 MemoryRegion *address_space_mem,
413 MemoryRegion *address_space_io,
414 uint8_t devfn_min, const char *typename);
415void pci_root_bus_cleanup(PCIBus *bus);
416void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
417 void *irq_opaque, int nirq);
418void pci_bus_irqs_cleanup(PCIBus *bus);
419int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
420
421static inline int pci_swizzle(int slot, int pin)
422{
423 return (slot + pin) % PCI_NUM_PINS;
424}
425int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
426PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
427 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
428 void *irq_opaque,
429 MemoryRegion *address_space_mem,
430 MemoryRegion *address_space_io,
431 uint8_t devfn_min, int nirq,
432 const char *typename);
433void pci_unregister_root_bus(PCIBus *bus);
434void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
435PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
436bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
437void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
438void pci_device_set_intx_routing_notifier(PCIDevice *dev,
439 PCIINTxRoutingNotifier notifier);
440void pci_device_reset(PCIDevice *dev);
441
442PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
443 const char *default_model,
444 const char *default_devaddr);
445
446PCIDevice *pci_vga_init(PCIBus *bus);
447
448static inline PCIBus *pci_get_bus(const PCIDevice *dev)
449{
450 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
451}
452int pci_bus_num(PCIBus *s);
453void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
454static inline int pci_dev_bus_num(const PCIDevice *dev)
455{
456 return pci_bus_num(pci_get_bus(dev));
457}
458
459int pci_bus_numa_node(PCIBus *bus);
460void pci_for_each_device(PCIBus *bus, int bus_num,
461 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
462 void *opaque);
463void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
464 void (*fn)(PCIBus *bus, PCIDevice *d,
465 void *opaque),
466 void *opaque);
467void pci_for_each_bus_depth_first(PCIBus *bus,
468 void *(*begin)(PCIBus *bus, void *parent_state),
469 void (*end)(PCIBus *bus, void *state),
470 void *parent_state);
471PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
472
473
474static inline
475void pci_for_each_bus(PCIBus *bus,
476 void (*fn)(PCIBus *bus, void *opaque),
477 void *opaque)
478{
479 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
480}
481
482PCIBus *pci_device_root_bus(const PCIDevice *d);
483const char *pci_root_bus_path(PCIDevice *dev);
484bool pci_bus_bypass_iommu(PCIBus *bus);
485PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
486int pci_qdev_find_device(const char *id, PCIDevice **pdev);
487void pci_bus_get_w64_range(PCIBus *bus, Range *range);
488
489void pci_device_deassert_intx(PCIDevice *dev);
490
491typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
492
493AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
494void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
495
496static inline void
497pci_set_byte(uint8_t *config, uint8_t val)
498{
499 *config = val;
500}
501
502static inline uint8_t
503pci_get_byte(const uint8_t *config)
504{
505 return *config;
506}
507
508static inline void
509pci_set_word(uint8_t *config, uint16_t val)
510{
511 stw_le_p(config, val);
512}
513
514static inline uint16_t
515pci_get_word(const uint8_t *config)
516{
517 return lduw_le_p(config);
518}
519
520static inline void
521pci_set_long(uint8_t *config, uint32_t val)
522{
523 stl_le_p(config, val);
524}
525
526static inline uint32_t
527pci_get_long(const uint8_t *config)
528{
529 return ldl_le_p(config);
530}
531
532
533
534
535
536
537
538
539static inline void
540pci_set_quad(uint8_t *config, uint64_t val)
541{
542 stq_le_p(config, val);
543}
544
545static inline uint64_t
546pci_get_quad(const uint8_t *config)
547{
548 return ldq_le_p(config);
549}
550
551static inline void
552pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
553{
554 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
555}
556
557static inline void
558pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
559{
560 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
561}
562
563static inline void
564pci_config_set_revision(uint8_t *pci_config, uint8_t val)
565{
566 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
567}
568
569static inline void
570pci_config_set_class(uint8_t *pci_config, uint16_t val)
571{
572 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
573}
574
575static inline void
576pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
577{
578 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
579}
580
581static inline void
582pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
583{
584 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
585}
586
587
588
589
590
591
592
593static inline uint8_t
594pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
595{
596 uint8_t val = pci_get_byte(config);
597 pci_set_byte(config, val & ~mask);
598 return val & mask;
599}
600
601static inline uint8_t
602pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
603{
604 uint8_t val = pci_get_byte(config);
605 pci_set_byte(config, val | mask);
606 return val & mask;
607}
608
609static inline uint16_t
610pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
611{
612 uint16_t val = pci_get_word(config);
613 pci_set_word(config, val & ~mask);
614 return val & mask;
615}
616
617static inline uint16_t
618pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
619{
620 uint16_t val = pci_get_word(config);
621 pci_set_word(config, val | mask);
622 return val & mask;
623}
624
625static inline uint32_t
626pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
627{
628 uint32_t val = pci_get_long(config);
629 pci_set_long(config, val & ~mask);
630 return val & mask;
631}
632
633static inline uint32_t
634pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
635{
636 uint32_t val = pci_get_long(config);
637 pci_set_long(config, val | mask);
638 return val & mask;
639}
640
641static inline uint64_t
642pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
643{
644 uint64_t val = pci_get_quad(config);
645 pci_set_quad(config, val & ~mask);
646 return val & mask;
647}
648
649static inline uint64_t
650pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
651{
652 uint64_t val = pci_get_quad(config);
653 pci_set_quad(config, val | mask);
654 return val & mask;
655}
656
657
658static inline void
659pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
660{
661 uint8_t val = pci_get_byte(config);
662 uint8_t rval = reg << ctz32(mask);
663 pci_set_byte(config, (~mask & val) | (mask & rval));
664}
665
666static inline uint8_t
667pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
668{
669 uint8_t val = pci_get_byte(config);
670 return (val & mask) >> ctz32(mask);
671}
672
673static inline void
674pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
675{
676 uint16_t val = pci_get_word(config);
677 uint16_t rval = reg << ctz32(mask);
678 pci_set_word(config, (~mask & val) | (mask & rval));
679}
680
681static inline uint16_t
682pci_get_word_by_mask(uint8_t *config, uint16_t mask)
683{
684 uint16_t val = pci_get_word(config);
685 return (val & mask) >> ctz32(mask);
686}
687
688static inline void
689pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
690{
691 uint32_t val = pci_get_long(config);
692 uint32_t rval = reg << ctz32(mask);
693 pci_set_long(config, (~mask & val) | (mask & rval));
694}
695
696static inline uint32_t
697pci_get_long_by_mask(uint8_t *config, uint32_t mask)
698{
699 uint32_t val = pci_get_long(config);
700 return (val & mask) >> ctz32(mask);
701}
702
703static inline void
704pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
705{
706 uint64_t val = pci_get_quad(config);
707 uint64_t rval = reg << ctz32(mask);
708 pci_set_quad(config, (~mask & val) | (mask & rval));
709}
710
711static inline uint64_t
712pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
713{
714 uint64_t val = pci_get_quad(config);
715 return (val & mask) >> ctz32(mask);
716}
717
718PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
719 const char *name);
720PCIDevice *pci_new(int devfn, const char *name);
721bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
722
723PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
724 bool multifunction,
725 const char *name);
726PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
727
728void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
729
730qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
731void pci_set_irq(PCIDevice *pci_dev, int level);
732
733static inline void pci_irq_assert(PCIDevice *pci_dev)
734{
735 pci_set_irq(pci_dev, 1);
736}
737
738static inline void pci_irq_deassert(PCIDevice *pci_dev)
739{
740 pci_set_irq(pci_dev, 0);
741}
742
743
744
745
746
747static inline void pci_irq_pulse(PCIDevice *pci_dev)
748{
749 pci_irq_assert(pci_dev);
750 pci_irq_deassert(pci_dev);
751}
752
753static inline int pci_is_express(const PCIDevice *d)
754{
755 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
756}
757
758static inline int pci_is_express_downstream_port(const PCIDevice *d)
759{
760 uint8_t type;
761
762 if (!pci_is_express(d) || !d->exp.exp_cap) {
763 return 0;
764 }
765
766 type = pcie_cap_get_type(d);
767
768 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
769}
770
771static inline uint32_t pci_config_size(const PCIDevice *d)
772{
773 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
774}
775
776static inline uint16_t pci_get_bdf(PCIDevice *dev)
777{
778 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
779}
780
781uint16_t pci_requester_id(PCIDevice *dev);
782
783
784static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
785{
786 return &dev->bus_master_as;
787}
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
803 void *buf, dma_addr_t len,
804 DMADirection dir)
805{
806 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
807}
808
809
810
811
812
813
814
815
816
817
818
819
820
821static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
822 void *buf, dma_addr_t len)
823{
824 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
825}
826
827
828
829
830
831
832
833
834
835
836
837
838
839static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
840 const void *buf, dma_addr_t len)
841{
842 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
843}
844
845#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
846 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
847 dma_addr_t addr) \
848 { \
849 return ld##_l##_dma(pci_get_address_space(dev), addr); \
850 } \
851 static inline void st##_s##_pci_dma(PCIDevice *dev, \
852 dma_addr_t addr, uint##_bits##_t val) \
853 { \
854 st##_s##_dma(pci_get_address_space(dev), addr, val); \
855 }
856
857PCI_DMA_DEFINE_LDST(ub, b, 8);
858PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
859PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
860PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
861PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
862PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
863PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
864
865#undef PCI_DMA_DEFINE_LDST
866
867static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
868 dma_addr_t *plen, DMADirection dir)
869{
870 void *buf;
871
872 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
873 return buf;
874}
875
876static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
877 DMADirection dir, dma_addr_t access_len)
878{
879 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
880}
881
882static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
883 int alloc_hint)
884{
885 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
886}
887
888extern const VMStateDescription vmstate_pci_device;
889
890#define VMSTATE_PCI_DEVICE(_field, _state) { \
891 .name = (stringify(_field)), \
892 .size = sizeof(PCIDevice), \
893 .vmsd = &vmstate_pci_device, \
894 .flags = VMS_STRUCT, \
895 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
896}
897
898#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
899 .name = (stringify(_field)), \
900 .size = sizeof(PCIDevice), \
901 .vmsd = &vmstate_pci_device, \
902 .flags = VMS_STRUCT|VMS_POINTER, \
903 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
904}
905
906MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
907
908#endif
909