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21#include "qemu/osdep.h"
22#include "qemu/qemu-print.h"
23#include "qemu-common.h"
24#include "target/arm/idau.h"
25#include "qemu/module.h"
26#include "qapi/error.h"
27#include "qapi/visitor.h"
28#include "cpu.h"
29#ifdef CONFIG_TCG
30#include "hw/core/tcg-cpu-ops.h"
31#endif
32#include "internals.h"
33#include "exec/exec-all.h"
34#include "hw/qdev-properties.h"
35#if !defined(CONFIG_USER_ONLY)
36#include "hw/loader.h"
37#include "hw/boards.h"
38#endif
39#include "sysemu/tcg.h"
40#include "sysemu/hw_accel.h"
41#include "kvm_arm.h"
42#include "disas/capstone.h"
43#include "fpu/softfloat.h"
44
45static void arm_cpu_set_pc(CPUState *cs, vaddr value)
46{
47 ARMCPU *cpu = ARM_CPU(cs);
48 CPUARMState *env = &cpu->env;
49
50 if (is_a64(env)) {
51 env->pc = value;
52 env->thumb = 0;
53 } else {
54 env->regs[15] = value & ~1;
55 env->thumb = value & 1;
56 }
57}
58
59#ifdef CONFIG_TCG
60void arm_cpu_synchronize_from_tb(CPUState *cs,
61 const TranslationBlock *tb)
62{
63 ARMCPU *cpu = ARM_CPU(cs);
64 CPUARMState *env = &cpu->env;
65
66
67
68
69
70 if (is_a64(env)) {
71 env->pc = tb->pc;
72 } else {
73 env->regs[15] = tb->pc;
74 }
75}
76#endif
77
78static bool arm_cpu_has_work(CPUState *cs)
79{
80 ARMCPU *cpu = ARM_CPU(cs);
81
82 return (cpu->power_state != PSCI_OFF)
83 && cs->interrupt_request &
84 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
85 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
86 | CPU_INTERRUPT_EXITTB);
87}
88
89void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
90 void *opaque)
91{
92 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
93
94 entry->hook = hook;
95 entry->opaque = opaque;
96
97 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
98}
99
100void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
101 void *opaque)
102{
103 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
104
105 entry->hook = hook;
106 entry->opaque = opaque;
107
108 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
109}
110
111static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
112{
113
114 ARMCPRegInfo *ri = value;
115 ARMCPU *cpu = opaque;
116
117 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
118 return;
119 }
120
121 if (ri->resetfn) {
122 ri->resetfn(&cpu->env, ri);
123 return;
124 }
125
126
127
128
129
130
131 if (!ri->fieldoffset) {
132 return;
133 }
134
135 if (cpreg_field_is_64bit(ri)) {
136 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
137 } else {
138 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
139 }
140}
141
142static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
143{
144
145
146
147
148
149 ARMCPRegInfo *ri = value;
150 ARMCPU *cpu = opaque;
151 uint64_t oldvalue, newvalue;
152
153 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
154 return;
155 }
156
157 oldvalue = read_raw_cp_reg(&cpu->env, ri);
158 cp_reg_reset(key, value, opaque);
159 newvalue = read_raw_cp_reg(&cpu->env, ri);
160 assert(oldvalue == newvalue);
161}
162
163static void arm_cpu_reset(DeviceState *dev)
164{
165 CPUState *s = CPU(dev);
166 ARMCPU *cpu = ARM_CPU(s);
167 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
168 CPUARMState *env = &cpu->env;
169
170 acc->parent_reset(dev);
171
172 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
173
174 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
175 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
176
177 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
178 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
179 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
180 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
181
182 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON;
183
184 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
185 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
186 }
187
188 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
189
190 env->aarch64 = 1;
191#if defined(CONFIG_USER_ONLY)
192 env->pstate = PSTATE_MODE_EL0t;
193
194 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
195
196 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
197 SCTLR_EnDA | SCTLR_EnDB);
198
199 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
200
201 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
202
203 if (cpu_isar_feature(aa64_sve, cpu)) {
204 env->vfp.zcr_el[1] =
205 aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
206 }
207
208
209
210
211 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37);
212
213
214 if (cpu_isar_feature(aa64_mte, cpu)) {
215
216 env->cp15.sctlr_el[1] |= SCTLR_ATA0;
217
218
219
220
221
222
223
224
225 env->cp15.gcr_el1 = 0x1ffff;
226 }
227#else
228
229 if (arm_feature(env, ARM_FEATURE_EL3)) {
230 env->pstate = PSTATE_MODE_EL3h;
231 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
232 env->pstate = PSTATE_MODE_EL2h;
233 } else {
234 env->pstate = PSTATE_MODE_EL1h;
235 }
236 env->pc = cpu->rvbar;
237#endif
238 } else {
239#if defined(CONFIG_USER_ONLY)
240
241 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
242#endif
243 }
244
245#if defined(CONFIG_USER_ONLY)
246 env->uncached_cpsr = ARM_CPU_MODE_USR;
247
248 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
249 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
250 env->cp15.c15_cpar = 3;
251 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
252 env->cp15.c15_cpar = 1;
253 }
254#else
255
256
257
258
259
260
261 if (arm_feature(env, ARM_FEATURE_EL2) &&
262 !arm_feature(env, ARM_FEATURE_EL3)) {
263 env->uncached_cpsr = ARM_CPU_MODE_HYP;
264 } else {
265 env->uncached_cpsr = ARM_CPU_MODE_SVC;
266 }
267 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
268#endif
269
270 if (arm_feature(env, ARM_FEATURE_M)) {
271#ifndef CONFIG_USER_ONLY
272 uint32_t initial_msp;
273 uint32_t initial_pc;
274 uint8_t *rom;
275 uint32_t vecbase;
276#endif
277
278 if (cpu_isar_feature(aa32_lob, cpu)) {
279
280
281
282
283
284 env->v7m.ltpsize = 4;
285
286 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
287 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
288 }
289
290 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
291 env->v7m.secure = true;
292 } else {
293
294
295
296
297
298 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
299
300
301
302
303
304
305
306 env->v7m.nsacr = 0xcff;
307 }
308
309
310
311
312
313 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
314 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
315 if (arm_feature(env, ARM_FEATURE_V8)) {
316
317 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
318 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
319 }
320 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
321 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
322 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
323 }
324
325 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
326 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
327 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
328 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
329 }
330
331#ifndef CONFIG_USER_ONLY
332
333 env->regs[14] = 0xffffffff;
334
335 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
336 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80;
337
338
339 vecbase = env->v7m.vecbase[env->v7m.secure];
340 rom = rom_ptr_for_as(s->as, vecbase, 8);
341 if (rom) {
342
343
344
345 initial_msp = ldl_p(rom);
346 initial_pc = ldl_p(rom + 4);
347 } else {
348
349
350
351
352
353 initial_msp = ldl_phys(s->as, vecbase);
354 initial_pc = ldl_phys(s->as, vecbase + 4);
355 }
356
357 env->regs[13] = initial_msp & 0xFFFFFFFC;
358 env->regs[15] = initial_pc & ~1;
359 env->thumb = initial_pc & 1;
360#else
361
362
363
364
365
366 env->v7m.secure = false;
367 env->v7m.nsacr = 0xcff;
368 env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
369 env->v7m.fpccr[M_REG_S] &=
370 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
371 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
372#endif
373 }
374
375#ifndef CONFIG_USER_ONLY
376
377
378
379
380 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
381 env->regs[15] = 0xFFFF0000;
382 }
383
384
385
386
387
388 arm_clear_exclusive(env);
389
390 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
391#endif
392
393 if (arm_feature(env, ARM_FEATURE_PMSA)) {
394 if (cpu->pmsav7_dregion > 0) {
395 if (arm_feature(env, ARM_FEATURE_V8)) {
396 memset(env->pmsav8.rbar[M_REG_NS], 0,
397 sizeof(*env->pmsav8.rbar[M_REG_NS])
398 * cpu->pmsav7_dregion);
399 memset(env->pmsav8.rlar[M_REG_NS], 0,
400 sizeof(*env->pmsav8.rlar[M_REG_NS])
401 * cpu->pmsav7_dregion);
402 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
403 memset(env->pmsav8.rbar[M_REG_S], 0,
404 sizeof(*env->pmsav8.rbar[M_REG_S])
405 * cpu->pmsav7_dregion);
406 memset(env->pmsav8.rlar[M_REG_S], 0,
407 sizeof(*env->pmsav8.rlar[M_REG_S])
408 * cpu->pmsav7_dregion);
409 }
410 } else if (arm_feature(env, ARM_FEATURE_V7)) {
411 memset(env->pmsav7.drbar, 0,
412 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
413 memset(env->pmsav7.drsr, 0,
414 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
415 memset(env->pmsav7.dracr, 0,
416 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
417 }
418 }
419 env->pmsav7.rnr[M_REG_NS] = 0;
420 env->pmsav7.rnr[M_REG_S] = 0;
421 env->pmsav8.mair0[M_REG_NS] = 0;
422 env->pmsav8.mair0[M_REG_S] = 0;
423 env->pmsav8.mair1[M_REG_NS] = 0;
424 env->pmsav8.mair1[M_REG_S] = 0;
425 }
426
427 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
428 if (cpu->sau_sregion > 0) {
429 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
430 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
431 }
432 env->sau.rnr = 0;
433
434
435
436 env->sau.ctrl = 0;
437 }
438
439 set_flush_to_zero(1, &env->vfp.standard_fp_status);
440 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
441 set_default_nan_mode(1, &env->vfp.standard_fp_status);
442 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
443 set_float_detect_tininess(float_tininess_before_rounding,
444 &env->vfp.fp_status);
445 set_float_detect_tininess(float_tininess_before_rounding,
446 &env->vfp.standard_fp_status);
447 set_float_detect_tininess(float_tininess_before_rounding,
448 &env->vfp.fp_status_f16);
449 set_float_detect_tininess(float_tininess_before_rounding,
450 &env->vfp.standard_fp_status_f16);
451#ifndef CONFIG_USER_ONLY
452 if (kvm_enabled()) {
453 kvm_arm_reset_vcpu(cpu);
454 }
455#endif
456
457 hw_breakpoint_update_all(cpu);
458 hw_watchpoint_update_all(cpu);
459 arm_rebuild_hflags(env);
460}
461
462static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
463 unsigned int target_el,
464 unsigned int cur_el, bool secure,
465 uint64_t hcr_el2)
466{
467 CPUARMState *env = cs->env_ptr;
468 bool pstate_unmasked;
469 bool unmasked = false;
470
471
472
473
474
475
476 if (cur_el > target_el) {
477 return false;
478 }
479
480 switch (excp_idx) {
481 case EXCP_FIQ:
482 pstate_unmasked = !(env->daif & PSTATE_F);
483 break;
484
485 case EXCP_IRQ:
486 pstate_unmasked = !(env->daif & PSTATE_I);
487 break;
488
489 case EXCP_VFIQ:
490 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
491
492 return false;
493 }
494 return !(env->daif & PSTATE_F);
495 case EXCP_VIRQ:
496 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
497
498 return false;
499 }
500 return !(env->daif & PSTATE_I);
501 default:
502 g_assert_not_reached();
503 }
504
505
506
507
508
509
510 if ((target_el > cur_el) && (target_el != 1)) {
511
512 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
513
514
515
516
517
518
519 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) {
520 unmasked = true;
521 }
522 } else {
523
524
525
526
527
528 bool hcr, scr;
529
530 switch (excp_idx) {
531 case EXCP_FIQ:
532
533
534
535
536
537
538
539 hcr = hcr_el2 & HCR_FMO;
540 scr = (env->cp15.scr_el3 & SCR_FIQ);
541
542
543
544
545
546
547
548 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
549 break;
550 case EXCP_IRQ:
551
552
553
554
555
556
557
558 hcr = hcr_el2 & HCR_IMO;
559 scr = false;
560 break;
561 default:
562 g_assert_not_reached();
563 }
564
565 if ((scr || hcr) && !secure) {
566 unmasked = true;
567 }
568 }
569 }
570
571
572
573
574
575 return unmasked || pstate_unmasked;
576}
577
578bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
579{
580 CPUClass *cc = CPU_GET_CLASS(cs);
581 CPUARMState *env = cs->env_ptr;
582 uint32_t cur_el = arm_current_el(env);
583 bool secure = arm_is_secure(env);
584 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
585 uint32_t target_el;
586 uint32_t excp_idx;
587
588
589
590 if (interrupt_request & CPU_INTERRUPT_FIQ) {
591 excp_idx = EXCP_FIQ;
592 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
593 if (arm_excp_unmasked(cs, excp_idx, target_el,
594 cur_el, secure, hcr_el2)) {
595 goto found;
596 }
597 }
598 if (interrupt_request & CPU_INTERRUPT_HARD) {
599 excp_idx = EXCP_IRQ;
600 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
601 if (arm_excp_unmasked(cs, excp_idx, target_el,
602 cur_el, secure, hcr_el2)) {
603 goto found;
604 }
605 }
606 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
607 excp_idx = EXCP_VIRQ;
608 target_el = 1;
609 if (arm_excp_unmasked(cs, excp_idx, target_el,
610 cur_el, secure, hcr_el2)) {
611 goto found;
612 }
613 }
614 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
615 excp_idx = EXCP_VFIQ;
616 target_el = 1;
617 if (arm_excp_unmasked(cs, excp_idx, target_el,
618 cur_el, secure, hcr_el2)) {
619 goto found;
620 }
621 }
622 return false;
623
624 found:
625 cs->exception_index = excp_idx;
626 env->exception.target_el = target_el;
627 cc->tcg_ops->do_interrupt(cs);
628 return true;
629}
630
631void arm_cpu_update_virq(ARMCPU *cpu)
632{
633
634
635
636
637 CPUARMState *env = &cpu->env;
638 CPUState *cs = CPU(cpu);
639
640 bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
641 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
642
643 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
644 if (new_state) {
645 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
646 } else {
647 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
648 }
649 }
650}
651
652void arm_cpu_update_vfiq(ARMCPU *cpu)
653{
654
655
656
657
658 CPUARMState *env = &cpu->env;
659 CPUState *cs = CPU(cpu);
660
661 bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
662 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
663
664 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
665 if (new_state) {
666 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
667 } else {
668 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
669 }
670 }
671}
672
673#ifndef CONFIG_USER_ONLY
674static void arm_cpu_set_irq(void *opaque, int irq, int level)
675{
676 ARMCPU *cpu = opaque;
677 CPUARMState *env = &cpu->env;
678 CPUState *cs = CPU(cpu);
679 static const int mask[] = {
680 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
681 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
682 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
683 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
684 };
685
686 if (level) {
687 env->irq_line_state |= mask[irq];
688 } else {
689 env->irq_line_state &= ~mask[irq];
690 }
691
692 switch (irq) {
693 case ARM_CPU_VIRQ:
694 assert(arm_feature(env, ARM_FEATURE_EL2));
695 arm_cpu_update_virq(cpu);
696 break;
697 case ARM_CPU_VFIQ:
698 assert(arm_feature(env, ARM_FEATURE_EL2));
699 arm_cpu_update_vfiq(cpu);
700 break;
701 case ARM_CPU_IRQ:
702 case ARM_CPU_FIQ:
703 if (level) {
704 cpu_interrupt(cs, mask[irq]);
705 } else {
706 cpu_reset_interrupt(cs, mask[irq]);
707 }
708 break;
709 default:
710 g_assert_not_reached();
711 }
712}
713
714static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
715{
716#ifdef CONFIG_KVM
717 ARMCPU *cpu = opaque;
718 CPUARMState *env = &cpu->env;
719 CPUState *cs = CPU(cpu);
720 uint32_t linestate_bit;
721 int irq_id;
722
723 switch (irq) {
724 case ARM_CPU_IRQ:
725 irq_id = KVM_ARM_IRQ_CPU_IRQ;
726 linestate_bit = CPU_INTERRUPT_HARD;
727 break;
728 case ARM_CPU_FIQ:
729 irq_id = KVM_ARM_IRQ_CPU_FIQ;
730 linestate_bit = CPU_INTERRUPT_FIQ;
731 break;
732 default:
733 g_assert_not_reached();
734 }
735
736 if (level) {
737 env->irq_line_state |= linestate_bit;
738 } else {
739 env->irq_line_state &= ~linestate_bit;
740 }
741 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
742#endif
743}
744
745static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
746{
747 ARMCPU *cpu = ARM_CPU(cs);
748 CPUARMState *env = &cpu->env;
749
750 cpu_synchronize_state(cs);
751 return arm_cpu_data_is_big_endian(env);
752}
753
754#endif
755
756static int
757print_insn_thumb1(bfd_vma pc, disassemble_info *info)
758{
759 return print_insn_arm(pc | 1, info);
760}
761
762static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
763{
764 ARMCPU *ac = ARM_CPU(cpu);
765 CPUARMState *env = &ac->env;
766 bool sctlr_b;
767
768 if (is_a64(env)) {
769
770
771
772
773#if defined(CONFIG_ARM_A64_DIS)
774 info->print_insn = print_insn_arm_a64;
775#endif
776 info->cap_arch = CS_ARCH_ARM64;
777 info->cap_insn_unit = 4;
778 info->cap_insn_split = 4;
779 } else {
780 int cap_mode;
781 if (env->thumb) {
782 info->print_insn = print_insn_thumb1;
783 info->cap_insn_unit = 2;
784 info->cap_insn_split = 4;
785 cap_mode = CS_MODE_THUMB;
786 } else {
787 info->print_insn = print_insn_arm;
788 info->cap_insn_unit = 4;
789 info->cap_insn_split = 4;
790 cap_mode = CS_MODE_ARM;
791 }
792 if (arm_feature(env, ARM_FEATURE_V8)) {
793 cap_mode |= CS_MODE_V8;
794 }
795 if (arm_feature(env, ARM_FEATURE_M)) {
796 cap_mode |= CS_MODE_MCLASS;
797 }
798 info->cap_arch = CS_ARCH_ARM;
799 info->cap_mode = cap_mode;
800 }
801
802 sctlr_b = arm_sctlr_b(env);
803 if (bswap_code(sctlr_b)) {
804#ifdef TARGET_WORDS_BIGENDIAN
805 info->endian = BFD_ENDIAN_LITTLE;
806#else
807 info->endian = BFD_ENDIAN_BIG;
808#endif
809 }
810 info->flags &= ~INSN_ARM_BE32;
811#ifndef CONFIG_USER_ONLY
812 if (sctlr_b) {
813 info->flags |= INSN_ARM_BE32;
814 }
815#endif
816}
817
818#ifdef TARGET_AARCH64
819
820static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
821{
822 ARMCPU *cpu = ARM_CPU(cs);
823 CPUARMState *env = &cpu->env;
824 uint32_t psr = pstate_read(env);
825 int i;
826 int el = arm_current_el(env);
827 const char *ns_status;
828
829 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
830 for (i = 0; i < 32; i++) {
831 if (i == 31) {
832 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
833 } else {
834 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
835 (i + 2) % 3 ? " " : "\n");
836 }
837 }
838
839 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
840 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
841 } else {
842 ns_status = "";
843 }
844 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
845 psr,
846 psr & PSTATE_N ? 'N' : '-',
847 psr & PSTATE_Z ? 'Z' : '-',
848 psr & PSTATE_C ? 'C' : '-',
849 psr & PSTATE_V ? 'V' : '-',
850 ns_status,
851 el,
852 psr & PSTATE_SP ? 'h' : 't');
853
854 if (cpu_isar_feature(aa64_bti, cpu)) {
855 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
856 }
857 if (!(flags & CPU_DUMP_FPU)) {
858 qemu_fprintf(f, "\n");
859 return;
860 }
861 if (fp_exception_el(env, el) != 0) {
862 qemu_fprintf(f, " FPU disabled\n");
863 return;
864 }
865 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
866 vfp_get_fpcr(env), vfp_get_fpsr(env));
867
868 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
869 int j, zcr_len = sve_zcr_len_for_el(env, el);
870
871 for (i = 0; i <= FFR_PRED_NUM; i++) {
872 bool eol;
873 if (i == FFR_PRED_NUM) {
874 qemu_fprintf(f, "FFR=");
875
876 eol = true;
877 } else {
878 qemu_fprintf(f, "P%02d=", i);
879 switch (zcr_len) {
880 case 0:
881 eol = i % 8 == 7;
882 break;
883 case 1:
884 eol = i % 6 == 5;
885 break;
886 case 2:
887 case 3:
888 eol = i % 3 == 2;
889 break;
890 default:
891
892 eol = true;
893 break;
894 }
895 }
896 for (j = zcr_len / 4; j >= 0; j--) {
897 int digits;
898 if (j * 4 + 4 <= zcr_len + 1) {
899 digits = 16;
900 } else {
901 digits = (zcr_len % 4 + 1) * 4;
902 }
903 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
904 env->vfp.pregs[i].p[j],
905 j ? ":" : eol ? "\n" : " ");
906 }
907 }
908
909 for (i = 0; i < 32; i++) {
910 if (zcr_len == 0) {
911 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
912 i, env->vfp.zregs[i].d[1],
913 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
914 } else if (zcr_len == 1) {
915 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
916 ":%016" PRIx64 ":%016" PRIx64 "\n",
917 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
918 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
919 } else {
920 for (j = zcr_len; j >= 0; j--) {
921 bool odd = (zcr_len - j) % 2 != 0;
922 if (j == zcr_len) {
923 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
924 } else if (!odd) {
925 if (j > 0) {
926 qemu_fprintf(f, " [%x-%x]=", j, j - 1);
927 } else {
928 qemu_fprintf(f, " [%x]=", j);
929 }
930 }
931 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
932 env->vfp.zregs[i].d[j * 2 + 1],
933 env->vfp.zregs[i].d[j * 2],
934 odd || j == 0 ? "\n" : ":");
935 }
936 }
937 }
938 } else {
939 for (i = 0; i < 32; i++) {
940 uint64_t *q = aa64_vfp_qreg(env, i);
941 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
942 i, q[1], q[0], (i & 1 ? "\n" : " "));
943 }
944 }
945}
946
947#else
948
949static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
950{
951 g_assert_not_reached();
952}
953
954#endif
955
956static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
957{
958 ARMCPU *cpu = ARM_CPU(cs);
959 CPUARMState *env = &cpu->env;
960 int i;
961
962 if (is_a64(env)) {
963 aarch64_cpu_dump_state(cs, f, flags);
964 return;
965 }
966
967 for (i = 0; i < 16; i++) {
968 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
969 if ((i % 4) == 3) {
970 qemu_fprintf(f, "\n");
971 } else {
972 qemu_fprintf(f, " ");
973 }
974 }
975
976 if (arm_feature(env, ARM_FEATURE_M)) {
977 uint32_t xpsr = xpsr_read(env);
978 const char *mode;
979 const char *ns_status = "";
980
981 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
982 ns_status = env->v7m.secure ? "S " : "NS ";
983 }
984
985 if (xpsr & XPSR_EXCP) {
986 mode = "handler";
987 } else {
988 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
989 mode = "unpriv-thread";
990 } else {
991 mode = "priv-thread";
992 }
993 }
994
995 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
996 xpsr,
997 xpsr & XPSR_N ? 'N' : '-',
998 xpsr & XPSR_Z ? 'Z' : '-',
999 xpsr & XPSR_C ? 'C' : '-',
1000 xpsr & XPSR_V ? 'V' : '-',
1001 xpsr & XPSR_T ? 'T' : 'A',
1002 ns_status,
1003 mode);
1004 } else {
1005 uint32_t psr = cpsr_read(env);
1006 const char *ns_status = "";
1007
1008 if (arm_feature(env, ARM_FEATURE_EL3) &&
1009 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
1010 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1011 }
1012
1013 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1014 psr,
1015 psr & CPSR_N ? 'N' : '-',
1016 psr & CPSR_Z ? 'Z' : '-',
1017 psr & CPSR_C ? 'C' : '-',
1018 psr & CPSR_V ? 'V' : '-',
1019 psr & CPSR_T ? 'T' : 'A',
1020 ns_status,
1021 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1022 }
1023
1024 if (flags & CPU_DUMP_FPU) {
1025 int numvfpregs = 0;
1026 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1027 numvfpregs = 32;
1028 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1029 numvfpregs = 16;
1030 }
1031 for (i = 0; i < numvfpregs; i++) {
1032 uint64_t v = *aa32_vfp_dreg(env, i);
1033 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1034 i * 2, (uint32_t)v,
1035 i * 2 + 1, (uint32_t)(v >> 32),
1036 i, v);
1037 }
1038 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1039 }
1040}
1041
1042uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
1043{
1044 uint32_t Aff1 = idx / clustersz;
1045 uint32_t Aff0 = idx % clustersz;
1046 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1047}
1048
1049static void cpreg_hashtable_data_destroy(gpointer data)
1050{
1051
1052
1053
1054
1055
1056
1057 ARMCPRegInfo *r = data;
1058
1059 g_free((void *)r->name);
1060 g_free(r);
1061}
1062
1063static void arm_cpu_initfn(Object *obj)
1064{
1065 ARMCPU *cpu = ARM_CPU(obj);
1066
1067 cpu_set_cpustate_pointers(cpu);
1068 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
1069 g_free, cpreg_hashtable_data_destroy);
1070
1071 QLIST_INIT(&cpu->pre_el_change_hooks);
1072 QLIST_INIT(&cpu->el_change_hooks);
1073
1074#ifdef CONFIG_USER_ONLY
1075# ifdef TARGET_AARCH64
1076
1077
1078
1079
1080
1081 cpu->sve_default_vq = 4;
1082# endif
1083#else
1084
1085 if (kvm_enabled()) {
1086
1087
1088
1089 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
1090 } else {
1091 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
1092 }
1093
1094 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1095 ARRAY_SIZE(cpu->gt_timer_outputs));
1096
1097 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1098 "gicv3-maintenance-interrupt", 1);
1099 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1100 "pmu-interrupt", 1);
1101#endif
1102
1103
1104
1105
1106
1107 cpu->dtb_compatible = "qemu,unknown";
1108 cpu->psci_version = 1;
1109 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1110
1111 if (tcg_enabled()) {
1112 cpu->psci_version = 2;
1113 }
1114}
1115
1116static Property arm_cpu_gt_cntfrq_property =
1117 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
1118 NANOSECONDS_PER_SECOND / GTIMER_SCALE);
1119
1120static Property arm_cpu_reset_cbar_property =
1121 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1122
1123static Property arm_cpu_reset_hivecs_property =
1124 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1125
1126static Property arm_cpu_rvbar_property =
1127 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
1128
1129#ifndef CONFIG_USER_ONLY
1130static Property arm_cpu_has_el2_property =
1131 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1132
1133static Property arm_cpu_has_el3_property =
1134 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1135#endif
1136
1137static Property arm_cpu_cfgend_property =
1138 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1139
1140static Property arm_cpu_has_vfp_property =
1141 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1142
1143static Property arm_cpu_has_neon_property =
1144 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1145
1146static Property arm_cpu_has_dsp_property =
1147 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1148
1149static Property arm_cpu_has_mpu_property =
1150 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1151
1152
1153
1154
1155
1156
1157static Property arm_cpu_pmsav7_dregion_property =
1158 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1159 pmsav7_dregion,
1160 qdev_prop_uint32, uint32_t);
1161
1162static bool arm_get_pmu(Object *obj, Error **errp)
1163{
1164 ARMCPU *cpu = ARM_CPU(obj);
1165
1166 return cpu->has_pmu;
1167}
1168
1169static void arm_set_pmu(Object *obj, bool value, Error **errp)
1170{
1171 ARMCPU *cpu = ARM_CPU(obj);
1172
1173 if (value) {
1174 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1175 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1176 return;
1177 }
1178 set_feature(&cpu->env, ARM_FEATURE_PMU);
1179 } else {
1180 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1181 }
1182 cpu->has_pmu = value;
1183}
1184
1185unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1186{
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1206 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1207}
1208
1209void arm_cpu_post_init(Object *obj)
1210{
1211 ARMCPU *cpu = ARM_CPU(obj);
1212
1213
1214
1215
1216
1217 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1218 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1219 }
1220
1221 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1222 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1223 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1224 }
1225
1226 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1227 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1228 }
1229
1230 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1231 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
1232 }
1233
1234#ifndef CONFIG_USER_ONLY
1235 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1236
1237
1238
1239 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1240
1241 object_property_add_link(obj, "secure-memory",
1242 TYPE_MEMORY_REGION,
1243 (Object **)&cpu->secure_memory,
1244 qdev_prop_allow_set_link_before_realize,
1245 OBJ_PROP_LINK_STRONG);
1246 }
1247
1248 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1249 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1250 }
1251#endif
1252
1253 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1254 cpu->has_pmu = true;
1255 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu);
1256 }
1257
1258
1259
1260
1261
1262
1263 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
1264 ? cpu_isar_feature(aa64_fp_simd, cpu)
1265 : cpu_isar_feature(aa32_vfp, cpu)) {
1266 cpu->has_vfp = true;
1267 if (!kvm_enabled()) {
1268 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
1269 }
1270 }
1271
1272 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1273 cpu->has_neon = true;
1274 if (!kvm_enabled()) {
1275 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1276 }
1277 }
1278
1279 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1280 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1281 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1282 }
1283
1284 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1285 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1286 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1287 qdev_property_add_static(DEVICE(obj),
1288 &arm_cpu_pmsav7_dregion_property);
1289 }
1290 }
1291
1292 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1293 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1294 qdev_prop_allow_set_link_before_realize,
1295 OBJ_PROP_LINK_STRONG);
1296
1297
1298
1299
1300
1301 object_property_add_uint32_ptr(obj, "init-svtor",
1302 &cpu->init_svtor,
1303 OBJ_PROP_FLAG_READWRITE);
1304 }
1305 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1306
1307
1308
1309
1310 object_property_add_uint32_ptr(obj, "init-nsvtor",
1311 &cpu->init_nsvtor,
1312 OBJ_PROP_FLAG_READWRITE);
1313 }
1314
1315 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1316
1317 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1318 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1319 }
1320
1321 if (kvm_enabled()) {
1322 kvm_arm_add_vcpu_properties(obj);
1323 }
1324
1325#ifndef CONFIG_USER_ONLY
1326 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
1327 cpu_isar_feature(aa64_mte, cpu)) {
1328 object_property_add_link(obj, "tag-memory",
1329 TYPE_MEMORY_REGION,
1330 (Object **)&cpu->tag_memory,
1331 qdev_prop_allow_set_link_before_realize,
1332 OBJ_PROP_LINK_STRONG);
1333
1334 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1335 object_property_add_link(obj, "secure-tag-memory",
1336 TYPE_MEMORY_REGION,
1337 (Object **)&cpu->secure_tag_memory,
1338 qdev_prop_allow_set_link_before_realize,
1339 OBJ_PROP_LINK_STRONG);
1340 }
1341 }
1342#endif
1343}
1344
1345static void arm_cpu_finalizefn(Object *obj)
1346{
1347 ARMCPU *cpu = ARM_CPU(obj);
1348 ARMELChangeHook *hook, *next;
1349
1350 g_hash_table_destroy(cpu->cp_regs);
1351
1352 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1353 QLIST_REMOVE(hook, node);
1354 g_free(hook);
1355 }
1356 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1357 QLIST_REMOVE(hook, node);
1358 g_free(hook);
1359 }
1360#ifndef CONFIG_USER_ONLY
1361 if (cpu->pmu_timer) {
1362 timer_free(cpu->pmu_timer);
1363 }
1364#endif
1365}
1366
1367void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1368{
1369 Error *local_err = NULL;
1370
1371 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1372 arm_cpu_sve_finalize(cpu, &local_err);
1373 if (local_err != NULL) {
1374 error_propagate(errp, local_err);
1375 return;
1376 }
1377
1378
1379
1380
1381
1382
1383 if (!kvm_enabled()) {
1384 arm_cpu_pauth_finalize(cpu, &local_err);
1385 if (local_err != NULL) {
1386 error_propagate(errp, local_err);
1387 return;
1388 }
1389 }
1390 }
1391
1392 if (kvm_enabled()) {
1393 kvm_arm_steal_time_finalize(cpu, &local_err);
1394 if (local_err != NULL) {
1395 error_propagate(errp, local_err);
1396 return;
1397 }
1398 }
1399}
1400
1401static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1402{
1403 CPUState *cs = CPU(dev);
1404 ARMCPU *cpu = ARM_CPU(dev);
1405 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1406 CPUARMState *env = &cpu->env;
1407 int pagebits;
1408 Error *local_err = NULL;
1409 bool no_aa32 = false;
1410
1411
1412
1413
1414
1415 if (cpu->host_cpu_probe_failed) {
1416 if (!kvm_enabled()) {
1417 error_setg(errp, "The 'host' CPU type can only be used with KVM");
1418 } else {
1419 error_setg(errp, "Failed to retrieve host CPU features");
1420 }
1421 return;
1422 }
1423
1424#ifndef CONFIG_USER_ONLY
1425
1426
1427
1428
1429 if (arm_feature(env, ARM_FEATURE_M)) {
1430 if (!env->nvic) {
1431 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1432 return;
1433 }
1434 } else {
1435 if (env->nvic) {
1436 error_setg(errp, "This board can only be used with Cortex-M CPUs");
1437 return;
1438 }
1439 }
1440
1441 {
1442 uint64_t scale;
1443
1444 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1445 if (!cpu->gt_cntfrq_hz) {
1446 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
1447 cpu->gt_cntfrq_hz);
1448 return;
1449 }
1450 scale = gt_cntfrq_period_ns(cpu);
1451 } else {
1452 scale = GTIMER_SCALE;
1453 }
1454
1455 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1456 arm_gt_ptimer_cb, cpu);
1457 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1458 arm_gt_vtimer_cb, cpu);
1459 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1460 arm_gt_htimer_cb, cpu);
1461 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1462 arm_gt_stimer_cb, cpu);
1463 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1464 arm_gt_hvtimer_cb, cpu);
1465 }
1466#endif
1467
1468 cpu_exec_realizefn(cs, &local_err);
1469 if (local_err != NULL) {
1470 error_propagate(errp, local_err);
1471 return;
1472 }
1473
1474 arm_cpu_finalize_features(cpu, &local_err);
1475 if (local_err != NULL) {
1476 error_propagate(errp, local_err);
1477 return;
1478 }
1479
1480 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1481 cpu->has_vfp != cpu->has_neon) {
1482
1483
1484
1485
1486 error_setg(errp,
1487 "AArch64 CPUs must have both VFP and Neon or neither");
1488 return;
1489 }
1490
1491 if (!cpu->has_vfp) {
1492 uint64_t t;
1493 uint32_t u;
1494
1495 t = cpu->isar.id_aa64isar1;
1496 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1497 cpu->isar.id_aa64isar1 = t;
1498
1499 t = cpu->isar.id_aa64pfr0;
1500 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
1501 cpu->isar.id_aa64pfr0 = t;
1502
1503 u = cpu->isar.id_isar6;
1504 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
1505 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
1506 cpu->isar.id_isar6 = u;
1507
1508 u = cpu->isar.mvfr0;
1509 u = FIELD_DP32(u, MVFR0, FPSP, 0);
1510 u = FIELD_DP32(u, MVFR0, FPDP, 0);
1511 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
1512 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
1513 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
1514 if (!arm_feature(env, ARM_FEATURE_M)) {
1515 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
1516 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
1517 }
1518 cpu->isar.mvfr0 = u;
1519
1520 u = cpu->isar.mvfr1;
1521 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
1522 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
1523 u = FIELD_DP32(u, MVFR1, FPHP, 0);
1524 if (arm_feature(env, ARM_FEATURE_M)) {
1525 u = FIELD_DP32(u, MVFR1, FP16, 0);
1526 }
1527 cpu->isar.mvfr1 = u;
1528
1529 u = cpu->isar.mvfr2;
1530 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
1531 cpu->isar.mvfr2 = u;
1532 }
1533
1534 if (!cpu->has_neon) {
1535 uint64_t t;
1536 uint32_t u;
1537
1538 unset_feature(env, ARM_FEATURE_NEON);
1539
1540 t = cpu->isar.id_aa64isar0;
1541 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
1542 cpu->isar.id_aa64isar0 = t;
1543
1544 t = cpu->isar.id_aa64isar1;
1545 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
1546 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
1547 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
1548 cpu->isar.id_aa64isar1 = t;
1549
1550 t = cpu->isar.id_aa64pfr0;
1551 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
1552 cpu->isar.id_aa64pfr0 = t;
1553
1554 u = cpu->isar.id_isar5;
1555 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
1556 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
1557 cpu->isar.id_isar5 = u;
1558
1559 u = cpu->isar.id_isar6;
1560 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
1561 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
1562 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
1563 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
1564 cpu->isar.id_isar6 = u;
1565
1566 if (!arm_feature(env, ARM_FEATURE_M)) {
1567 u = cpu->isar.mvfr1;
1568 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
1569 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
1570 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
1571 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
1572 cpu->isar.mvfr1 = u;
1573
1574 u = cpu->isar.mvfr2;
1575 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
1576 cpu->isar.mvfr2 = u;
1577 }
1578 }
1579
1580 if (!cpu->has_neon && !cpu->has_vfp) {
1581 uint64_t t;
1582 uint32_t u;
1583
1584 t = cpu->isar.id_aa64isar0;
1585 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
1586 cpu->isar.id_aa64isar0 = t;
1587
1588 t = cpu->isar.id_aa64isar1;
1589 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
1590 cpu->isar.id_aa64isar1 = t;
1591
1592 u = cpu->isar.mvfr0;
1593 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
1594 cpu->isar.mvfr0 = u;
1595
1596
1597 u = cpu->isar.mvfr1;
1598 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
1599 cpu->isar.mvfr1 = u;
1600 }
1601
1602 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
1603 uint32_t u;
1604
1605 unset_feature(env, ARM_FEATURE_THUMB_DSP);
1606
1607 u = cpu->isar.id_isar1;
1608 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
1609 cpu->isar.id_isar1 = u;
1610
1611 u = cpu->isar.id_isar2;
1612 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
1613 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
1614 cpu->isar.id_isar2 = u;
1615
1616 u = cpu->isar.id_isar3;
1617 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
1618 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
1619 cpu->isar.id_isar3 = u;
1620 }
1621
1622
1623 if (arm_feature(env, ARM_FEATURE_V8)) {
1624 if (arm_feature(env, ARM_FEATURE_M)) {
1625 set_feature(env, ARM_FEATURE_V7);
1626 } else {
1627 set_feature(env, ARM_FEATURE_V7VE);
1628 }
1629 }
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1640 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1641 }
1642
1643 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1644
1645
1646
1647
1648
1649
1650
1651
1652 assert(!tcg_enabled() || no_aa32 ||
1653 cpu_isar_feature(aa32_arm_div, cpu));
1654 set_feature(env, ARM_FEATURE_LPAE);
1655 set_feature(env, ARM_FEATURE_V7);
1656 }
1657 if (arm_feature(env, ARM_FEATURE_V7)) {
1658 set_feature(env, ARM_FEATURE_VAPA);
1659 set_feature(env, ARM_FEATURE_THUMB2);
1660 set_feature(env, ARM_FEATURE_MPIDR);
1661 if (!arm_feature(env, ARM_FEATURE_M)) {
1662 set_feature(env, ARM_FEATURE_V6K);
1663 } else {
1664 set_feature(env, ARM_FEATURE_V6);
1665 }
1666
1667
1668
1669
1670 set_feature(env, ARM_FEATURE_VBAR);
1671 }
1672 if (arm_feature(env, ARM_FEATURE_V6K)) {
1673 set_feature(env, ARM_FEATURE_V6);
1674 set_feature(env, ARM_FEATURE_MVFR);
1675 }
1676 if (arm_feature(env, ARM_FEATURE_V6)) {
1677 set_feature(env, ARM_FEATURE_V5);
1678 if (!arm_feature(env, ARM_FEATURE_M)) {
1679 assert(!tcg_enabled() || no_aa32 ||
1680 cpu_isar_feature(aa32_jazelle, cpu));
1681 set_feature(env, ARM_FEATURE_AUXCR);
1682 }
1683 }
1684 if (arm_feature(env, ARM_FEATURE_V5)) {
1685 set_feature(env, ARM_FEATURE_V4T);
1686 }
1687 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1688 set_feature(env, ARM_FEATURE_V7MP);
1689 }
1690 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1691 set_feature(env, ARM_FEATURE_CBAR);
1692 }
1693 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1694 !arm_feature(env, ARM_FEATURE_M)) {
1695 set_feature(env, ARM_FEATURE_THUMB_DSP);
1696 }
1697
1698
1699
1700
1701
1702 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
1703 !cpu_isar_feature(aa32_vfp_simd, cpu) ||
1704 !arm_feature(env, ARM_FEATURE_XSCALE));
1705
1706 if (arm_feature(env, ARM_FEATURE_V7) &&
1707 !arm_feature(env, ARM_FEATURE_M) &&
1708 !arm_feature(env, ARM_FEATURE_PMSA)) {
1709
1710
1711
1712 pagebits = 12;
1713 } else {
1714
1715
1716
1717 pagebits = 10;
1718 }
1719 if (!set_preferred_target_page_bits(pagebits)) {
1720
1721
1722
1723
1724 error_setg(errp, "This CPU requires a smaller page size than the "
1725 "system is using");
1726 return;
1727 }
1728
1729
1730
1731
1732
1733
1734 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
1735 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1736 ARM_DEFAULT_CPUS_PER_CLUSTER);
1737 }
1738
1739 if (cpu->reset_hivecs) {
1740 cpu->reset_sctlr |= (1 << 13);
1741 }
1742
1743 if (cpu->cfgend) {
1744 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1745 cpu->reset_sctlr |= SCTLR_EE;
1746 } else {
1747 cpu->reset_sctlr |= SCTLR_B;
1748 }
1749 }
1750
1751 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
1752
1753
1754
1755 unset_feature(env, ARM_FEATURE_EL3);
1756
1757
1758
1759
1760 cpu->isar.id_pfr1 &= ~0xf0;
1761 cpu->isar.id_aa64pfr0 &= ~0xf000;
1762 }
1763
1764 if (!cpu->has_el2) {
1765 unset_feature(env, ARM_FEATURE_EL2);
1766 }
1767
1768 if (!cpu->has_pmu) {
1769 unset_feature(env, ARM_FEATURE_PMU);
1770 }
1771 if (arm_feature(env, ARM_FEATURE_PMU)) {
1772 pmu_init(cpu);
1773
1774 if (!kvm_enabled()) {
1775 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1776 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1777 }
1778
1779#ifndef CONFIG_USER_ONLY
1780 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1781 cpu);
1782#endif
1783 } else {
1784 cpu->isar.id_aa64dfr0 =
1785 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
1786 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
1787 cpu->pmceid0 = 0;
1788 cpu->pmceid1 = 0;
1789 }
1790
1791 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1792
1793
1794
1795
1796 cpu->isar.id_aa64pfr0 &= ~0xf00;
1797 cpu->isar.id_pfr1 &= ~0xf000;
1798 }
1799
1800#ifndef CONFIG_USER_ONLY
1801 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
1802
1803
1804
1805
1806 cpu->isar.id_aa64pfr1 =
1807 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
1808 }
1809#endif
1810
1811
1812
1813
1814 if (!cpu->has_mpu) {
1815 cpu->pmsav7_dregion = 0;
1816 }
1817 if (cpu->pmsav7_dregion == 0) {
1818 cpu->has_mpu = false;
1819 }
1820
1821 if (arm_feature(env, ARM_FEATURE_PMSA) &&
1822 arm_feature(env, ARM_FEATURE_V7)) {
1823 uint32_t nr = cpu->pmsav7_dregion;
1824
1825 if (nr > 0xff) {
1826 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1827 return;
1828 }
1829
1830 if (nr) {
1831 if (arm_feature(env, ARM_FEATURE_V8)) {
1832
1833 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1834 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1835 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1836 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1837 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1838 }
1839 } else {
1840 env->pmsav7.drbar = g_new0(uint32_t, nr);
1841 env->pmsav7.drsr = g_new0(uint32_t, nr);
1842 env->pmsav7.dracr = g_new0(uint32_t, nr);
1843 }
1844 }
1845 }
1846
1847 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1848 uint32_t nr = cpu->sau_sregion;
1849
1850 if (nr > 0xff) {
1851 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1852 return;
1853 }
1854
1855 if (nr) {
1856 env->sau.rbar = g_new0(uint32_t, nr);
1857 env->sau.rlar = g_new0(uint32_t, nr);
1858 }
1859 }
1860
1861 if (arm_feature(env, ARM_FEATURE_EL3)) {
1862 set_feature(env, ARM_FEATURE_VBAR);
1863 }
1864
1865 register_cp_regs_for_features(cpu);
1866 arm_cpu_register_gdb_regs_for_features(cpu);
1867
1868 init_cpreg_list(cpu);
1869
1870#ifndef CONFIG_USER_ONLY
1871 MachineState *ms = MACHINE(qdev_get_machine());
1872 unsigned int smp_cpus = ms->smp.cpus;
1873 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY);
1874
1875
1876
1877
1878
1879 if (cpu->tag_memory != NULL) {
1880 cs->num_ases = 3 + has_secure;
1881 } else {
1882 cs->num_ases = 1 + has_secure;
1883 }
1884
1885 if (has_secure) {
1886 if (!cpu->secure_memory) {
1887 cpu->secure_memory = cs->memory;
1888 }
1889 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1890 cpu->secure_memory);
1891 }
1892
1893 if (cpu->tag_memory != NULL) {
1894 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
1895 cpu->tag_memory);
1896 if (has_secure) {
1897 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
1898 cpu->secure_tag_memory);
1899 }
1900 }
1901
1902 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1903
1904
1905 if (cpu->core_count == -1) {
1906 cpu->core_count = smp_cpus;
1907 }
1908#endif
1909
1910 if (tcg_enabled()) {
1911 int dcz_blocklen = 4 << cpu->dcz_blocksize;
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922 assert(dcz_blocklen <= TARGET_PAGE_SIZE);
1923
1924
1925
1926
1927
1928
1929 if (cpu_isar_feature(aa64_mte, cpu)) {
1930 assert(dcz_blocklen >= 2 * TAG_GRANULE);
1931 }
1932 }
1933
1934 qemu_init_vcpu(cs);
1935 cpu_reset(cs);
1936
1937 acc->parent_realize(dev, errp);
1938}
1939
1940static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1941{
1942 ObjectClass *oc;
1943 char *typename;
1944 char **cpuname;
1945 const char *cpunamestr;
1946
1947 cpuname = g_strsplit(cpu_model, ",", 1);
1948 cpunamestr = cpuname[0];
1949#ifdef CONFIG_USER_ONLY
1950
1951
1952
1953 if (!strcmp(cpunamestr, "any")) {
1954 cpunamestr = "max";
1955 }
1956#endif
1957 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1958 oc = object_class_by_name(typename);
1959 g_strfreev(cpuname);
1960 g_free(typename);
1961 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1962 object_class_is_abstract(oc)) {
1963 return NULL;
1964 }
1965 return oc;
1966}
1967
1968static Property arm_cpu_properties[] = {
1969 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1970 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
1971 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1972 mp_affinity, ARM64_AFFINITY_INVALID),
1973 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
1974 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
1975 DEFINE_PROP_END_OF_LIST()
1976};
1977
1978static gchar *arm_gdb_arch_name(CPUState *cs)
1979{
1980 ARMCPU *cpu = ARM_CPU(cs);
1981 CPUARMState *env = &cpu->env;
1982
1983 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1984 return g_strdup("iwmmxt");
1985 }
1986 return g_strdup("arm");
1987}
1988
1989#ifndef CONFIG_USER_ONLY
1990#include "hw/core/sysemu-cpu-ops.h"
1991
1992static const struct SysemuCPUOps arm_sysemu_ops = {
1993 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
1994 .asidx_from_attrs = arm_asidx_from_attrs,
1995 .write_elf32_note = arm_cpu_write_elf32_note,
1996 .write_elf64_note = arm_cpu_write_elf64_note,
1997 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
1998 .legacy_vmsd = &vmstate_arm_cpu,
1999};
2000#endif
2001
2002#ifdef CONFIG_TCG
2003static const struct TCGCPUOps arm_tcg_ops = {
2004 .initialize = arm_translate_init,
2005 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
2006 .cpu_exec_interrupt = arm_cpu_exec_interrupt,
2007 .tlb_fill = arm_cpu_tlb_fill,
2008 .debug_excp_handler = arm_debug_excp_handler,
2009
2010#if !defined(CONFIG_USER_ONLY)
2011 .do_interrupt = arm_cpu_do_interrupt,
2012 .do_transaction_failed = arm_cpu_do_transaction_failed,
2013 .do_unaligned_access = arm_cpu_do_unaligned_access,
2014 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
2015 .debug_check_watchpoint = arm_debug_check_watchpoint,
2016 .debug_check_breakpoint = arm_debug_check_breakpoint,
2017#endif
2018};
2019#endif
2020
2021static void arm_cpu_class_init(ObjectClass *oc, void *data)
2022{
2023 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2024 CPUClass *cc = CPU_CLASS(acc);
2025 DeviceClass *dc = DEVICE_CLASS(oc);
2026
2027 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2028 &acc->parent_realize);
2029
2030 device_class_set_props(dc, arm_cpu_properties);
2031 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
2032
2033 cc->class_by_name = arm_cpu_class_by_name;
2034 cc->has_work = arm_cpu_has_work;
2035 cc->dump_state = arm_cpu_dump_state;
2036 cc->set_pc = arm_cpu_set_pc;
2037 cc->gdb_read_register = arm_cpu_gdb_read_register;
2038 cc->gdb_write_register = arm_cpu_gdb_write_register;
2039#ifndef CONFIG_USER_ONLY
2040 cc->sysemu_ops = &arm_sysemu_ops;
2041#endif
2042 cc->gdb_num_core_regs = 26;
2043 cc->gdb_core_xml_file = "arm-core.xml";
2044 cc->gdb_arch_name = arm_gdb_arch_name;
2045 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2046 cc->gdb_stop_before_watchpoint = true;
2047 cc->disas_set_info = arm_disas_set_info;
2048
2049#ifdef CONFIG_TCG
2050 cc->tcg_ops = &arm_tcg_ops;
2051#endif
2052}
2053
2054#ifdef CONFIG_KVM
2055static void arm_host_initfn(Object *obj)
2056{
2057 ARMCPU *cpu = ARM_CPU(obj);
2058
2059 kvm_arm_set_cpu_features_from_host(cpu);
2060 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2061 aarch64_add_sve_properties(obj);
2062 }
2063 arm_cpu_post_init(obj);
2064}
2065
2066static const TypeInfo host_arm_cpu_type_info = {
2067 .name = TYPE_ARM_HOST_CPU,
2068 .parent = TYPE_AARCH64_CPU,
2069 .instance_init = arm_host_initfn,
2070};
2071
2072#endif
2073
2074static void arm_cpu_instance_init(Object *obj)
2075{
2076 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2077
2078 acc->info->initfn(obj);
2079 arm_cpu_post_init(obj);
2080}
2081
2082static void cpu_register_class_init(ObjectClass *oc, void *data)
2083{
2084 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2085
2086 acc->info = data;
2087}
2088
2089void arm_cpu_register(const ARMCPUInfo *info)
2090{
2091 TypeInfo type_info = {
2092 .parent = TYPE_ARM_CPU,
2093 .instance_size = sizeof(ARMCPU),
2094 .instance_align = __alignof__(ARMCPU),
2095 .instance_init = arm_cpu_instance_init,
2096 .class_size = sizeof(ARMCPUClass),
2097 .class_init = info->class_init ?: cpu_register_class_init,
2098 .class_data = (void *)info,
2099 };
2100
2101 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2102 type_register(&type_info);
2103 g_free((void *)type_info.name);
2104}
2105
2106static const TypeInfo arm_cpu_type_info = {
2107 .name = TYPE_ARM_CPU,
2108 .parent = TYPE_CPU,
2109 .instance_size = sizeof(ARMCPU),
2110 .instance_align = __alignof__(ARMCPU),
2111 .instance_init = arm_cpu_initfn,
2112 .instance_finalize = arm_cpu_finalizefn,
2113 .abstract = true,
2114 .class_size = sizeof(ARMCPUClass),
2115 .class_init = arm_cpu_class_init,
2116};
2117
2118static void arm_cpu_register_types(void)
2119{
2120 type_register_static(&arm_cpu_type_info);
2121
2122#ifdef CONFIG_KVM
2123 type_register_static(&host_arm_cpu_type_info);
2124#endif
2125}
2126
2127type_init(arm_cpu_register_types)
2128