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8#include "qemu/osdep.h"
9#include "cpu.h"
10#include "internals.h"
11#include "exec/exec-all.h"
12#include "exec/helper-proto.h"
13
14
15static bool linked_bp_matches(ARMCPU *cpu, int lbn)
16{
17 CPUARMState *env = &cpu->env;
18 uint64_t bcr = env->cp15.dbgbcr[lbn];
19 int brps = arm_num_brps(cpu);
20 int ctx_cmps = arm_num_ctx_cmps(cpu);
21 int bt;
22 uint32_t contextidr;
23 uint64_t hcr_el2;
24
25
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27
28
29
30
31
32 if (lbn >= brps || lbn < (brps - ctx_cmps)) {
33 return false;
34 }
35
36 bcr = env->cp15.dbgbcr[lbn];
37
38 if (extract64(bcr, 0, 1) == 0) {
39
40 return false;
41 }
42
43 bt = extract64(bcr, 20, 4);
44 hcr_el2 = arm_hcr_el2_eff(env);
45
46 switch (bt) {
47 case 3:
48 switch (arm_current_el(env)) {
49 default:
50
51 return false;
52 case 2:
53 if (!(hcr_el2 & HCR_E2H)) {
54
55 return false;
56 }
57 contextidr = env->cp15.contextidr_el[2];
58 break;
59 case 1:
60 contextidr = env->cp15.contextidr_el[1];
61 break;
62 case 0:
63 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
64 contextidr = env->cp15.contextidr_el[2];
65 } else {
66 contextidr = env->cp15.contextidr_el[1];
67 }
68 break;
69 }
70 break;
71
72 case 7:
73 contextidr = env->cp15.contextidr_el[1];
74 break;
75 case 13:
76 contextidr = env->cp15.contextidr_el[2];
77 break;
78
79 case 9:
80 case 11:
81 case 15:
82 default:
83
84
85
86
87 return false;
88 }
89
90
91
92
93
94
95 return contextidr == (uint32_t)env->cp15.dbgbvr[lbn];
96}
97
98static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
99{
100 CPUARMState *env = &cpu->env;
101 uint64_t cr;
102 int pac, hmc, ssc, wt, lbn;
103
104
105
106
107 bool is_secure = arm_is_secure(env);
108 int access_el = arm_current_el(env);
109
110 if (is_wp) {
111 CPUWatchpoint *wp = env->cpu_watchpoint[n];
112
113 if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
114 return false;
115 }
116 cr = env->cp15.dbgwcr[n];
117 if (wp->hitattrs.user) {
118
119
120
121
122
123 access_el = 0;
124 }
125 } else {
126 uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
127
128 if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) {
129 return false;
130 }
131 cr = env->cp15.dbgbcr[n];
132 }
133
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138
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145
146 pac = extract64(cr, 1, 2);
147 hmc = extract64(cr, 13, 1);
148 ssc = extract64(cr, 14, 2);
149
150 switch (ssc) {
151 case 0:
152 break;
153 case 1:
154 case 3:
155 if (is_secure) {
156 return false;
157 }
158 break;
159 case 2:
160 if (!is_secure) {
161 return false;
162 }
163 break;
164 }
165
166 switch (access_el) {
167 case 3:
168 case 2:
169 if (!hmc) {
170 return false;
171 }
172 break;
173 case 1:
174 if (extract32(pac, 0, 1) == 0) {
175 return false;
176 }
177 break;
178 case 0:
179 if (extract32(pac, 1, 1) == 0) {
180 return false;
181 }
182 break;
183 default:
184 g_assert_not_reached();
185 }
186
187 wt = extract64(cr, 20, 1);
188 lbn = extract64(cr, 16, 4);
189
190 if (wt && !linked_bp_matches(cpu, lbn)) {
191 return false;
192 }
193
194 return true;
195}
196
197static bool check_watchpoints(ARMCPU *cpu)
198{
199 CPUARMState *env = &cpu->env;
200 int n;
201
202
203
204
205
206 if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
207 || !arm_generate_debug_exceptions(env)) {
208 return false;
209 }
210
211 for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
212 if (bp_wp_matches(cpu, n, true)) {
213 return true;
214 }
215 }
216 return false;
217}
218
219bool arm_debug_check_breakpoint(CPUState *cs)
220{
221 ARMCPU *cpu = ARM_CPU(cs);
222 CPUARMState *env = &cpu->env;
223 int n;
224
225
226
227
228
229 if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
230 || !arm_generate_debug_exceptions(env)) {
231 return false;
232 }
233
234 for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
235 if (bp_wp_matches(cpu, n, false)) {
236 return true;
237 }
238 }
239 return false;
240}
241
242bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
243{
244
245
246
247
248 ARMCPU *cpu = ARM_CPU(cs);
249
250 return check_watchpoints(cpu);
251}
252
253void arm_debug_excp_handler(CPUState *cs)
254{
255
256
257
258
259 ARMCPU *cpu = ARM_CPU(cs);
260 CPUARMState *env = &cpu->env;
261 CPUWatchpoint *wp_hit = cs->watchpoint_hit;
262
263 if (wp_hit) {
264 if (wp_hit->flags & BP_CPU) {
265 bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
266 bool same_el = arm_debug_target_el(env) == arm_current_el(env);
267
268 cs->watchpoint_hit = NULL;
269
270 env->exception.fsr = arm_debug_exception_fsr(env);
271 env->exception.vaddress = wp_hit->hitaddr;
272 raise_exception(env, EXCP_DATA_ABORT,
273 syn_watchpoint(same_el, 0, wnr),
274 arm_debug_target_el(env));
275 }
276 } else {
277 uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
278 bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
279
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283
284
285
286 if (cpu_breakpoint_test(cs, pc, BP_GDB)
287 || !cpu_breakpoint_test(cs, pc, BP_CPU)) {
288 return;
289 }
290
291 env->exception.fsr = arm_debug_exception_fsr(env);
292
293
294
295
296
297 env->exception.vaddress = 0;
298 raise_exception(env, EXCP_PREFETCH_ABORT,
299 syn_breakpoint(same_el),
300 arm_debug_target_el(env));
301 }
302}
303
304#if !defined(CONFIG_USER_ONLY)
305
306vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
307{
308 ARMCPU *cpu = ARM_CPU(cs);
309 CPUARMState *env = &cpu->env;
310
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316
317
318 if (arm_sctlr_b(env)) {
319 if (len == 1) {
320 addr ^= 3;
321 } else if (len == 2) {
322 addr ^= 2;
323 }
324 }
325
326 return addr;
327}
328
329#endif
330