LXR qemu/target/arm/translate-a64.h

   1/*
   2 *  AArch64 translation, common definitions.
   3 *
   4 * This library is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU Lesser General Public
   6 * License as published by the Free Software Foundation; either
   7 * version 2.1 of the License, or (at your option) any later version.
   8 *
   9 * This library is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12 * Lesser General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU Lesser General Public
  15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef TARGET_ARM_TRANSLATE_A64_H
  19#define TARGET_ARM_TRANSLATE_A64_H
  20
  21#define unsupported_encoding(s, insn)                                    \
  22    do {                                                                 \
  23        qemu_log_mask(LOG_UNIMP,                                         \
  24                      "%s:%d: unsupported instruction encoding 0x%08x "  \
  25                      "at pc=%016" PRIx64 "\n",                          \
  26                      __FILE__, __LINE__, insn, s->pc_curr);             \
  27        unallocated_encoding(s);                                         \
  28    } while (0)
  29
  30TCGv_i64 new_tmp_a64(DisasContext *s);
  31TCGv_i64 new_tmp_a64_local(DisasContext *s);
  32TCGv_i64 new_tmp_a64_zero(DisasContext *s);
  33TCGv_i64 cpu_reg(DisasContext *s, int reg);
  34TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
  35TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf);
  36TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf);
  37void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
  38bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
  39                            unsigned int imms, unsigned int immr);
  40bool sve_access_check(DisasContext *s);
  41TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
  42TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
  43                        bool tag_checked, int log2_size);
  44TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
  45                        bool tag_checked, int size);
  46
  47/* We should have at some point before trying to access an FP register
  48 * done the necessary access check, so assert that
  49 * (a) we did the check and
  50 * (b) we didn't then just plough ahead anyway if it failed.
  51 * Print the instruction pattern in the abort message so we can figure
  52 * out what we need to fix if a user encounters this problem in the wild.
  53 */
  54static inline void assert_fp_access_checked(DisasContext *s)
  55{
  56#ifdef CONFIG_DEBUG_TCG
  57    if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
  58        fprintf(stderr, "target-arm: FP access check missing for "
  59                "instruction 0x%08x\n", s->insn);
  60        abort();
  61    }
  62#endif
  63}
  64
  65/* Return the offset into CPUARMState of an element of specified
  66 * size, 'element' places in from the least significant end of
  67 * the FP/vector register Qn.
  68 */
  69static inline int vec_reg_offset(DisasContext *s, int regno,
  70                                 int element, MemOp size)
  71{
  72    int element_size = 1 << size;
  73    int offs = element * element_size;
  74#ifdef HOST_WORDS_BIGENDIAN
  75    /* This is complicated slightly because vfp.zregs[n].d[0] is
  76     * still the lowest and vfp.zregs[n].d[15] the highest of the
  77     * 256 byte vector, even on big endian systems.
  78     *
  79     * Calculate the offset assuming fully little-endian,
  80     * then XOR to account for the order of the 8-byte units.
  81     *
  82     * For 16 byte elements, the two 8 byte halves will not form a
  83     * host int128 if the host is bigendian, since they're in the
  84     * wrong order.  However the only 16 byte operation we have is
  85     * a move, so we can ignore this for the moment.  More complicated
  86     * operations will have to special case loading and storing from
  87     * the zregs array.
  88     */
  89    if (element_size < 8) {
  90        offs ^= 8 - element_size;
  91    }
  92#endif
  93    offs += offsetof(CPUARMState, vfp.zregs[regno]);
  94    assert_fp_access_checked(s);
  95    return offs;
  96}
  97
  98/* Return the offset info CPUARMState of the "whole" vector register Qn.  */
  99static inline int vec_full_reg_offset(DisasContext *s, int regno)
 100{
 101    assert_fp_access_checked(s);
 102    return offsetof(CPUARMState, vfp.zregs[regno]);
 103}
 104
 105/* Return a newly allocated pointer to the vector register.  */
 106static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
 107{
 108    TCGv_ptr ret = tcg_temp_new_ptr();
 109    tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
 110    return ret;
 111}
 112
 113/* Return the byte size of the "whole" vector register, VL / 8.  */
 114static inline int vec_full_reg_size(DisasContext *s)
 115{
 116    return s->sve_len;
 117}
 118
 119bool disas_sve(DisasContext *, uint32_t);
 120
 121void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 122                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 123void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 124                  uint32_t rm_ofs, int64_t shift,
 125                  uint32_t opr_sz, uint32_t max_sz);
 126
 127#endif /* TARGET_ARM_TRANSLATE_A64_H */
 128