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20#include "qemu/osdep.h"
21#include "tcg/tcg-op.h"
22#include "tcg/tcg-op-gvec.h"
23#include "translate.h"
24#include "translate-a32.h"
25
26#include "decode-m-nocp.c.inc"
27
28
29
30
31
32
33
34
35
36
37static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
38{
39 TCGv_i32 fptr;
40
41 if (!arm_dc_feature(s, ARM_FEATURE_M) ||
42 !arm_dc_feature(s, ARM_FEATURE_V8)) {
43 return false;
44 }
45
46 if (a->op) {
47
48
49
50
51
52
53
54 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
55 return false;
56 }
57 } else {
58
59
60
61
62
63
64 if (dc_isar_feature(aa32_simd_r32, s)) {
65 unallocated_encoding(s);
66 return true;
67 }
68 }
69
70
71
72
73
74
75 if (!s->v8m_secure) {
76 unallocated_encoding(s);
77 return true;
78 }
79
80 s->eci_handled = true;
81
82
83 if (!dc_isar_feature(aa32_vfp, s)) {
84 clear_eci_state(s);
85 return true;
86 }
87
88 fptr = load_reg(s, a->rn);
89 if (a->l) {
90 gen_helper_v7m_vlldm(cpu_env, fptr);
91 } else {
92 gen_helper_v7m_vlstm(cpu_env, fptr);
93 }
94 tcg_temp_free_i32(fptr);
95
96 clear_eci_state(s);
97
98
99 s->base.is_jmp = DISAS_UPDATE_EXIT;
100 return true;
101}
102
103static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
104{
105 int btmreg, topreg;
106 TCGv_i64 zero;
107 TCGv_i32 aspen, sfpa;
108
109 if (!dc_isar_feature(aa32_m_sec_state, s)) {
110
111 return false;
112 }
113
114
115 if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
116 unallocated_encoding(s);
117 return true;
118 }
119
120 s->eci_handled = true;
121
122 if (!dc_isar_feature(aa32_vfp_simd, s)) {
123
124 clear_eci_state(s);
125 return true;
126 }
127
128
129
130
131
132
133 aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
134 sfpa = load_cpu_field(v7m.control[M_REG_S]);
135 tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
136 tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
137 tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
138 tcg_gen_or_i32(sfpa, sfpa, aspen);
139 arm_gen_condlabel(s);
140 tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
141
142 if (s->fp_excp_el != 0) {
143 gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
144 syn_uncategorized(), s->fp_excp_el);
145 return true;
146 }
147
148 topreg = a->vd + a->imm - 1;
149 btmreg = a->vd;
150
151
152 if (a->size == 3) {
153 topreg = topreg * 2 + 1;
154 btmreg *= 2;
155 }
156
157 if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
158
159 unallocated_encoding(s);
160 return true;
161 }
162
163
164 if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
165 topreg = 31;
166 }
167
168 if (!vfp_access_check(s)) {
169 return true;
170 }
171
172
173 zero = tcg_const_i64(0);
174 if (btmreg & 1) {
175 write_neon_element64(zero, btmreg >> 1, 1, MO_32);
176 btmreg++;
177 }
178 for (; btmreg + 1 <= topreg; btmreg += 2) {
179 write_neon_element64(zero, btmreg >> 1, 0, MO_64);
180 }
181 if (btmreg == topreg) {
182 write_neon_element64(zero, btmreg >> 1, 0, MO_32);
183 btmreg++;
184 }
185 assert(btmreg == topreg + 1);
186 if (dc_isar_feature(aa32_mve, s)) {
187 TCGv_i32 z32 = tcg_const_i32(0);
188 store_cpu_field(z32, v7m.vpr);
189 }
190
191 clear_eci_state(s);
192 return true;
193}
194
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213
214typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value,
215 bool do_access);
216
217
218
219
220
221
222typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque,
223 bool do_access);
224
225
226typedef enum FPSysRegCheckResult {
227 FPSysRegCheckFailed,
228 FPSysRegCheckDone,
229 FPSysRegCheckContinue,
230} FPSysRegCheckResult;
231
232static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
233{
234 if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
235 return FPSysRegCheckFailed;
236 }
237
238 switch (regno) {
239 case ARM_VFP_FPSCR:
240 case QEMU_VFP_FPSCR_NZCV:
241 break;
242 case ARM_VFP_FPSCR_NZCVQC:
243 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
244 return FPSysRegCheckFailed;
245 }
246 break;
247 case ARM_VFP_FPCXT_S:
248 case ARM_VFP_FPCXT_NS:
249 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
250 return FPSysRegCheckFailed;
251 }
252 if (!s->v8m_secure) {
253 return FPSysRegCheckFailed;
254 }
255 break;
256 case ARM_VFP_VPR:
257 case ARM_VFP_P0:
258 if (!dc_isar_feature(aa32_mve, s)) {
259 return FPSysRegCheckFailed;
260 }
261 break;
262 default:
263 return FPSysRegCheckFailed;
264 }
265
266
267
268
269
270
271
272 if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) {
273 return FPSysRegCheckDone;
274 }
275 return FPSysRegCheckContinue;
276}
277
278static void gen_branch_fpInactive(DisasContext *s, TCGCond cond,
279 TCGLabel *label)
280{
281
282
283
284
285
286
287
288
289
290
291
292
293 assert(cond == TCG_COND_EQ || cond == TCG_COND_NE);
294
295
296 TCGv_i32 aspen, fpca;
297 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]);
298 fpca = load_cpu_field(v7m.control[M_REG_S]);
299 tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
300 tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
301 tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK);
302 tcg_gen_or_i32(fpca, fpca, aspen);
303 tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label);
304 tcg_temp_free_i32(aspen);
305 tcg_temp_free_i32(fpca);
306}
307
308static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
309 fp_sysreg_loadfn *loadfn,
310 void *opaque)
311{
312
313 TCGv_i32 tmp;
314 TCGLabel *lab_end = NULL;
315
316 switch (fp_sysreg_checks(s, regno)) {
317 case FPSysRegCheckFailed:
318 return false;
319 case FPSysRegCheckDone:
320 return true;
321 case FPSysRegCheckContinue:
322 break;
323 }
324
325 switch (regno) {
326 case ARM_VFP_FPSCR:
327 tmp = loadfn(s, opaque, true);
328 gen_helper_vfp_set_fpscr(cpu_env, tmp);
329 tcg_temp_free_i32(tmp);
330 gen_lookup_tb(s);
331 break;
332 case ARM_VFP_FPSCR_NZCVQC:
333 {
334 TCGv_i32 fpscr;
335 tmp = loadfn(s, opaque, true);
336 if (dc_isar_feature(aa32_mve, s)) {
337
338 TCGv_i32 qc = tcg_temp_new_i32();
339 tcg_gen_andi_i32(qc, tmp, FPCR_QC);
340
341
342
343
344 tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc),
345 16, 16, qc);
346 }
347 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
348 fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
349 tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
350 tcg_gen_or_i32(fpscr, fpscr, tmp);
351 store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
352 tcg_temp_free_i32(tmp);
353 break;
354 }
355 case ARM_VFP_FPCXT_NS:
356 {
357 TCGLabel *lab_active = gen_new_label();
358
359 lab_end = gen_new_label();
360 gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
361
362
363
364
365 loadfn(s, opaque, false);
366 tcg_gen_br(lab_end);
367
368 gen_set_label(lab_active);
369
370
371
372
373
374 if (!vfp_access_check_m(s, true)) {
375
376
377
378
379 s->base.is_jmp = DISAS_NEXT;
380 break;
381 }
382 }
383
384 case ARM_VFP_FPCXT_S:
385 {
386 TCGv_i32 sfpa, control;
387
388
389
390
391 tmp = loadfn(s, opaque, true);
392 sfpa = tcg_temp_new_i32();
393 tcg_gen_shri_i32(sfpa, tmp, 31);
394 control = load_cpu_field(v7m.control[M_REG_S]);
395 tcg_gen_deposit_i32(control, control, sfpa,
396 R_V7M_CONTROL_SFPA_SHIFT, 1);
397 store_cpu_field(control, v7m.control[M_REG_S]);
398 tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
399 gen_helper_vfp_set_fpscr(cpu_env, tmp);
400 tcg_temp_free_i32(tmp);
401 tcg_temp_free_i32(sfpa);
402 break;
403 }
404 case ARM_VFP_VPR:
405
406 if (IS_USER(s)) {
407 loadfn(s, opaque, false);
408 break;
409 }
410 tmp = loadfn(s, opaque, true);
411 store_cpu_field(tmp, v7m.vpr);
412 break;
413 case ARM_VFP_P0:
414 {
415 TCGv_i32 vpr;
416 tmp = loadfn(s, opaque, true);
417 vpr = load_cpu_field(v7m.vpr);
418 tcg_gen_deposit_i32(vpr, vpr, tmp,
419 R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
420 store_cpu_field(vpr, v7m.vpr);
421 tcg_temp_free_i32(tmp);
422 break;
423 }
424 default:
425 g_assert_not_reached();
426 }
427 if (lab_end) {
428 gen_set_label(lab_end);
429 }
430 return true;
431}
432
433static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
434 fp_sysreg_storefn *storefn,
435 void *opaque)
436{
437
438 TCGv_i32 tmp;
439 TCGLabel *lab_end = NULL;
440 bool lookup_tb = false;
441
442 switch (fp_sysreg_checks(s, regno)) {
443 case FPSysRegCheckFailed:
444 return false;
445 case FPSysRegCheckDone:
446 return true;
447 case FPSysRegCheckContinue:
448 break;
449 }
450
451 if (regno == ARM_VFP_FPSCR_NZCVQC && !dc_isar_feature(aa32_mve, s)) {
452
453 regno = QEMU_VFP_FPSCR_NZCV;
454 }
455
456 switch (regno) {
457 case ARM_VFP_FPSCR:
458 tmp = tcg_temp_new_i32();
459 gen_helper_vfp_get_fpscr(tmp, cpu_env);
460 storefn(s, opaque, tmp, true);
461 break;
462 case ARM_VFP_FPSCR_NZCVQC:
463 tmp = tcg_temp_new_i32();
464 gen_helper_vfp_get_fpscr(tmp, cpu_env);
465 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK);
466 storefn(s, opaque, tmp, true);
467 break;
468 case QEMU_VFP_FPSCR_NZCV:
469
470
471
472
473 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
474 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
475 storefn(s, opaque, tmp, true);
476 break;
477 case ARM_VFP_FPCXT_S:
478 {
479 TCGv_i32 control, sfpa, fpscr;
480
481 tmp = tcg_temp_new_i32();
482 sfpa = tcg_temp_new_i32();
483 gen_helper_vfp_get_fpscr(tmp, cpu_env);
484 tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
485 control = load_cpu_field(v7m.control[M_REG_S]);
486 tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
487 tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
488 tcg_gen_or_i32(tmp, tmp, sfpa);
489 tcg_temp_free_i32(sfpa);
490
491
492
493
494 storefn(s, opaque, tmp, true);
495
496
497
498
499 tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
500 store_cpu_field(control, v7m.control[M_REG_S]);
501 fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
502 gen_helper_vfp_set_fpscr(cpu_env, fpscr);
503 tcg_temp_free_i32(fpscr);
504 lookup_tb = true;
505 break;
506 }
507 case ARM_VFP_FPCXT_NS:
508 {
509 TCGv_i32 control, sfpa, fpscr, fpdscr, zero;
510 TCGLabel *lab_active = gen_new_label();
511
512 lookup_tb = true;
513
514 gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
515
516 TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);
517 storefn(s, opaque, tmp, true);
518 lab_end = gen_new_label();
519 tcg_gen_br(lab_end);
520
521 gen_set_label(lab_active);
522
523
524
525
526
527 if (!vfp_access_check_m(s, true)) {
528
529
530
531
532 s->base.is_jmp = DISAS_NEXT;
533 break;
534 }
535 tmp = tcg_temp_new_i32();
536 sfpa = tcg_temp_new_i32();
537 fpscr = tcg_temp_new_i32();
538 gen_helper_vfp_get_fpscr(fpscr, cpu_env);
539 tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
540 control = load_cpu_field(v7m.control[M_REG_S]);
541 tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
542 tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
543 tcg_gen_or_i32(tmp, tmp, sfpa);
544 tcg_temp_free_i32(control);
545
546 storefn(s, opaque, tmp, true);
547
548 fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
549 zero = tcg_const_i32(0);
550 tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr);
551 gen_helper_vfp_set_fpscr(cpu_env, fpscr);
552 tcg_temp_free_i32(zero);
553 tcg_temp_free_i32(sfpa);
554 tcg_temp_free_i32(fpdscr);
555 tcg_temp_free_i32(fpscr);
556 break;
557 }
558 case ARM_VFP_VPR:
559
560 if (IS_USER(s)) {
561 storefn(s, opaque, NULL, false);
562 break;
563 }
564 tmp = load_cpu_field(v7m.vpr);
565 storefn(s, opaque, tmp, true);
566 break;
567 case ARM_VFP_P0:
568 tmp = load_cpu_field(v7m.vpr);
569 tcg_gen_extract_i32(tmp, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
570 storefn(s, opaque, tmp, true);
571 break;
572 default:
573 g_assert_not_reached();
574 }
575
576 if (lab_end) {
577 gen_set_label(lab_end);
578 }
579 if (lookup_tb) {
580 gen_lookup_tb(s);
581 }
582 return true;
583}
584
585static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value,
586 bool do_access)
587{
588 arg_VMSR_VMRS *a = opaque;
589
590 if (!do_access) {
591 return;
592 }
593
594 if (a->rt == 15) {
595
596 gen_set_nzcv(value);
597 tcg_temp_free_i32(value);
598 } else {
599 store_reg(s, a->rt, value);
600 }
601}
602
603static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque, bool do_access)
604{
605 arg_VMSR_VMRS *a = opaque;
606
607 if (!do_access) {
608 return NULL;
609 }
610 return load_reg(s, a->rt);
611}
612
613static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
614{
615
616
617
618
619
620
621 if (a->rt == 15) {
622 if (a->l && a->reg == ARM_VFP_FPSCR) {
623 a->reg = QEMU_VFP_FPSCR_NZCV;
624 } else {
625 return false;
626 }
627 }
628
629 if (a->l) {
630
631 return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a);
632 } else {
633
634 return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a);
635 }
636}
637
638static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value,
639 bool do_access)
640{
641 arg_vldr_sysreg *a = opaque;
642 uint32_t offset = a->imm;
643 TCGv_i32 addr;
644
645 if (!a->a) {
646 offset = -offset;
647 }
648
649 if (!do_access && !a->w) {
650 return;
651 }
652
653 addr = load_reg(s, a->rn);
654 if (a->p) {
655 tcg_gen_addi_i32(addr, addr, offset);
656 }
657
658 if (s->v8m_stackcheck && a->rn == 13 && a->w) {
659 gen_helper_v8m_stackcheck(cpu_env, addr);
660 }
661
662 if (do_access) {
663 gen_aa32_st_i32(s, value, addr, get_mem_index(s),
664 MO_UL | MO_ALIGN | s->be_data);
665 tcg_temp_free_i32(value);
666 }
667
668 if (a->w) {
669
670 if (!a->p) {
671 tcg_gen_addi_i32(addr, addr, offset);
672 }
673 store_reg(s, a->rn, addr);
674 } else {
675 tcg_temp_free_i32(addr);
676 }
677}
678
679static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque,
680 bool do_access)
681{
682 arg_vldr_sysreg *a = opaque;
683 uint32_t offset = a->imm;
684 TCGv_i32 addr;
685 TCGv_i32 value = NULL;
686
687 if (!a->a) {
688 offset = -offset;
689 }
690
691 if (!do_access && !a->w) {
692 return NULL;
693 }
694
695 addr = load_reg(s, a->rn);
696 if (a->p) {
697 tcg_gen_addi_i32(addr, addr, offset);
698 }
699
700 if (s->v8m_stackcheck && a->rn == 13 && a->w) {
701 gen_helper_v8m_stackcheck(cpu_env, addr);
702 }
703
704 if (do_access) {
705 value = tcg_temp_new_i32();
706 gen_aa32_ld_i32(s, value, addr, get_mem_index(s),
707 MO_UL | MO_ALIGN | s->be_data);
708 }
709
710 if (a->w) {
711
712 if (!a->p) {
713 tcg_gen_addi_i32(addr, addr, offset);
714 }
715 store_reg(s, a->rn, addr);
716 } else {
717 tcg_temp_free_i32(addr);
718 }
719 return value;
720}
721
722static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
723{
724 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
725 return false;
726 }
727 if (a->rn == 15) {
728 return false;
729 }
730 return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a);
731}
732
733static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
734{
735 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
736 return false;
737 }
738 if (a->rn == 15) {
739 return false;
740 }
741 return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a);
742}
743
744static bool trans_NOCP(DisasContext *s, arg_nocp *a)
745{
746
747
748
749
750
751
752 assert(arm_dc_feature(s, ARM_FEATURE_M));
753
754 if (a->cp == 11) {
755 a->cp = 10;
756 }
757 if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
758 (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
759
760 a->cp = 10;
761 }
762
763 if (a->cp != 10) {
764 gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
765 syn_uncategorized(), default_exception_el(s));
766 return true;
767 }
768
769 if (s->fp_excp_el != 0) {
770 gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
771 syn_uncategorized(), s->fp_excp_el);
772 return true;
773 }
774
775 return false;
776}
777
778static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
779{
780
781 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
782 return false;
783 }
784 return trans_NOCP(s, a);
785}
786