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18#include "qemu/osdep.h"
19#include "cpu.h"
20#include "internal.h"
21#include "tcg/tcg-op.h"
22#include "insn.h"
23#include "opcodes.h"
24#include "translate.h"
25#define QEMU_GENERATE
26#include "macros.h"
27#undef QEMU_GENERATE
28#include "gen_tcg.h"
29
30static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
31{
32 TCGv zero = tcg_const_tl(0);
33 TCGv slot_mask = tcg_temp_new();
34
35 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
36 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
37 val, hex_new_value[rnum]);
38 if (HEX_DEBUG) {
39
40
41
42
43
44
45
46 tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
47 tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
48 }
49
50 tcg_temp_free(zero);
51 tcg_temp_free(slot_mask);
52}
53
54static inline void gen_log_reg_write(int rnum, TCGv val)
55{
56 tcg_gen_mov_tl(hex_new_value[rnum], val);
57 if (HEX_DEBUG) {
58
59 tcg_gen_movi_tl(hex_reg_written[rnum], 1);
60 }
61}
62
63static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
64{
65 TCGv val32 = tcg_temp_new();
66 TCGv zero = tcg_const_tl(0);
67 TCGv slot_mask = tcg_temp_new();
68
69 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
70
71 tcg_gen_extrl_i64_i32(val32, val);
72 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum],
73 slot_mask, zero,
74 val32, hex_new_value[rnum]);
75
76 tcg_gen_extrh_i64_i32(val32, val);
77 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
78 slot_mask, zero,
79 val32, hex_new_value[rnum + 1]);
80 if (HEX_DEBUG) {
81
82
83
84
85
86
87
88 tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
89 tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
90 tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
91 slot_mask);
92 }
93
94 tcg_temp_free(val32);
95 tcg_temp_free(zero);
96 tcg_temp_free(slot_mask);
97}
98
99static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
100{
101
102 tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
103 if (HEX_DEBUG) {
104
105 tcg_gen_movi_tl(hex_reg_written[rnum], 1);
106 }
107
108
109 tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
110 if (HEX_DEBUG) {
111
112 tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
113 }
114}
115
116static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
117{
118 TCGv base_val = tcg_temp_new();
119
120 tcg_gen_andi_tl(base_val, val, 0xff);
121
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125
126
127
128
129 if (!test_bit(pnum, ctx->pregs_written)) {
130 tcg_gen_mov_tl(hex_new_pred_value[pnum], base_val);
131 } else {
132 tcg_gen_and_tl(hex_new_pred_value[pnum],
133 hex_new_pred_value[pnum], base_val);
134 }
135 tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);
136
137 tcg_temp_free(base_val);
138}
139
140static inline void gen_read_p3_0(TCGv control_reg)
141{
142 tcg_gen_movi_tl(control_reg, 0);
143 for (int i = 0; i < NUM_PREGS; i++) {
144 tcg_gen_deposit_tl(control_reg, control_reg, hex_pred[i], i * 8, 8);
145 }
146}
147
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155
156
157static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num,
158 TCGv dest)
159{
160 if (reg_num == HEX_REG_P3_0) {
161 gen_read_p3_0(dest);
162 } else if (reg_num == HEX_REG_PC) {
163 tcg_gen_movi_tl(dest, ctx->base.pc_next);
164 } else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
165 tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_PKT_CNT],
166 ctx->num_packets);
167 } else if (reg_num == HEX_REG_QEMU_INSN_CNT) {
168 tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_INSN_CNT],
169 ctx->num_insns);
170 } else {
171 tcg_gen_mov_tl(dest, hex_gpr[reg_num]);
172 }
173}
174
175static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num,
176 TCGv_i64 dest)
177{
178 if (reg_num == HEX_REG_P3_0) {
179 TCGv p3_0 = tcg_temp_new();
180 gen_read_p3_0(p3_0);
181 tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]);
182 tcg_temp_free(p3_0);
183 } else if (reg_num == HEX_REG_PC - 1) {
184 TCGv pc = tcg_const_tl(ctx->base.pc_next);
185 tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc);
186 tcg_temp_free(pc);
187 } else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
188 TCGv pkt_cnt = tcg_temp_new();
189 TCGv insn_cnt = tcg_temp_new();
190 tcg_gen_addi_tl(pkt_cnt, hex_gpr[HEX_REG_QEMU_PKT_CNT],
191 ctx->num_packets);
192 tcg_gen_addi_tl(insn_cnt, hex_gpr[HEX_REG_QEMU_INSN_CNT],
193 ctx->num_insns);
194 tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt);
195 tcg_temp_free(pkt_cnt);
196 tcg_temp_free(insn_cnt);
197 } else {
198 tcg_gen_concat_i32_i64(dest,
199 hex_gpr[reg_num],
200 hex_gpr[reg_num + 1]);
201 }
202}
203
204static inline void gen_write_p3_0(TCGv control_reg)
205{
206 for (int i = 0; i < NUM_PREGS; i++) {
207 tcg_gen_extract_tl(hex_pred[i], control_reg, i * 8, 8);
208 }
209}
210
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217
218static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
219 TCGv val)
220{
221 if (reg_num == HEX_REG_P3_0) {
222 gen_write_p3_0(val);
223 } else {
224 gen_log_reg_write(reg_num, val);
225 ctx_log_reg_write(ctx, reg_num);
226 if (reg_num == HEX_REG_QEMU_PKT_CNT) {
227 ctx->num_packets = 0;
228 }
229 if (reg_num == HEX_REG_QEMU_INSN_CNT) {
230 ctx->num_insns = 0;
231 }
232 }
233}
234
235static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
236 TCGv_i64 val)
237{
238 if (reg_num == HEX_REG_P3_0) {
239 TCGv val32 = tcg_temp_new();
240 tcg_gen_extrl_i64_i32(val32, val);
241 gen_write_p3_0(val32);
242 tcg_gen_extrh_i64_i32(val32, val);
243 gen_log_reg_write(reg_num + 1, val32);
244 tcg_temp_free(val32);
245 ctx_log_reg_write(ctx, reg_num + 1);
246 } else {
247 gen_log_reg_write_pair(reg_num, val);
248 ctx_log_reg_write_pair(ctx, reg_num);
249 if (reg_num == HEX_REG_QEMU_PKT_CNT) {
250 ctx->num_packets = 0;
251 ctx->num_insns = 0;
252 }
253 }
254}
255
256static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
257{
258 if (sign) {
259 tcg_gen_sextract_tl(result, src, N * 8, 8);
260 } else {
261 tcg_gen_extract_tl(result, src, N * 8, 8);
262 }
263 return result;
264}
265
266static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
267{
268 TCGv_i64 res64 = tcg_temp_new_i64();
269 if (sign) {
270 tcg_gen_sextract_i64(res64, src, N * 8, 8);
271 } else {
272 tcg_gen_extract_i64(res64, src, N * 8, 8);
273 }
274 tcg_gen_extrl_i64_i32(result, res64);
275 tcg_temp_free_i64(res64);
276
277 return result;
278}
279
280static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
281{
282 if (sign) {
283 tcg_gen_sextract_tl(result, src, N * 16, 16);
284 } else {
285 tcg_gen_extract_tl(result, src, N * 16, 16);
286 }
287 return result;
288}
289
290static inline void gen_set_half(int N, TCGv result, TCGv src)
291{
292 tcg_gen_deposit_tl(result, result, src, N * 16, 16);
293}
294
295static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
296{
297 TCGv_i64 src64 = tcg_temp_new_i64();
298 tcg_gen_extu_i32_i64(src64, src);
299 tcg_gen_deposit_i64(result, result, src64, N * 16, 16);
300 tcg_temp_free_i64(src64);
301}
302
303static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
304{
305 TCGv_i64 src64 = tcg_temp_new_i64();
306 tcg_gen_extu_i32_i64(src64, src);
307 tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
308 tcg_temp_free_i64(src64);
309}
310
311static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
312{
313 tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
314 tcg_gen_mov_tl(hex_llsc_addr, vaddr);
315 tcg_gen_mov_tl(hex_llsc_val, dest);
316}
317
318static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
319{
320 tcg_gen_qemu_ld64(dest, vaddr, mem_index);
321 tcg_gen_mov_tl(hex_llsc_addr, vaddr);
322 tcg_gen_mov_i64(hex_llsc_val_i64, dest);
323}
324
325static inline void gen_store_conditional4(DisasContext *ctx,
326 TCGv pred, TCGv vaddr, TCGv src)
327{
328 TCGLabel *fail = gen_new_label();
329 TCGLabel *done = gen_new_label();
330 TCGv one, zero, tmp;
331
332 tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
333
334 one = tcg_const_tl(0xff);
335 zero = tcg_const_tl(0);
336 tmp = tcg_temp_new();
337 tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src,
338 ctx->mem_idx, MO_32);
339 tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val,
340 one, zero);
341 tcg_temp_free(one);
342 tcg_temp_free(zero);
343 tcg_temp_free(tmp);
344 tcg_gen_br(done);
345
346 gen_set_label(fail);
347 tcg_gen_movi_tl(pred, 0);
348
349 gen_set_label(done);
350 tcg_gen_movi_tl(hex_llsc_addr, ~0);
351}
352
353static inline void gen_store_conditional8(DisasContext *ctx,
354 TCGv pred, TCGv vaddr, TCGv_i64 src)
355{
356 TCGLabel *fail = gen_new_label();
357 TCGLabel *done = gen_new_label();
358 TCGv_i64 one, zero, tmp;
359
360 tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
361
362 one = tcg_const_i64(0xff);
363 zero = tcg_const_i64(0);
364 tmp = tcg_temp_new_i64();
365 tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src,
366 ctx->mem_idx, MO_64);
367 tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64,
368 one, zero);
369 tcg_gen_extrl_i64_i32(pred, tmp);
370 tcg_temp_free_i64(one);
371 tcg_temp_free_i64(zero);
372 tcg_temp_free_i64(tmp);
373 tcg_gen_br(done);
374
375 gen_set_label(fail);
376 tcg_gen_movi_tl(pred, 0);
377
378 gen_set_label(done);
379 tcg_gen_movi_tl(hex_llsc_addr, ~0);
380}
381
382static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
383{
384 tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
385 tcg_gen_movi_tl(hex_store_width[slot], width);
386 tcg_gen_mov_tl(hex_store_val32[slot], src);
387}
388
389static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
390 DisasContext *ctx, int slot)
391{
392 gen_store32(vaddr, src, 1, slot);
393 ctx->store_width[slot] = 1;
394}
395
396static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
397 DisasContext *ctx, int slot)
398{
399 TCGv tmp = tcg_const_tl(src);
400 gen_store1(cpu_env, vaddr, tmp, ctx, slot);
401 tcg_temp_free(tmp);
402}
403
404static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
405 DisasContext *ctx, int slot)
406{
407 gen_store32(vaddr, src, 2, slot);
408 ctx->store_width[slot] = 2;
409}
410
411static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
412 DisasContext *ctx, int slot)
413{
414 TCGv tmp = tcg_const_tl(src);
415 gen_store2(cpu_env, vaddr, tmp, ctx, slot);
416 tcg_temp_free(tmp);
417}
418
419static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
420 DisasContext *ctx, int slot)
421{
422 gen_store32(vaddr, src, 4, slot);
423 ctx->store_width[slot] = 4;
424}
425
426static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
427 DisasContext *ctx, int slot)
428{
429 TCGv tmp = tcg_const_tl(src);
430 gen_store4(cpu_env, vaddr, tmp, ctx, slot);
431 tcg_temp_free(tmp);
432}
433
434static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
435 DisasContext *ctx, int slot)
436{
437 tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
438 tcg_gen_movi_tl(hex_store_width[slot], 8);
439 tcg_gen_mov_i64(hex_store_val64[slot], src);
440 ctx->store_width[slot] = 8;
441}
442
443static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src,
444 DisasContext *ctx, int slot)
445{
446 TCGv_i64 tmp = tcg_const_i64(src);
447 gen_store8(cpu_env, vaddr, tmp, ctx, slot);
448 tcg_temp_free_i64(tmp);
449}
450
451static TCGv gen_8bitsof(TCGv result, TCGv value)
452{
453 TCGv zero = tcg_const_tl(0);
454 TCGv ones = tcg_const_tl(0xff);
455 tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero);
456 tcg_temp_free(zero);
457 tcg_temp_free(ones);
458
459 return result;
460}
461
462#include "tcg_funcs_generated.c.inc"
463#include "tcg_func_table_generated.c.inc"
464