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18#ifndef HEXAGON_MACROS_H
19#define HEXAGON_MACROS_H
20
21#include "cpu.h"
22#include "hex_regs.h"
23#include "reg_fields.h"
24
25#ifdef QEMU_GENERATE
26#define READ_REG(dest, NUM) gen_read_reg(dest, NUM)
27#else
28#define READ_REG(NUM) (env->gpr[(NUM)])
29#define READ_PREG(NUM) (env->pred[NUM])
30
31#define WRITE_RREG(NUM, VAL) log_reg_write(env, NUM, VAL, slot)
32#define WRITE_PREG(NUM, VAL) log_pred_write(env, NUM, VAL)
33#endif
34
35#define PCALIGN 4
36#define PCALIGN_MASK (PCALIGN - 1)
37
38#define GET_FIELD(FIELD, REGIN) \
39 fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \
40 reg_field_info[FIELD].offset)
41
42#ifdef QEMU_GENERATE
43#define GET_USR_FIELD(FIELD, DST) \
44 tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \
45 reg_field_info[FIELD].offset, \
46 reg_field_info[FIELD].width)
47
48#define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int)
49#define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv)
50#define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64)
51
52#define SET_USR_FIELD_FUNC(X) \
53 __builtin_choose_expr(TYPE_INT(X), \
54 gen_set_usr_fieldi, \
55 __builtin_choose_expr(TYPE_TCGV(X), \
56 gen_set_usr_field, (void)0))
57#define SET_USR_FIELD(FIELD, VAL) \
58 SET_USR_FIELD_FUNC(VAL)(FIELD, VAL)
59#else
60#define GET_USR_FIELD(FIELD) \
61 fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
62 reg_field_info[FIELD].offset)
63
64#define SET_USR_FIELD(FIELD, VAL) \
65 fINSERT_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
66 reg_field_info[FIELD].offset, (VAL))
67#endif
68
69#ifdef QEMU_GENERATE
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92
93#define CHECK_NOSHUF \
94 do { \
95 if (insn->slot == 0 && pkt->pkt_has_store_s1) { \
96 process_store(ctx, pkt, 1); \
97 } \
98 } while (0)
99
100#define MEM_LOAD1s(DST, VA) \
101 do { \
102 CHECK_NOSHUF; \
103 tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
104 } while (0)
105#define MEM_LOAD1u(DST, VA) \
106 do { \
107 CHECK_NOSHUF; \
108 tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
109 } while (0)
110#define MEM_LOAD2s(DST, VA) \
111 do { \
112 CHECK_NOSHUF; \
113 tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
114 } while (0)
115#define MEM_LOAD2u(DST, VA) \
116 do { \
117 CHECK_NOSHUF; \
118 tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
119 } while (0)
120#define MEM_LOAD4s(DST, VA) \
121 do { \
122 CHECK_NOSHUF; \
123 tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
124 } while (0)
125#define MEM_LOAD4u(DST, VA) \
126 do { \
127 CHECK_NOSHUF; \
128 tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
129 } while (0)
130#define MEM_LOAD8u(DST, VA) \
131 do { \
132 CHECK_NOSHUF; \
133 tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
134 } while (0)
135
136#define MEM_STORE1_FUNC(X) \
137 __builtin_choose_expr(TYPE_INT(X), \
138 gen_store1i, \
139 __builtin_choose_expr(TYPE_TCGV(X), \
140 gen_store1, (void)0))
141#define MEM_STORE1(VA, DATA, SLOT) \
142 MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
143
144#define MEM_STORE2_FUNC(X) \
145 __builtin_choose_expr(TYPE_INT(X), \
146 gen_store2i, \
147 __builtin_choose_expr(TYPE_TCGV(X), \
148 gen_store2, (void)0))
149#define MEM_STORE2(VA, DATA, SLOT) \
150 MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
151
152#define MEM_STORE4_FUNC(X) \
153 __builtin_choose_expr(TYPE_INT(X), \
154 gen_store4i, \
155 __builtin_choose_expr(TYPE_TCGV(X), \
156 gen_store4, (void)0))
157#define MEM_STORE4(VA, DATA, SLOT) \
158 MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
159
160#define MEM_STORE8_FUNC(X) \
161 __builtin_choose_expr(TYPE_INT(X), \
162 gen_store8i, \
163 __builtin_choose_expr(TYPE_TCGV_I64(X), \
164 gen_store8, (void)0))
165#define MEM_STORE8(VA, DATA, SLOT) \
166 MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
167#else
168#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA))
169#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA))
170#define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA))
171#define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA))
172#define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA))
173#define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA))
174#define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA))
175#define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA))
176
177#define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
178#define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
179#define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
180#define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
181#endif
182
183#define CANCEL cancel_slot(env, slot)
184
185#define LOAD_CANCEL(EA) do { CANCEL; } while (0)
186
187#ifdef QEMU_GENERATE
188static inline void gen_pred_cancel(TCGv pred, int slot_num)
189 {
190 TCGv slot_mask = tcg_const_tl(1 << slot_num);
191 TCGv tmp = tcg_temp_new();
192 TCGv zero = tcg_const_tl(0);
193 TCGv one = tcg_const_tl(1);
194 tcg_gen_or_tl(slot_mask, hex_slot_cancelled, slot_mask);
195 tcg_gen_andi_tl(tmp, pred, 1);
196 tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero,
197 slot_mask, hex_slot_cancelled);
198 tcg_temp_free(slot_mask);
199 tcg_temp_free(tmp);
200 tcg_temp_free(zero);
201 tcg_temp_free(one);
202}
203#define PRED_LOAD_CANCEL(PRED, EA) \
204 gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot)
205#endif
206
207#define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
208
209#define fMAX(A, B) (((A) > (B)) ? (A) : (B))
210
211#define fMIN(A, B) (((A) < (B)) ? (A) : (B))
212
213#define fABS(A) (((A) < 0) ? (-(A)) : (A))
214#define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \
215 REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG)
216#define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \
217 ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL)
218#define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
219 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
220#define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \
221 (((HIBIT) - (LOWBIT) + 1) ? \
222 extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
223 0LL)
224#define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \
225 do { \
226 int width = ((HIBIT) - (LOWBIT) + 1); \
227 INREG = (width >= 0 ? \
228 deposit64((INREG), (LOWBIT), width, (INVAL)) : \
229 INREG); \
230 } while (0)
231
232#define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
233
234#ifdef QEMU_GENERATE
235#define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1)
236#else
237#define fLSBOLD(VAL) ((VAL) & 1)
238#endif
239
240#ifdef QEMU_GENERATE
241#define fLSBNEW(PVAL) tcg_gen_andi_tl(LSB, (PVAL), 1)
242#define fLSBNEW0 tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1)
243#define fLSBNEW1 tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1)
244#else
245#define fLSBNEW(PVAL) ((PVAL) & 1)
246#define fLSBNEW0 (env->new_pred_value[0] & 1)
247#define fLSBNEW1 (env->new_pred_value[1] & 1)
248#endif
249
250#ifdef QEMU_GENERATE
251#define fLSBOLDNOT(VAL) \
252 do { \
253 tcg_gen_andi_tl(LSB, (VAL), 1); \
254 tcg_gen_xori_tl(LSB, LSB, 1); \
255 } while (0)
256#define fLSBNEWNOT(PNUM) \
257 do { \
258 tcg_gen_andi_tl(LSB, (PNUM), 1); \
259 tcg_gen_xori_tl(LSB, LSB, 1); \
260 } while (0)
261#else
262#define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM))
263#define fLSBOLDNOT(VAL) (!fLSBOLD(VAL))
264#define fLSBNEW0NOT (!fLSBNEW0)
265#define fLSBNEW1NOT (!fLSBNEW1)
266#endif
267
268#define fNEWREG(VAL) ((int32_t)(VAL))
269
270#define fNEWREG_ST(VAL) (VAL)
271
272#define fSATUVALN(N, VAL) \
273 ({ \
274 fSET_OVERFLOW(); \
275 ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \
276 })
277#define fSATVALN(N, VAL) \
278 ({ \
279 fSET_OVERFLOW(); \
280 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
281 })
282#define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL)
283#define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL)
284#define fSATN(N, VAL) \
285 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
286#define fADDSAT64(DST, A, B) \
287 do { \
288 uint64_t __a = fCAST8u(A); \
289 uint64_t __b = fCAST8u(B); \
290 uint64_t __sum = __a + __b; \
291 uint64_t __xor = __a ^ __b; \
292 const uint64_t __mask = 0x8000000000000000ULL; \
293 if (__xor & __mask) { \
294 DST = __sum; \
295 } \
296 else if ((__a ^ __sum) & __mask) { \
297 if (__sum & __mask) { \
298 DST = 0x7FFFFFFFFFFFFFFFLL; \
299 fSET_OVERFLOW(); \
300 } else { \
301 DST = 0x8000000000000000LL; \
302 fSET_OVERFLOW(); \
303 } \
304 } else { \
305 DST = __sum; \
306 } \
307 } while (0)
308#define fSATUN(N, VAL) \
309 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
310#define fSATH(VAL) (fSATN(16, VAL))
311#define fSATUH(VAL) (fSATUN(16, VAL))
312#define fSATUB(VAL) (fSATUN(8, VAL))
313#define fSATB(VAL) (fSATN(8, VAL))
314#define fIMMEXT(IMM) (IMM = IMM)
315#define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
316
317#define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK)
318
319#ifdef QEMU_GENERATE
320static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
321{
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332 TCGv msb = tcg_temp_new();
333 TCGv lsb = tcg_temp_new();
334
335 tcg_gen_extract_tl(lsb, val, 17, 7);
336 tcg_gen_sari_tl(msb, val, 21);
337 tcg_gen_deposit_tl(result, msb, lsb, 0, 7);
338
339 tcg_gen_shli_tl(result, result, shift);
340
341 tcg_temp_free(msb);
342 tcg_temp_free(lsb);
343
344 return result;
345}
346#define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT))
347#else
348#define fREAD_IREG(VAL) \
349 (fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f)))
350#endif
351
352#define fREAD_LR() (READ_REG(HEX_REG_LR))
353
354#define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A)
355#define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A)
356#define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A)
357
358#define fREAD_SP() (READ_REG(HEX_REG_SP))
359#define fREAD_LC0 (READ_REG(HEX_REG_LC0))
360#define fREAD_LC1 (READ_REG(HEX_REG_LC1))
361#define fREAD_SA0 (READ_REG(HEX_REG_SA0))
362#define fREAD_SA1 (READ_REG(HEX_REG_SA1))
363#define fREAD_FP() (READ_REG(HEX_REG_FP))
364#ifdef FIXME
365
366#define fREAD_GP() \
367 (insn->extension_valid ? 0 : READ_REG(HEX_REG_GP))
368#else
369#define fREAD_GP() READ_REG(HEX_REG_GP)
370#endif
371#define fREAD_PC() (READ_REG(HEX_REG_PC))
372
373#define fREAD_NPC() (env->next_PC & (0xfffffffe))
374
375#define fREAD_P0() (READ_PREG(0))
376#define fREAD_P3() (READ_PREG(3))
377
378#define fCHECK_PCALIGN(A)
379
380#define fWRITE_NPC(A) write_new_pc(env, A)
381
382#define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC)
383#define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR)
384#define fHINTJR(TARGET) { }
385#define fCALL(A) \
386 do { \
387 fWRITE_LR(fREAD_NPC()); \
388 fBRANCH(A, COF_TYPE_CALL); \
389 } while (0)
390#define fCALLR(A) \
391 do { \
392 fWRITE_LR(fREAD_NPC()); \
393 fBRANCH(A, COF_TYPE_CALLR); \
394 } while (0)
395#define fWRITE_LOOP_REGS0(START, COUNT) \
396 do { \
397 WRITE_RREG(HEX_REG_LC0, COUNT); \
398 WRITE_RREG(HEX_REG_SA0, START); \
399 } while (0)
400#define fWRITE_LOOP_REGS1(START, COUNT) \
401 do { \
402 WRITE_RREG(HEX_REG_LC1, COUNT); \
403 WRITE_RREG(HEX_REG_SA1, START);\
404 } while (0)
405#define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL)
406#define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL)
407
408#define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
409#define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
410#define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
411#define fWRITE_P0(VAL) WRITE_PREG(0, VAL)
412#define fWRITE_P1(VAL) WRITE_PREG(1, VAL)
413#define fWRITE_P2(VAL) WRITE_PREG(2, VAL)
414#define fWRITE_P3(VAL) WRITE_PREG(3, VAL)
415#define fPART1(WORK) if (part1) { WORK; return; }
416#define fCAST4u(A) ((uint32_t)(A))
417#define fCAST4s(A) ((int32_t)(A))
418#define fCAST8u(A) ((uint64_t)(A))
419#define fCAST8s(A) ((int64_t)(A))
420#define fCAST4_4s(A) ((int32_t)(A))
421#define fCAST4_4u(A) ((uint32_t)(A))
422#define fCAST4_8s(A) ((int64_t)((int32_t)(A)))
423#define fCAST4_8u(A) ((uint64_t)((uint32_t)(A)))
424#define fCAST8_8s(A) ((int64_t)(A))
425#define fCAST8_8u(A) ((uint64_t)(A))
426#define fCAST2_8s(A) ((int64_t)((int16_t)(A)))
427#define fCAST2_8u(A) ((uint64_t)((uint16_t)(A)))
428#define fZE8_16(A) ((int16_t)((uint8_t)(A)))
429#define fSE8_16(A) ((int16_t)((int8_t)(A)))
430#define fSE16_32(A) ((int32_t)((int16_t)(A)))
431#define fZE16_32(A) ((uint32_t)((uint16_t)(A)))
432#define fSE32_64(A) ((int64_t)((int32_t)(A)))
433#define fZE32_64(A) ((uint64_t)((uint32_t)(A)))
434#define fSE8_32(A) ((int32_t)((int8_t)(A)))
435#define fZE8_32(A) ((int32_t)((uint8_t)(A)))
436#define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B))
437#define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B))
438#define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B))
439#define fMPY8SS(A, B) (int)((short)(A) * (short)(B))
440#define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B))
441#define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B))
442#define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B))
443#define fMPY16US(A, B) fMPY16SU(B, A)
444#define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B))
445#define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B))
446#define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B))
447#define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B))
448#define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B))
449#define fROUND(A) (A + 0x8000)
450#define fCLIP(DST, SRC, U) \
451 do { \
452 int32_t maxv = (1 << U) - 1; \
453 int32_t minv = -(1 << U); \
454 DST = fMIN(maxv, fMAX(SRC, minv)); \
455 } while (0)
456#define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A)))
457#define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1))))))
458#define fCRNDN(A, N) (conv_round(A, N))
459#define fADD128(A, B) (int128_add(A, B))
460#define fSUB128(A, B) (int128_sub(A, B))
461#define fSHIFTR128(A, B) (int128_rshift(A, B))
462#define fSHIFTL128(A, B) (int128_lshift(A, B))
463#define fAND128(A, B) (int128_and(A, B))
464#define fCAST8S_16S(A) (int128_exts64(A))
465#define fCAST16S_8S(A) (int128_getlo(A))
466
467#ifdef QEMU_GENERATE
468#define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM)
469#define fEA_RRs(REG, REG2, SCALE) \
470 do { \
471 TCGv tmp = tcg_temp_new(); \
472 tcg_gen_shli_tl(tmp, REG2, SCALE); \
473 tcg_gen_add_tl(EA, REG, tmp); \
474 tcg_temp_free(tmp); \
475 } while (0)
476#define fEA_IRs(IMM, REG, SCALE) \
477 do { \
478 tcg_gen_shli_tl(EA, REG, SCALE); \
479 tcg_gen_addi_tl(EA, EA, IMM); \
480 } while (0)
481#else
482#define fEA_RI(REG, IMM) \
483 do { \
484 EA = REG + IMM; \
485 } while (0)
486#define fEA_RRs(REG, REG2, SCALE) \
487 do { \
488 EA = REG + (REG2 << SCALE); \
489 } while (0)
490#define fEA_IRs(IMM, REG, SCALE) \
491 do { \
492 EA = IMM + (REG << SCALE); \
493 } while (0)
494#endif
495
496#ifdef QEMU_GENERATE
497#define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM)
498#define fEA_REG(REG) tcg_gen_mov_tl(EA, REG)
499#define fEA_BREVR(REG) gen_helper_fbrev(EA, REG)
500#define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM)
501#define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL)
502#define fPM_CIRI(REG, IMM, MVAL) \
503 do { \
504 TCGv tcgv_siV = tcg_const_tl(siV); \
505 gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \
506 hex_gpr[HEX_REG_CS0 + MuN]); \
507 tcg_temp_free(tcgv_siV); \
508 } while (0)
509#else
510#define fEA_IMM(IMM) do { EA = (IMM); } while (0)
511#define fEA_REG(REG) do { EA = (REG); } while (0)
512#define fEA_GPI(IMM) do { EA = (fREAD_GP() + (IMM)); } while (0)
513#define fPM_I(REG, IMM) do { REG = REG + (IMM); } while (0)
514#define fPM_M(REG, MVAL) do { REG = REG + (MVAL); } while (0)
515#endif
516#define fSCALE(N, A) (((int64_t)(A)) << N)
517#define fSATW(A) fSATN(32, ((long long)A))
518#define fSAT(A) fSATN(32, (A))
519#define fSAT_ORIG_SHL(A, ORIG_REG) \
520 ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
521 ? fSATVALN(32, ((int32_t)(ORIG_REG))) \
522 : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
523 : fSAT(A)))
524#define fPASS(A) A
525#define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \
526 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
527 : (fCAST##REGSTYPE(SRC) << (SHAMT)))
528#define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \
529 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s)
530#define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
531 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u)
532#define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \
533 (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
534 : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
535#define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
536 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
537 : (fCAST##REGSTYPE(SRC) >> (SHAMT)))
538#define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \
539 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s)
540#define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \
541 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
542#define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \
543 (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \
544 << ((-(SHAMT)) - 1)) << 1, (SRC)) \
545 : (fCAST##REGSTYPE##s(SRC) >> (SHAMT)))
546#define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT))
547#define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
548 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))
549#define fROTL(SRC, SHAMT, REGSTYPE) \
550 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
551 ((fCAST##REGSTYPE##u(SRC) >> \
552 ((sizeof(SRC) * 8) - (SHAMT))))))
553#define fROTR(SRC, SHAMT, REGSTYPE) \
554 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
555 ((fCAST##REGSTYPE##u(SRC) << \
556 ((sizeof(SRC) * 8) - (SHAMT))))))
557#define fASHIFTL(SRC, SHAMT, REGSTYPE) \
558 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT)))
559
560#ifdef QEMU_GENERATE
561#define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
562#else
563#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
564 DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
565#endif
566
567#define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
568
569#define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY)
570#define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
571#define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
572
573#ifdef CONFIG_USER_ONLY
574#define fFRAMECHECK(ADDR, EA) do { } while (0)
575#else
576
577#define fFRAMECHECK(ADDR, EA) g_assert_not_reached();
578#endif
579
580#ifdef QEMU_GENERATE
581#define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \
582 gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx);
583#endif
584
585#ifdef QEMU_GENERATE
586#define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot)
587#else
588#define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)
589#endif
590
591#ifdef QEMU_GENERATE
592#define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \
593 gen_store_conditional##SIZE(ctx, PRED, EA, SRC);
594#endif
595
596#ifdef QEMU_GENERATE
597#define GETBYTE_FUNC(X) \
598 __builtin_choose_expr(TYPE_TCGV(X), \
599 gen_get_byte, \
600 __builtin_choose_expr(TYPE_TCGV_I64(X), \
601 gen_get_byte_i64, (void)0))
602#define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true)
603#define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false)
604#else
605#define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff))
606#define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff))
607#endif
608
609#define fSETBYTE(N, DST, VAL) \
610 do { \
611 DST = (DST & ~(0x0ffLL << ((N) * 8))) | \
612 (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \
613 } while (0)
614
615#ifdef QEMU_GENERATE
616#define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true)
617#define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false)
618#else
619#define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff))
620#define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff))
621#endif
622#define fSETHALF(N, DST, VAL) \
623 do { \
624 DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \
625 (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \
626 } while (0)
627#define fSETHALFw fSETHALF
628#define fSETHALFd fSETHALF
629
630#define fGETWORD(N, SRC) \
631 ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
632#define fGETUWORD(N, SRC) \
633 ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
634
635#define fSETWORD(N, DST, VAL) \
636 do { \
637 DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \
638 (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \
639 } while (0)
640
641#define fSETBIT(N, DST, VAL) \
642 do { \
643 DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \
644 } while (0)
645
646#define fGETBIT(N, SRC) (((SRC) >> N) & 1)
647#define fSETBITS(HI, LO, DST, VAL) \
648 do { \
649 int j; \
650 for (j = LO; j <= HI; j++) { \
651 fSETBIT(j, DST, VAL); \
652 } \
653 } while (0)
654#define fCOUNTONES_4(VAL) ctpop32(VAL)
655#define fCOUNTONES_8(VAL) ctpop64(VAL)
656#define fBREV_8(VAL) revbit64(VAL)
657#define fBREV_4(VAL) revbit32(VAL)
658#define fCL1_8(VAL) clo64(VAL)
659#define fCL1_4(VAL) clo32(VAL)
660#define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN)
661#define fDEINTERLEAVE(MIXED) deinterleave(MIXED)
662#define fHIDE(A) A
663#define fCONSTLL(A) A##LL
664#define fECHO(A) (A)
665
666#define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)
667#define fPAUSE(IMM)
668
669#define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \
670 ((VAL) << reg_field_info[FIELD].offset)
671#define fGET_REG_FIELD_MASK(FIELD) \
672 (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset)
673#define fREAD_REG_FIELD(REG, FIELD) \
674 fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
675 reg_field_info[FIELD].width, \
676 reg_field_info[FIELD].offset)
677#define fGET_FIELD(VAL, FIELD)
678#define fSET_FIELD(VAL, FIELD, NEWVAL)
679#define fBARRIER()
680#define fSYNCH()
681#define fISYNC()
682#define fDCFETCH(REG) \
683 do { (void)REG; } while (0)
684#define fICINVA(REG) \
685 do { (void)REG; } while (0)
686#define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
687#define fDCCLEANA(REG) \
688 do { (void)REG; } while (0)
689#define fDCCLEANINVA(REG) \
690 do { (void)REG; } while (0)
691
692#define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
693
694#define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
695 STRBITNUM)
696
697
698#endif
699
