LXR qemu/target/ppc/cpu.h

   1/*
   2 *  PowerPC emulation cpu definitions for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef PPC_CPU_H
  21#define PPC_CPU_H
  22
  23#include "qemu/int128.h"
  24#include "exec/cpu-defs.h"
  25#include "cpu-qom.h"
  26#include "qom/object.h"
  27
  28#define TCG_GUEST_DEFAULT_MO 0
  29
  30#define TARGET_PAGE_BITS_64K 16
  31#define TARGET_PAGE_BITS_16M 24
  32
  33#if defined(TARGET_PPC64)
  34#define PPC_ELF_MACHINE     EM_PPC64
  35#else
  36#define PPC_ELF_MACHINE     EM_PPC
  37#endif
  38
  39#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
  40#define PPC_BIT32(bit)          (0x80000000 >> (bit))
  41#define PPC_BIT8(bit)           (0x80 >> (bit))
  42#define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
  43#define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
  44                                 PPC_BIT32(bs))
  45#define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
  46
  47/*****************************************************************************/
  48/* Exception vectors definitions                                             */
  49enum {
  50    POWERPC_EXCP_NONE    = -1,
  51    /* The 64 first entries are used by the PowerPC embedded specification   */
  52    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
  53    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
  54    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
  55    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
  56    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
  57    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
  58    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
  59    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
  60    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
  61    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
  62    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
  63    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
  64    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
  65    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
  66    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
  67    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
  68    /* Vectors 16 to 31 are reserved                                         */
  69    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
  70    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
  71    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
  72    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
  73    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
  74    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
  75    POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
  76    POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
  77    POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
  78    /* Vectors 42 to 63 are reserved                                         */
  79    /* Exceptions defined in the PowerPC server specification                */
  80    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
  81    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
  82    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
  83    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
  84    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
  85    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
  86    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
  87    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
  88    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
  89    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
  90    /* 40x specific exceptions                                               */
  91    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
  92    /* 601 specific exceptions                                               */
  93    POWERPC_EXCP_IO       = 75, /* IO error exception                        */
  94    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
  95    /* 602 specific exceptions                                               */
  96    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
  97    /* 602/603 specific exceptions                                           */
  98    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
  99    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 100    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 101    /* Exceptions available on most PowerPC                                  */
 102    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 103    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 104    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 105    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 106    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 107    /* 7xx/74xx specific exceptions                                          */
 108    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 109    /* 74xx specific exceptions                                              */
 110    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 111    /* 970FX specific exceptions                                             */
 112    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 113    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 114    /* Freescale embedded cores specific exceptions                          */
 115    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 116    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 117    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 118    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 119    /* VSX Unavailable (Power ISA 2.06 and later)                            */
 120    POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 121    POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
 122    /* Additional ISA 2.06 and later server exceptions                       */
 123    POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
 124    POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
 125    POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
 126    /* Server doorbell variants */
 127    POWERPC_EXCP_SDOOR    = 99,
 128    POWERPC_EXCP_SDOOR_HV = 100,
 129    /* ISA 3.00 additions */
 130    POWERPC_EXCP_HVIRT    = 101,
 131    POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception                     */
 132    /* EOL                                                                   */
 133    POWERPC_EXCP_NB       = 103,
 134    /* QEMU exceptions: special cases we want to stop translation            */
 135    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 136};
 137
 138/* Exceptions error codes                                                    */
 139enum {
 140    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 141    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 142    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 143    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 144    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 145    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 146    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 147    POWERPC_EXCP_ALIGN_INSN    = 0x07,  /* Pref. insn x-ing 64-byte boundary */
 148    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 149    /* FP exceptions                                                         */
 150    POWERPC_EXCP_FP            = 0x10,
 151    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 152    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 153    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 154    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 155    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 156    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 157    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 158    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 159    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 160    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 161    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 162    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 163    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 164    /* Invalid instruction                                                   */
 165    POWERPC_EXCP_INVAL         = 0x20,
 166    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 167    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 168    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 169    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 170    /* Privileged instruction                                                */
 171    POWERPC_EXCP_PRIV          = 0x30,
 172    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 173    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 174    /* Trap                                                                  */
 175    POWERPC_EXCP_TRAP          = 0x40,
 176};
 177
 178#define PPC_INPUT(env) ((env)->bus_model)
 179
 180/*****************************************************************************/
 181typedef struct opc_handler_t opc_handler_t;
 182
 183/*****************************************************************************/
 184/* Types used to describe some PowerPC registers etc. */
 185typedef struct DisasContext DisasContext;
 186typedef struct ppc_spr_t ppc_spr_t;
 187typedef union ppc_tlb_t ppc_tlb_t;
 188typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
 189
 190/* SPR access micro-ops generations callbacks */
 191struct ppc_spr_t {
 192    const char *name;
 193    target_ulong default_value;
 194#ifndef CONFIG_USER_ONLY
 195    unsigned int gdb_id;
 196#endif
 197#ifdef CONFIG_TCG
 198    void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 199    void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 200# ifndef CONFIG_USER_ONLY
 201    void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 202    void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 203    void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 204    void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 205# endif
 206#endif
 207#ifdef CONFIG_KVM
 208    /*
 209     * We (ab)use the fact that all the SPRs will have ids for the
 210     * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 211     * don't sync this
 212     */
 213    uint64_t one_reg_id;
 214#endif
 215};
 216
 217/* VSX/Altivec registers (128 bits) */
 218typedef union _ppc_vsr_t {
 219    uint8_t u8[16];
 220    uint16_t u16[8];
 221    uint32_t u32[4];
 222    uint64_t u64[2];
 223    int8_t s8[16];
 224    int16_t s16[8];
 225    int32_t s32[4];
 226    int64_t s64[2];
 227    float32 f32[4];
 228    float64 f64[2];
 229    float128 f128;
 230#ifdef CONFIG_INT128
 231    __uint128_t u128;
 232#endif
 233    Int128  s128;
 234} ppc_vsr_t;
 235
 236typedef ppc_vsr_t ppc_avr_t;
 237typedef ppc_vsr_t ppc_fprp_t;
 238
 239#if !defined(CONFIG_USER_ONLY)
 240/* Software TLB cache */
 241typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 242struct ppc6xx_tlb_t {
 243    target_ulong pte0;
 244    target_ulong pte1;
 245    target_ulong EPN;
 246};
 247
 248typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 249struct ppcemb_tlb_t {
 250    uint64_t RPN;
 251    target_ulong EPN;
 252    target_ulong PID;
 253    target_ulong size;
 254    uint32_t prot;
 255    uint32_t attr; /* Storage attributes */
 256};
 257
 258typedef struct ppcmas_tlb_t {
 259     uint32_t mas8;
 260     uint32_t mas1;
 261     uint64_t mas2;
 262     uint64_t mas7_3;
 263} ppcmas_tlb_t;
 264
 265union ppc_tlb_t {
 266    ppc6xx_tlb_t *tlb6;
 267    ppcemb_tlb_t *tlbe;
 268    ppcmas_tlb_t *tlbm;
 269};
 270
 271/* possible TLB variants */
 272#define TLB_NONE               0
 273#define TLB_6XX                1
 274#define TLB_EMB                2
 275#define TLB_MAS                3
 276#endif
 277
 278typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
 279
 280typedef struct ppc_slb_t ppc_slb_t;
 281struct ppc_slb_t {
 282    uint64_t esid;
 283    uint64_t vsid;
 284    const PPCHash64SegmentPageSizes *sps;
 285};
 286
 287#define MAX_SLB_ENTRIES         64
 288#define SEGMENT_SHIFT_256M      28
 289#define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 290
 291#define SEGMENT_SHIFT_1T        40
 292#define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 293
 294typedef struct ppc_v3_pate_t {
 295    uint64_t dw0;
 296    uint64_t dw1;
 297} ppc_v3_pate_t;
 298
 299/*****************************************************************************/
 300/* Machine state register bits definition                                    */
 301#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 302#define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 303#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 304#define MSR_HV   60 /* hypervisor state                               hflags */
 305#define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
 306#define MSR_TS1  33
 307#define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
 308#define MSR_CM   31 /* Computation mode for BookE                     hflags */
 309#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 310#define MSR_GS   28 /* guest state for BookE                                 */
 311#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 312#define MSR_VR   25 /* altivec available                            x hflags */
 313#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 314#define MSR_AP   23 /* Access privilege state on 602                  hflags */
 315#define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
 316#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 317#define MSR_KEY  19 /* key bit on 603e                                       */
 318#define MSR_POW  18 /* Power management                                      */
 319#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 320#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 321#define MSR_ILE  16 /* Interrupt little-endian mode                          */
 322#define MSR_EE   15 /* External interrupt enable                             */
 323#define MSR_PR   14 /* Problem state                                  hflags */
 324#define MSR_FP   13 /* Floating point available                       hflags */
 325#define MSR_ME   12 /* Machine check interrupt enable                        */
 326#define MSR_FE0  11 /* Floating point exception mode 0                       */
 327#define MSR_SE   10 /* Single-step trace enable                     x hflags */
 328#define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 329#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 330#define MSR_BE   9  /* Branch trace enable                          x hflags */
 331#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 332#define MSR_FE1  8  /* Floating point exception mode 1                       */
 333#define MSR_AL   7  /* AL bit on POWER                                       */
 334#define MSR_EP   6  /* Exception prefix on 601                               */
 335#define MSR_IR   5  /* Instruction relocate                                  */
 336#define MSR_DR   4  /* Data relocate                                         */
 337#define MSR_IS   5  /* Instruction address space (BookE)                     */
 338#define MSR_DS   4  /* Data address space (BookE)                            */
 339#define MSR_PE   3  /* Protection enable on 403                              */
 340#define MSR_PX   2  /* Protection exclusive on 403                  x        */
 341#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 342#define MSR_RI   1  /* Recoverable interrupt                        1        */
 343#define MSR_LE   0  /* Little-endian mode                           1 hflags */
 344
 345/* LPCR bits */
 346#define LPCR_VPM0         PPC_BIT(0)
 347#define LPCR_VPM1         PPC_BIT(1)
 348#define LPCR_ISL          PPC_BIT(2)
 349#define LPCR_KBV          PPC_BIT(3)
 350#define LPCR_DPFD_SHIFT   (63 - 11)
 351#define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
 352#define LPCR_VRMASD_SHIFT (63 - 16)
 353#define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
 354/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
 355#define LPCR_PECE_U_SHIFT (63 - 19)
 356#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
 357#define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
 358#define LPCR_RMLS_SHIFT   (63 - 37)   /* RMLS (removed in ISA v3.0) */
 359#define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
 360#define LPCR_HAIL         PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
 361#define LPCR_ILE          PPC_BIT(38)
 362#define LPCR_AIL_SHIFT    (63 - 40)   /* Alternate interrupt location */
 363#define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
 364#define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
 365#define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
 366#define LPCR_HR           PPC_BIT(43) /* Host Radix */
 367#define LPCR_ONL          PPC_BIT(45)
 368#define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
 369#define LPCR_P7_PECE0     PPC_BIT(49)
 370#define LPCR_P7_PECE1     PPC_BIT(50)
 371#define LPCR_P7_PECE2     PPC_BIT(51)
 372#define LPCR_P8_PECE0     PPC_BIT(47)
 373#define LPCR_P8_PECE1     PPC_BIT(48)
 374#define LPCR_P8_PECE2     PPC_BIT(49)
 375#define LPCR_P8_PECE3     PPC_BIT(50)
 376#define LPCR_P8_PECE4     PPC_BIT(51)
 377/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
 378#define LPCR_PECE_L_SHIFT (63 - 51)
 379#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
 380#define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
 381#define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
 382#define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
 383#define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
 384#define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
 385#define LPCR_MER          PPC_BIT(52)
 386#define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
 387#define LPCR_TC           PPC_BIT(54)
 388#define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
 389#define LPCR_LPES0        PPC_BIT(60)
 390#define LPCR_LPES1        PPC_BIT(61)
 391#define LPCR_RMI          PPC_BIT(62)
 392#define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
 393#define LPCR_HDICE        PPC_BIT(63)
 394
 395/* PSSCR bits */
 396#define PSSCR_ESL         PPC_BIT(42) /* Enable State Loss */
 397#define PSSCR_EC          PPC_BIT(43) /* Exit Criterion */
 398
 399/* HFSCR bits */
 400#define HFSCR_MSGP     PPC_BIT(53) /* Privileged Message Send Facilities */
 401#define HFSCR_IC_MSGP  0xA
 402
 403#define msr_sf   ((env->msr >> MSR_SF)   & 1)
 404#define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 405#if defined(TARGET_PPC64)
 406#define msr_hv   ((env->msr >> MSR_HV)   & 1)
 407#else
 408#define msr_hv   (0)
 409#endif
 410#define msr_cm   ((env->msr >> MSR_CM)   & 1)
 411#define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 412#define msr_gs   ((env->msr >> MSR_GS)   & 1)
 413#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 414#define msr_vr   ((env->msr >> MSR_VR)   & 1)
 415#define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 416#define msr_ap   ((env->msr >> MSR_AP)   & 1)
 417#define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
 418#define msr_sa   ((env->msr >> MSR_SA)   & 1)
 419#define msr_key  ((env->msr >> MSR_KEY)  & 1)
 420#define msr_pow  ((env->msr >> MSR_POW)  & 1)
 421#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 422#define msr_ce   ((env->msr >> MSR_CE)   & 1)
 423#define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 424#define msr_ee   ((env->msr >> MSR_EE)   & 1)
 425#define msr_pr   ((env->msr >> MSR_PR)   & 1)
 426#define msr_fp   ((env->msr >> MSR_FP)   & 1)
 427#define msr_me   ((env->msr >> MSR_ME)   & 1)
 428#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 429#define msr_se   ((env->msr >> MSR_SE)   & 1)
 430#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 431#define msr_uble ((env->msr >> MSR_UBLE) & 1)
 432#define msr_be   ((env->msr >> MSR_BE)   & 1)
 433#define msr_de   ((env->msr >> MSR_DE)   & 1)
 434#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 435#define msr_al   ((env->msr >> MSR_AL)   & 1)
 436#define msr_ep   ((env->msr >> MSR_EP)   & 1)
 437#define msr_ir   ((env->msr >> MSR_IR)   & 1)
 438#define msr_dr   ((env->msr >> MSR_DR)   & 1)
 439#define msr_is   ((env->msr >> MSR_IS)   & 1)
 440#define msr_ds   ((env->msr >> MSR_DS)   & 1)
 441#define msr_pe   ((env->msr >> MSR_PE)   & 1)
 442#define msr_px   ((env->msr >> MSR_PX)   & 1)
 443#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 444#define msr_ri   ((env->msr >> MSR_RI)   & 1)
 445#define msr_le   ((env->msr >> MSR_LE)   & 1)
 446#define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 447#define msr_tm   ((env->msr >> MSR_TM)   & 1)
 448
 449#define DBCR0_ICMP (1 << 27)
 450#define DBCR0_BRT (1 << 26)
 451#define DBSR_ICMP (1 << 27)
 452#define DBSR_BRT (1 << 26)
 453
 454/* Hypervisor bit is more specific */
 455#if defined(TARGET_PPC64)
 456#define MSR_HVB (1ULL << MSR_HV)
 457#else
 458#define MSR_HVB (0ULL)
 459#endif
 460
 461/* DSISR */
 462#define DSISR_NOPTE              0x40000000
 463/* Not permitted by access authority of encoded access authority */
 464#define DSISR_PROTFAULT          0x08000000
 465#define DSISR_ISSTORE            0x02000000
 466/* Not permitted by virtual page class key protection */
 467#define DSISR_AMR                0x00200000
 468/* Unsupported Radix Tree Configuration */
 469#define DSISR_R_BADCONFIG        0x00080000
 470#define DSISR_ATOMIC_RC          0x00040000
 471/* Unable to translate address of (guest) pde or process/page table entry */
 472#define DSISR_PRTABLE_FAULT      0x00020000
 473
 474/* SRR1 error code fields */
 475
 476#define SRR1_NOPTE               DSISR_NOPTE
 477/* Not permitted due to no-execute or guard bit set */
 478#define SRR1_NOEXEC_GUARD        0x10000000
 479#define SRR1_PROTFAULT           DSISR_PROTFAULT
 480#define SRR1_IAMR                DSISR_AMR
 481
 482/* SRR1[42:45] wakeup fields for System Reset Interrupt */
 483
 484#define SRR1_WAKEMASK           0x003c0000 /* reason for wakeup */
 485
 486#define SRR1_WAKEHMI            0x00280000 /* Hypervisor maintenance */
 487#define SRR1_WAKEHVI            0x00240000 /* Hypervisor Virt. Interrupt (P9) */
 488#define SRR1_WAKEEE             0x00200000 /* External interrupt */
 489#define SRR1_WAKEDEC            0x00180000 /* Decrementer interrupt */
 490#define SRR1_WAKEDBELL          0x00140000 /* Privileged doorbell */
 491#define SRR1_WAKERESET          0x00100000 /* System reset */
 492#define SRR1_WAKEHDBELL         0x000c0000 /* Hypervisor doorbell */
 493#define SRR1_WAKESCOM           0x00080000 /* SCOM not in power-saving mode */
 494
 495/* SRR1[46:47] power-saving exit mode */
 496
 497#define SRR1_WAKESTATE          0x00030000 /* Powersave exit mask */
 498
 499#define SRR1_WS_HVLOSS          0x00030000 /* HV resources not maintained */
 500#define SRR1_WS_GPRLOSS         0x00020000 /* GPRs not maintained */
 501#define SRR1_WS_NOLOSS          0x00010000 /* All resources maintained */
 502
 503/* Facility Status and Control (FSCR) bits */
 504#define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
 505#define FSCR_TAR        (63 - 55) /* Target Address Register */
 506#define FSCR_SCV        (63 - 51) /* System call vectored */
 507/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
 508#define FSCR_IC_MASK    (0xFFULL)
 509#define FSCR_IC_POS     (63 - 7)
 510#define FSCR_IC_DSCR_SPR3   2
 511#define FSCR_IC_PMU         3
 512#define FSCR_IC_BHRB        4
 513#define FSCR_IC_TM          5
 514#define FSCR_IC_EBB         7
 515#define FSCR_IC_TAR         8
 516#define FSCR_IC_SCV        12
 517
 518/* Exception state register bits definition                                  */
 519#define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
 520#define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
 521#define ESR_PTR   PPC_BIT(38) /* Trap                                   */
 522#define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
 523#define ESR_ST    PPC_BIT(40) /* Store Operation                        */
 524#define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
 525#define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
 526#define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
 527#define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
 528#define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
 529#define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
 530#define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
 531#define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
 532#define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
 533#define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
 534#define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
 535
 536/* Transaction EXception And Summary Register bits                           */
 537#define TEXASR_FAILURE_PERSISTENT                (63 - 7)
 538#define TEXASR_DISALLOWED                        (63 - 8)
 539#define TEXASR_NESTING_OVERFLOW                  (63 - 9)
 540#define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
 541#define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
 542#define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
 543#define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
 544#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
 545#define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
 546#define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
 547#define TEXASR_ABORT                             (63 - 31)
 548#define TEXASR_SUSPENDED                         (63 - 32)
 549#define TEXASR_PRIVILEGE_HV                      (63 - 34)
 550#define TEXASR_PRIVILEGE_PR                      (63 - 35)
 551#define TEXASR_FAILURE_SUMMARY                   (63 - 36)
 552#define TEXASR_TFIAR_EXACT                       (63 - 37)
 553#define TEXASR_ROT                               (63 - 38)
 554#define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
 555
 556enum {
 557    POWERPC_FLAG_NONE     = 0x00000000,
 558    /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 559    POWERPC_FLAG_SPE      = 0x00000001,
 560    POWERPC_FLAG_VRE      = 0x00000002,
 561    /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 562    POWERPC_FLAG_TGPR     = 0x00000004,
 563    POWERPC_FLAG_CE       = 0x00000008,
 564    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 565    POWERPC_FLAG_SE       = 0x00000010,
 566    POWERPC_FLAG_DWE      = 0x00000020,
 567    POWERPC_FLAG_UBLE     = 0x00000040,
 568    /* Flag for MSR bit 9 signification (BE/DE)                              */
 569    POWERPC_FLAG_BE       = 0x00000080,
 570    POWERPC_FLAG_DE       = 0x00000100,
 571    /* Flag for MSR bit 2 signification (PX/PMM)                             */
 572    POWERPC_FLAG_PX       = 0x00000200,
 573    POWERPC_FLAG_PMM      = 0x00000400,
 574    /* Flag for special features                                             */
 575    /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 576    POWERPC_FLAG_RTC_CLK  = 0x00010000,
 577    POWERPC_FLAG_BUS_CLK  = 0x00020000,
 578    /* Has CFAR                                                              */
 579    POWERPC_FLAG_CFAR     = 0x00040000,
 580    /* Has VSX                                                               */
 581    POWERPC_FLAG_VSX      = 0x00080000,
 582    /* Has Transaction Memory (ISA 2.07)                                     */
 583    POWERPC_FLAG_TM       = 0x00100000,
 584    /* Has SCV (ISA 3.00)                                                    */
 585    POWERPC_FLAG_SCV      = 0x00200000,
 586    /* Has HID0 for LE bit (601)                                             */
 587    POWERPC_FLAG_HID0_LE  = 0x00400000,
 588};
 589
 590/*
 591 * Bits for env->hflags.
 592 *
 593 * Most of these bits overlap with corresponding bits in MSR,
 594 * but some come from other sources.  Those that do come from
 595 * the MSR are validated in hreg_compute_hflags.
 596 */
 597enum {
 598    HFLAGS_LE = 0,   /* MSR_LE -- comes from elsewhere on 601 */
 599    HFLAGS_HV = 1,   /* computed from MSR_HV and other state */
 600    HFLAGS_64 = 2,   /* computed from MSR_CE and MSR_SF */
 601    HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
 602    HFLAGS_DR = 4,   /* MSR_DR */
 603    HFLAGS_SPE = 6,  /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
 604    HFLAGS_TM = 8,   /* computed from MSR_TM */
 605    HFLAGS_BE = 9,   /* MSR_BE -- from elsewhere on embedded ppc */
 606    HFLAGS_SE = 10,  /* MSR_SE -- from elsewhere on embedded ppc */
 607    HFLAGS_FP = 13,  /* MSR_FP */
 608    HFLAGS_PR = 14,  /* MSR_PR */
 609    HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
 610    HFLAGS_VR = 25,  /* MSR_VR if cpu has VRE */
 611
 612    HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
 613    HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
 614};
 615
 616/*****************************************************************************/
 617/* Floating point status and control register                                */
 618#define FPSCR_DRN2   34 /* Decimal Floating-Point rounding control           */
 619#define FPSCR_DRN1   33 /* Decimal Floating-Point rounding control           */
 620#define FPSCR_DRN0   32 /* Decimal Floating-Point rounding control           */
 621#define FPSCR_FX     31 /* Floating-point exception summary                  */
 622#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 623#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 624#define FPSCR_OX     28 /* Floating-point overflow exception                 */
 625#define FPSCR_UX     27 /* Floating-point underflow exception                */
 626#define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 627#define FPSCR_XX     25 /* Floating-point inexact exception                  */
 628#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 629#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 630#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 631#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 632#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 633#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 634#define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 635#define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 636#define FPSCR_C      16 /* Floating-point result class descriptor            */
 637#define FPSCR_FL     15 /* Floating-point less than or negative              */
 638#define FPSCR_FG     14 /* Floating-point greater than or negative           */
 639#define FPSCR_FE     13 /* Floating-point equal or zero                      */
 640#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 641#define FPSCR_FPCC   12 /* Floating-point condition code                     */
 642#define FPSCR_FPRF   12 /* Floating-point result flags                       */
 643#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 644#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 645#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 646#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 647#define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 648#define FPSCR_UE     5  /* Floating-point underflow exception enable          */
 649#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 650#define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 651#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 652#define FPSCR_RN1    1
 653#define FPSCR_RN0    0  /* Floating-point rounding control                   */
 654#define fpscr_drn    (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
 655#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 656#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 657#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 658#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 659#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 660#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 661#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 662#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 663#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 664#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 665#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 666#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 667#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 668#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 669#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 670#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 671#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 672#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 673#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 674#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 675#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 676#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 677#define fpscr_rn     (((env->fpscr) >> FPSCR_RN0)    & 0x3)
 678/* Invalid operation exception summary */
 679#define FPSCR_IX     ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 680                      (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 681                      (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 682                      (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 683                      (1 << FPSCR_VXCVI))
 684/* exception summary */
 685#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 686/* enabled exception summary */
 687#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 688                   0x1F)
 689
 690#define FP_DRN2         (1ull << FPSCR_DRN2)
 691#define FP_DRN1         (1ull << FPSCR_DRN1)
 692#define FP_DRN0         (1ull << FPSCR_DRN0)
 693#define FP_DRN          (FP_DRN2 | FP_DRN1 | FP_DRN0)
 694#define FP_FX           (1ull << FPSCR_FX)
 695#define FP_FEX          (1ull << FPSCR_FEX)
 696#define FP_VX           (1ull << FPSCR_VX)
 697#define FP_OX           (1ull << FPSCR_OX)
 698#define FP_UX           (1ull << FPSCR_UX)
 699#define FP_ZX           (1ull << FPSCR_ZX)
 700#define FP_XX           (1ull << FPSCR_XX)
 701#define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
 702#define FP_VXISI        (1ull << FPSCR_VXISI)
 703#define FP_VXIDI        (1ull << FPSCR_VXIDI)
 704#define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
 705#define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
 706#define FP_VXVC         (1ull << FPSCR_VXVC)
 707#define FP_FR           (1ull << FPSCR_FR)
 708#define FP_FI           (1ull << FPSCR_FI)
 709#define FP_C            (1ull << FPSCR_C)
 710#define FP_FL           (1ull << FPSCR_FL)
 711#define FP_FG           (1ull << FPSCR_FG)
 712#define FP_FE           (1ull << FPSCR_FE)
 713#define FP_FU           (1ull << FPSCR_FU)
 714#define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
 715#define FP_FPRF         (FP_C | FP_FPCC)
 716#define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
 717#define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
 718#define FP_VXCVI        (1ull << FPSCR_VXCVI)
 719#define FP_VE           (1ull << FPSCR_VE)
 720#define FP_OE           (1ull << FPSCR_OE)
 721#define FP_UE           (1ull << FPSCR_UE)
 722#define FP_ZE           (1ull << FPSCR_ZE)
 723#define FP_XE           (1ull << FPSCR_XE)
 724#define FP_NI           (1ull << FPSCR_NI)
 725#define FP_RN1          (1ull << FPSCR_RN1)
 726#define FP_RN0          (1ull << FPSCR_RN0)
 727#define FP_RN           (FP_RN1 | FP_RN0)
 728
 729#define FP_ENABLES      (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
 730#define FP_STATUS       (FP_FR | FP_FI | FP_FPRF)
 731
 732/* the exception bits which can be cleared by mcrfs - includes FX */
 733#define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
 734                          FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
 735                          FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
 736                          FP_VXSQRT | FP_VXCVI)
 737
 738/*****************************************************************************/
 739/* Vector status and control register */
 740#define VSCR_NJ         16 /* Vector non-java */
 741#define VSCR_SAT        0 /* Vector saturation */
 742
 743/*****************************************************************************/
 744/* BookE e500 MMU registers */
 745
 746#define MAS0_NV_SHIFT      0
 747#define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 748
 749#define MAS0_WQ_SHIFT      12
 750#define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 751/* Write TLB entry regardless of reservation */
 752#define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 753/* Write TLB entry only already in use */
 754#define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 755/* Clear TLB entry */
 756#define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 757
 758#define MAS0_HES_SHIFT     14
 759#define MAS0_HES           (1 << MAS0_HES_SHIFT)
 760
 761#define MAS0_ESEL_SHIFT    16
 762#define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 763
 764#define MAS0_TLBSEL_SHIFT  28
 765#define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 766#define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 767#define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 768#define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 769#define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 770
 771#define MAS0_ATSEL_SHIFT   31
 772#define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 773#define MAS0_ATSEL_TLB     0
 774#define MAS0_ATSEL_LRAT    MAS0_ATSEL
 775
 776#define MAS1_TSIZE_SHIFT   7
 777#define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 778
 779#define MAS1_TS_SHIFT      12
 780#define MAS1_TS            (1 << MAS1_TS_SHIFT)
 781
 782#define MAS1_IND_SHIFT     13
 783#define MAS1_IND           (1 << MAS1_IND_SHIFT)
 784
 785#define MAS1_TID_SHIFT     16
 786#define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 787
 788#define MAS1_IPROT_SHIFT   30
 789#define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 790
 791#define MAS1_VALID_SHIFT   31
 792#define MAS1_VALID         0x80000000
 793
 794#define MAS2_EPN_SHIFT     12
 795#define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 796
 797#define MAS2_ACM_SHIFT     6
 798#define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 799
 800#define MAS2_VLE_SHIFT     5
 801#define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 802
 803#define MAS2_W_SHIFT       4
 804#define MAS2_W             (1 << MAS2_W_SHIFT)
 805
 806#define MAS2_I_SHIFT       3
 807#define MAS2_I             (1 << MAS2_I_SHIFT)
 808
 809#define MAS2_M_SHIFT       2
 810#define MAS2_M             (1 << MAS2_M_SHIFT)
 811
 812#define MAS2_G_SHIFT       1
 813#define MAS2_G             (1 << MAS2_G_SHIFT)
 814
 815#define MAS2_E_SHIFT       0
 816#define MAS2_E             (1 << MAS2_E_SHIFT)
 817
 818#define MAS3_RPN_SHIFT     12
 819#define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 820
 821#define MAS3_U0                 0x00000200
 822#define MAS3_U1                 0x00000100
 823#define MAS3_U2                 0x00000080
 824#define MAS3_U3                 0x00000040
 825#define MAS3_UX                 0x00000020
 826#define MAS3_SX                 0x00000010
 827#define MAS3_UW                 0x00000008
 828#define MAS3_SW                 0x00000004
 829#define MAS3_UR                 0x00000002
 830#define MAS3_SR                 0x00000001
 831#define MAS3_SPSIZE_SHIFT       1
 832#define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 833
 834#define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 835#define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 836#define MAS4_TIDSELD_MASK       0x00030000
 837#define MAS4_TIDSELD_PID0       0x00000000
 838#define MAS4_TIDSELD_PID1       0x00010000
 839#define MAS4_TIDSELD_PID2       0x00020000
 840#define MAS4_TIDSELD_PIDZ       0x00030000
 841#define MAS4_INDD               0x00008000      /* Default IND */
 842#define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 843#define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 844#define MAS4_ACMD               0x00000040
 845#define MAS4_VLED               0x00000020
 846#define MAS4_WD                 0x00000010
 847#define MAS4_ID                 0x00000008
 848#define MAS4_MD                 0x00000004
 849#define MAS4_GD                 0x00000002
 850#define MAS4_ED                 0x00000001
 851#define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 852#define MAS4_WIMGED_SHIFT       0
 853
 854#define MAS5_SGS                0x80000000
 855#define MAS5_SLPID_MASK         0x00000fff
 856
 857#define MAS6_SPID0              0x3fff0000
 858#define MAS6_SPID1              0x00007ffe
 859#define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 860#define MAS6_SAS                0x00000001
 861#define MAS6_SPID               MAS6_SPID0
 862#define MAS6_SIND               0x00000002      /* Indirect page */
 863#define MAS6_SIND_SHIFT         1
 864#define MAS6_SPID_MASK          0x3fff0000
 865#define MAS6_SPID_SHIFT         16
 866#define MAS6_ISIZE_MASK         0x00000f80
 867#define MAS6_ISIZE_SHIFT        7
 868
 869#define MAS7_RPN                0xffffffff
 870
 871#define MAS8_TGS                0x80000000
 872#define MAS8_VF                 0x40000000
 873#define MAS8_TLBPID             0x00000fff
 874
 875/* Bit definitions for MMUCFG */
 876#define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 877#define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 878#define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 879#define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 880#define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 881#define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 882#define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 883#define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 884#define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 885
 886/* Bit definitions for MMUCSR0 */
 887#define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 888#define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 889#define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 890#define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 891#define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 892                         MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 893#define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 894#define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 895#define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 896#define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 897
 898/* TLBnCFG encoding */
 899#define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 900#define TLBnCFG_HES             0x00002000      /* HW select supported */
 901#define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 902#define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 903#define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 904#define TLBnCFG_IND             0x00020000      /* IND entries supported */
 905#define TLBnCFG_PT              0x00040000      /* Can load from page table */
 906#define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 907#define TLBnCFG_MINSIZE_SHIFT   20
 908#define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 909#define TLBnCFG_MAXSIZE_SHIFT   16
 910#define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 911#define TLBnCFG_ASSOC_SHIFT     24
 912
 913/* TLBnPS encoding */
 914#define TLBnPS_4K               0x00000004
 915#define TLBnPS_8K               0x00000008
 916#define TLBnPS_16K              0x00000010
 917#define TLBnPS_32K              0x00000020
 918#define TLBnPS_64K              0x00000040
 919#define TLBnPS_128K             0x00000080
 920#define TLBnPS_256K             0x00000100
 921#define TLBnPS_512K             0x00000200
 922#define TLBnPS_1M               0x00000400
 923#define TLBnPS_2M               0x00000800
 924#define TLBnPS_4M               0x00001000
 925#define TLBnPS_8M               0x00002000
 926#define TLBnPS_16M              0x00004000
 927#define TLBnPS_32M              0x00008000
 928#define TLBnPS_64M              0x00010000
 929#define TLBnPS_128M             0x00020000
 930#define TLBnPS_256M             0x00040000
 931#define TLBnPS_512M             0x00080000
 932#define TLBnPS_1G               0x00100000
 933#define TLBnPS_2G               0x00200000
 934#define TLBnPS_4G               0x00400000
 935#define TLBnPS_8G               0x00800000
 936#define TLBnPS_16G              0x01000000
 937#define TLBnPS_32G              0x02000000
 938#define TLBnPS_64G              0x04000000
 939#define TLBnPS_128G             0x08000000
 940#define TLBnPS_256G             0x10000000
 941
 942/* tlbilx action encoding */
 943#define TLBILX_T_ALL                    0
 944#define TLBILX_T_TID                    1
 945#define TLBILX_T_FULLMATCH              3
 946#define TLBILX_T_CLASS0                 4
 947#define TLBILX_T_CLASS1                 5
 948#define TLBILX_T_CLASS2                 6
 949#define TLBILX_T_CLASS3                 7
 950
 951/* BookE 2.06 helper defines */
 952
 953#define BOOKE206_FLUSH_TLB0    (1 << 0)
 954#define BOOKE206_FLUSH_TLB1    (1 << 1)
 955#define BOOKE206_FLUSH_TLB2    (1 << 2)
 956#define BOOKE206_FLUSH_TLB3    (1 << 3)
 957
 958/* number of possible TLBs */
 959#define BOOKE206_MAX_TLBN      4
 960
 961#define EPID_EPID_SHIFT 0x0
 962#define EPID_EPID 0xFF
 963#define EPID_ELPID_SHIFT 0x10
 964#define EPID_ELPID 0x3F0000
 965#define EPID_EGS 0x20000000
 966#define EPID_EGS_SHIFT 29
 967#define EPID_EAS 0x40000000
 968#define EPID_EAS_SHIFT 30
 969#define EPID_EPR 0x80000000
 970#define EPID_EPR_SHIFT 31
 971/* We don't support EGS and ELPID */
 972#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
 973
 974/*****************************************************************************/
 975/* Server and Embedded Processor Control */
 976
 977#define DBELL_TYPE_SHIFT               27
 978#define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 979#define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 980#define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 981#define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 982#define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 983#define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 984
 985#define DBELL_TYPE_DBELL_SERVER        (0x05 << DBELL_TYPE_SHIFT)
 986
 987#define DBELL_BRDCAST                  PPC_BIT(37)
 988#define DBELL_LPIDTAG_SHIFT            14
 989#define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 990#define DBELL_PIRTAG_MASK              0x3fff
 991
 992#define DBELL_PROCIDTAG_MASK           PPC_BITMASK(44, 63)
 993
 994#define PPC_PAGE_SIZES_MAX_SZ   8
 995
 996struct ppc_radix_page_info {
 997    uint32_t count;
 998    uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
 999};
1000

1001/*****************************************************************************/
1002/* The whole PowerPC CPU context */
1003
1004/*
1005 * PowerPC needs eight modes for different hypervisor/supervisor/guest
1006 * + real/paged mode combinations. The other two modes are for
1007 * external PID load/store.
1008 */
1009#define PPC_TLB_EPID_LOAD 8
1010#define PPC_TLB_EPID_STORE 9
1011
1012#define PPC_CPU_OPCODES_LEN          0x40
1013#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1014
1015struct CPUPPCState {
1016    /* Most commonly used resources during translated code execution first */
1017    target_ulong gpr[32];  /* general purpose registers */
1018    target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1019    target_ulong lr;
1020    target_ulong ctr;
1021    uint32_t crf[8];       /* condition register */
1022#if defined(TARGET_PPC64)
1023    target_ulong cfar;
1024#endif
1025    target_ulong xer;      /* XER (with SO, OV, CA split out) */
1026    target_ulong so;
1027    target_ulong ov;
1028    target_ulong ca;
1029    target_ulong ov32;
1030    target_ulong ca32;
1031
1032    target_ulong reserve_addr; /* Reservation address */
1033    target_ulong reserve_val;  /* Reservation value */
1034    target_ulong reserve_val2;
1035
1036    /* These are used in supervisor mode only */
1037    target_ulong msr;      /* machine state register */
1038    target_ulong tgpr[4];  /* temporary general purpose registers, */
1039                           /* used to speed-up TLB assist handlers */
1040
1041    target_ulong nip;      /* next instruction pointer */
1042    uint64_t retxh;        /* high part of 128-bit helper return */
1043
1044    /* when a memory exception occurs, the access type is stored here */
1045    int access_type;
1046
1047#if !defined(CONFIG_USER_ONLY)
1048    /* MMU context, only relevant for full system emulation */
1049#if defined(TARGET_PPC64)
1050    ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1051#endif
1052    target_ulong sr[32];   /* segment registers */
1053    uint32_t nb_BATs;      /* number of BATs */
1054    target_ulong DBAT[2][8];
1055    target_ulong IBAT[2][8];
1056    /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1057    int32_t nb_tlb;  /* Total number of TLB */
1058    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1059    int nb_ways;     /* Number of ways in the TLB set */
1060    int last_way;    /* Last used way used to allocate TLB in a LRU way */
1061    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1062    int nb_pids;     /* Number of available PID registers */
1063    int tlb_type;    /* Type of TLB we're dealing with */
1064    ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed */
1065    target_ulong pb[4]; /* 403 dedicated access protection registers */
1066    bool tlb_dirty;  /* Set to non-zero when modifying TLB */
1067    bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1068    uint32_t tlb_need_flush; /* Delayed flush needed */
1069#define TLB_NEED_LOCAL_FLUSH   0x1
1070#define TLB_NEED_GLOBAL_FLUSH  0x2
1071#endif
1072
1073    /* Other registers */
1074    target_ulong spr[1024]; /* special purpose registers */
1075    ppc_spr_t spr_cb[1024];
1076    /* Vector status and control register, minus VSCR_SAT */
1077    uint32_t vscr;
1078    /* VSX registers (including FP and AVR) */
1079    ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1080    /* Non-zero if and only if VSCR_SAT should be set */
1081    ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1082    /* SPE registers */
1083    uint64_t spe_acc;
1084    uint32_t spe_fscr;
1085    /* SPE and Altivec share status as they'll never be used simultaneously */
1086    float_status vec_status;
1087    float_status fp_status; /* Floating point execution context */
1088    target_ulong fpscr;     /* Floating point status and control register */
1089
1090    /* Internal devices resources */
1091    ppc_tb_t *tb_env;      /* Time base and decrementer */
1092    ppc_dcr_t *dcr_env;    /* Device control registers */
1093
1094    int dcache_line_size;
1095    int icache_line_size;
1096
1097    /* These resources are used during exception processing */
1098    /* CPU model definition */
1099    target_ulong msr_mask;
1100    powerpc_mmu_t mmu_model;
1101    powerpc_excp_t excp_model;
1102    powerpc_input_t bus_model;
1103    int bfd_mach;
1104    uint32_t flags;
1105    uint64_t insns_flags;
1106    uint64_t insns_flags2;
1107
1108    int error_code;
1109    uint32_t pending_interrupts;
1110#if !defined(CONFIG_USER_ONLY)
1111    /*
1112     * This is the IRQ controller, which is implementation dependent and only
1113     * relevant when emulating a complete machine. Note that this isn't used
1114     * by recent Book3s compatible CPUs (POWER7 and newer).
1115     */
1116    uint32_t irq_input_state;
1117    void **irq_inputs;
1118
1119    target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1120    target_ulong excp_prefix;
1121    target_ulong ivor_mask;
1122    target_ulong ivpr_mask;
1123    target_ulong hreset_vector;
1124    hwaddr mpic_iack;
1125    bool mpic_proxy;  /* true if the external proxy facility mode is enabled */
1126    bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1127                      /* instructions and SPRs are diallowed if MSR:HV is 0 */
1128    /*
1129     * On P7/P8/P9, set when in PM state so we need to handle resume in a
1130     * special way (such as routing some resume causes to 0x100, i.e. sreset).
1131     */
1132    bool resume_as_sreset;
1133#endif
1134
1135    /* These resources are used only in TCG */
1136    uint32_t hflags;
1137    target_ulong hflags_compat_nmsr; /* for migration compatibility */
1138
1139    /* Power management */
1140    int (*check_pow)(CPUPPCState *env);
1141
1142#if !defined(CONFIG_USER_ONLY)
1143    void *load_info;  /* holds boot loading state */
1144#endif
1145
1146    /* booke timers */
1147
1148    /*
1149     * Specifies bit locations of the Time Base used to signal a fixed timer
1150     * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1151     *
1152     * 0 selects the least significant bit, 63 selects the most significant bit
1153     */
1154    uint8_t fit_period[4];
1155    uint8_t wdt_period[4];
1156
1157    /* Transactional memory state */
1158    target_ulong tm_gpr[32];
1159    ppc_avr_t tm_vsr[64];
1160    uint64_t tm_cr;
1161    uint64_t tm_lr;
1162    uint64_t tm_ctr;
1163    uint64_t tm_fpscr;
1164    uint64_t tm_amr;
1165    uint64_t tm_ppr;
1166    uint64_t tm_vrsave;
1167    uint32_t tm_vscr;
1168    uint64_t tm_dscr;
1169    uint64_t tm_tar;
1170};
1171
1172#define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1173do {                                            \
1174    env->fit_period[0] = (a_);                  \
1175    env->fit_period[1] = (b_);                  \
1176    env->fit_period[2] = (c_);                  \
1177    env->fit_period[3] = (d_);                  \
1178 } while (0)
1179
1180#define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1181do {                                            \
1182    env->wdt_period[0] = (a_);                  \
1183    env->wdt_period[1] = (b_);                  \
1184    env->wdt_period[2] = (c_);                  \
1185    env->wdt_period[3] = (d_);                  \
1186 } while (0)
1187
1188typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1189typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1190
1191/**
1192 * PowerPCCPU:
1193 * @env: #CPUPPCState
1194 * @vcpu_id: vCPU identifier given to KVM
1195 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1196 *
1197 * A PowerPC CPU.
1198 */
1199struct PowerPCCPU {
1200    /*< private >*/
1201    CPUState parent_obj;
1202    /*< public >*/
1203
1204    CPUNegativeOffsetState neg;
1205    CPUPPCState env;
1206
1207    int vcpu_id;
1208    uint32_t compat_pvr;
1209    PPCVirtualHypervisor *vhyp;
1210    void *machine_data;
1211    int32_t node_id; /* NUMA node this CPU belongs to */
1212    PPCHash64Options *hash64_opts;
1213
1214    /* Those resources are used only during code translation */
1215    /* opcode handlers */
1216    opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1217
1218    /* Fields related to migration compatibility hacks */
1219    bool pre_2_8_migration;
1220    target_ulong mig_msr_mask;
1221    uint64_t mig_insns_flags;
1222    uint64_t mig_insns_flags2;
1223    uint32_t mig_nb_BATs;
1224    bool pre_2_10_migration;
1225    bool pre_3_0_migration;
1226    int32_t mig_slb_nr;
1227};
1228
1229
1230PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1231PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1232PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1233
1234#ifndef CONFIG_USER_ONLY
1235struct PPCVirtualHypervisorClass {
1236    InterfaceClass parent;
1237    void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1238    hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1239    const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1240                                         hwaddr ptex, int n);
1241    void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1242                        const ppc_hash_pte64_t *hptes,
1243                        hwaddr ptex, int n);
1244    void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1245    void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1246    void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
1247    target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1248    void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1249    void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1250};
1251
1252#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1253DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1254                     PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1255#endif /* CONFIG_USER_ONLY */
1256
1257void ppc_cpu_do_interrupt(CPUState *cpu);
1258bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1259void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1260hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1261int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1262int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1263int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1264int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1265#ifndef CONFIG_USER_ONLY
1266void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1267const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1268#endif
1269int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1270                               int cpuid, void *opaque);
1271int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1272                               int cpuid, void *opaque);
1273#ifndef CONFIG_USER_ONLY
1274void ppc_cpu_do_system_reset(CPUState *cs);
1275void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1276extern const VMStateDescription vmstate_ppc_cpu;
1277#endif
1278
1279/*****************************************************************************/
1280void ppc_translate_init(void);
1281/*
1282 * you can call this signal handler from your SIGBUS and SIGSEGV
1283 * signal handlers to inform the virtual CPU of exceptions. non zero
1284 * is returned if the signal was handled by the virtual CPU.
1285 */
1286int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);
1287bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1288                      MMUAccessType access_type, int mmu_idx,
1289                      bool probe, uintptr_t retaddr);
1290
1291#if !defined(CONFIG_USER_ONLY)
1292void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1293#endif /* !defined(CONFIG_USER_ONLY) */
1294void ppc_store_msr(CPUPPCState *env, target_ulong value);
1295void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1296
1297void ppc_cpu_list(void);
1298
1299/* Time-base and decrementer management */
1300#ifndef NO_CPU_IO_DEFS
1301uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1302uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1303void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1304void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1305uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1306uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1307void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1308void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1309uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1310void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1311bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1312target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1313void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1314target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1315void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1316void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1317uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1318void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1319uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
1320uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
1321#if !defined(CONFIG_USER_ONLY)
1322void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
1323void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
1324target_ulong load_40x_pit(CPUPPCState *env);
1325void store_40x_pit(CPUPPCState *env, target_ulong val);
1326void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1327void store_40x_sler(CPUPPCState *env, uint32_t val);
1328void store_booke_tcr(CPUPPCState *env, target_ulong val);
1329void store_booke_tsr(CPUPPCState *env, target_ulong val);
1330void ppc_tlb_invalidate_all(CPUPPCState *env);
1331void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1332void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1333#endif
1334#endif
1335
1336void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1337void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1338                                 const char *caller, uint32_t cause);
1339
1340static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1341{
1342    uint64_t gprv;
1343
1344    gprv = env->gpr[gprn];
1345    if (env->flags & POWERPC_FLAG_SPE) {
1346        /*
1347         * If the CPU implements the SPE extension, we have to get the
1348         * high bits of the GPR from the gprh storage area
1349         */
1350        gprv &= 0xFFFFFFFFULL;
1351        gprv |= (uint64_t)env->gprh[gprn] << 32;
1352    }
1353
1354    return gprv;
1355}
1356
1357/* Device control registers */
1358int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1359int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1360
1361#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1362#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1363#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1364
1365#define cpu_signal_handler cpu_ppc_signal_handler
1366#define cpu_list ppc_cpu_list
1367
1368/* MMU modes definitions */
1369#define MMU_USER_IDX 0
1370static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
1371{
1372#ifdef CONFIG_USER_ONLY
1373    return MMU_USER_IDX;
1374#else
1375    return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1376#endif
1377}
1378
1379/* Compatibility modes */
1380#if defined(TARGET_PPC64)
1381bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1382                      uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1383bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1384                           uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1385
1386int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1387
1388#if !defined(CONFIG_USER_ONLY)
1389int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1390#endif
1391int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1392void ppc_compat_add_property(Object *obj, const char *name,
1393                             uint32_t *compat_pvr, const char *basedesc);
1394#endif /* defined(TARGET_PPC64) */
1395
1396typedef CPUPPCState CPUArchState;
1397typedef PowerPCCPU ArchCPU;
1398
1399#include "exec/cpu-all.h"
1400
1401/*****************************************************************************/
1402/* CRF definitions */
1403#define CRF_LT_BIT    3
1404#define CRF_GT_BIT    2
1405#define CRF_EQ_BIT    1
1406#define CRF_SO_BIT    0
1407#define CRF_LT        (1 << CRF_LT_BIT)
1408#define CRF_GT        (1 << CRF_GT_BIT)
1409#define CRF_EQ        (1 << CRF_EQ_BIT)
1410#define CRF_SO        (1 << CRF_SO_BIT)
1411/* For SPE extensions */
1412#define CRF_CH        (1 << CRF_LT_BIT)
1413#define CRF_CL        (1 << CRF_GT_BIT)
1414#define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1415#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1416
1417/* XER definitions */
1418#define XER_SO  31
1419#define XER_OV  30
1420#define XER_CA  29
1421#define XER_OV32  19
1422#define XER_CA32  18
1423#define XER_CMP  8
1424#define XER_BC   0
1425#define xer_so  (env->so)
1426#define xer_ov  (env->ov)
1427#define xer_ca  (env->ca)
1428#define xer_ov32  (env->ov)
1429#define xer_ca32  (env->ca)
1430#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1431#define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1432
1433/* SPR definitions */
1434#define SPR_MQ                (0x000)
1435#define SPR_XER               (0x001)
1436#define SPR_601_VRTCU         (0x004)
1437#define SPR_601_VRTCL         (0x005)
1438#define SPR_601_UDECR         (0x006)
1439#define SPR_LR                (0x008)
1440#define SPR_CTR               (0x009)
1441#define SPR_UAMR              (0x00D)
1442#define SPR_DSCR              (0x011)
1443#define SPR_DSISR             (0x012)
1444#define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1445#define SPR_601_RTCU          (0x014)
1446#define SPR_601_RTCL          (0x015)
1447#define SPR_DECR              (0x016)
1448#define SPR_SDR1              (0x019)
1449#define SPR_SRR0              (0x01A)
1450#define SPR_SRR1              (0x01B)
1451#define SPR_CFAR              (0x01C)
1452#define SPR_AMR               (0x01D)
1453#define SPR_ACOP              (0x01F)
1454#define SPR_BOOKE_PID         (0x030)
1455#define SPR_BOOKS_PID         (0x030)
1456#define SPR_BOOKE_DECAR       (0x036)
1457#define SPR_BOOKE_CSRR0       (0x03A)
1458#define SPR_BOOKE_CSRR1       (0x03B)
1459#define SPR_BOOKE_DEAR        (0x03D)
1460#define SPR_IAMR              (0x03D)
1461#define SPR_BOOKE_ESR         (0x03E)
1462#define SPR_BOOKE_IVPR        (0x03F)
1463#define SPR_MPC_EIE           (0x050)
1464#define SPR_MPC_EID           (0x051)
1465#define SPR_MPC_NRI           (0x052)
1466#define SPR_TFHAR             (0x080)
1467#define SPR_TFIAR             (0x081)
1468#define SPR_TEXASR            (0x082)
1469#define SPR_TEXASRU           (0x083)
1470#define SPR_UCTRL             (0x088)
1471#define SPR_TIDR              (0x090)
1472#define SPR_MPC_CMPA          (0x090)
1473#define SPR_MPC_CMPB          (0x091)
1474#define SPR_MPC_CMPC          (0x092)
1475#define SPR_MPC_CMPD          (0x093)
1476#define SPR_MPC_ECR           (0x094)
1477#define SPR_MPC_DER           (0x095)
1478#define SPR_MPC_COUNTA        (0x096)
1479#define SPR_MPC_COUNTB        (0x097)
1480#define SPR_CTRL              (0x098)
1481#define SPR_MPC_CMPE          (0x098)
1482#define SPR_MPC_CMPF          (0x099)
1483#define SPR_FSCR              (0x099)
1484#define SPR_MPC_CMPG          (0x09A)
1485#define SPR_MPC_CMPH          (0x09B)
1486#define SPR_MPC_LCTRL1        (0x09C)
1487#define SPR_MPC_LCTRL2        (0x09D)
1488#define SPR_UAMOR             (0x09D)
1489#define SPR_MPC_ICTRL         (0x09E)
1490#define SPR_MPC_BAR           (0x09F)
1491#define SPR_PSPB              (0x09F)
1492#define SPR_DPDES             (0x0B0)
1493#define SPR_DAWR0             (0x0B4)
1494#define SPR_RPR               (0x0BA)
1495#define SPR_CIABR             (0x0BB)
1496#define SPR_DAWRX0            (0x0BC)
1497#define SPR_HFSCR             (0x0BE)
1498#define SPR_VRSAVE            (0x100)
1499#define SPR_USPRG0            (0x100)
1500#define SPR_USPRG1            (0x101)
1501#define SPR_USPRG2            (0x102)
1502#define SPR_USPRG3            (0x103)
1503#define SPR_USPRG4            (0x104)
1504#define SPR_USPRG5            (0x105)
1505#define SPR_USPRG6            (0x106)
1506#define SPR_USPRG7            (0x107)
1507#define SPR_VTBL              (0x10C)
1508#define SPR_VTBU              (0x10D)
1509#define SPR_SPRG0             (0x110)
1510#define SPR_SPRG1             (0x111)
1511#define SPR_SPRG2             (0x112)
1512#define SPR_SPRG3             (0x113)
1513#define SPR_SPRG4             (0x114)
1514#define SPR_SCOMC             (0x114)
1515#define SPR_SPRG5             (0x115)
1516#define SPR_SCOMD             (0x115)
1517#define SPR_SPRG6             (0x116)
1518#define SPR_SPRG7             (0x117)
1519#define SPR_ASR               (0x118)
1520#define SPR_EAR               (0x11A)
1521#define SPR_TBL               (0x11C)
1522#define SPR_TBU               (0x11D)
1523#define SPR_TBU40             (0x11E)
1524#define SPR_SVR               (0x11E)
1525#define SPR_BOOKE_PIR         (0x11E)
1526#define SPR_PVR               (0x11F)
1527#define SPR_HSPRG0            (0x130)
1528#define SPR_BOOKE_DBSR        (0x130)
1529#define SPR_HSPRG1            (0x131)
1530#define SPR_HDSISR            (0x132)
1531#define SPR_HDAR              (0x133)
1532#define SPR_BOOKE_EPCR        (0x133)
1533#define SPR_SPURR             (0x134)
1534#define SPR_BOOKE_DBCR0       (0x134)
1535#define SPR_IBCR              (0x135)
1536#define SPR_PURR              (0x135)
1537#define SPR_BOOKE_DBCR1       (0x135)
1538#define SPR_DBCR              (0x136)
1539#define SPR_HDEC              (0x136)
1540#define SPR_BOOKE_DBCR2       (0x136)
1541#define SPR_HIOR              (0x137)
1542#define SPR_MBAR              (0x137)
1543#define SPR_RMOR              (0x138)
1544#define SPR_BOOKE_IAC1        (0x138)
1545#define SPR_HRMOR             (0x139)
1546#define SPR_BOOKE_IAC2        (0x139)
1547#define SPR_HSRR0             (0x13A)
1548#define SPR_BOOKE_IAC3        (0x13A)
1549#define SPR_HSRR1             (0x13B)
1550#define SPR_BOOKE_IAC4        (0x13B)
1551#define SPR_BOOKE_DAC1        (0x13C)
1552#define SPR_MMCRH             (0x13C)
1553#define SPR_DABR2             (0x13D)
1554#define SPR_BOOKE_DAC2        (0x13D)
1555#define SPR_TFMR              (0x13D)
1556#define SPR_BOOKE_DVC1        (0x13E)
1557#define SPR_LPCR              (0x13E)
1558#define SPR_BOOKE_DVC2        (0x13F)
1559#define SPR_LPIDR             (0x13F)
1560#define SPR_BOOKE_TSR         (0x150)
1561#define SPR_HMER              (0x150)
1562#define SPR_HMEER             (0x151)
1563#define SPR_PCR               (0x152)
1564#define SPR_BOOKE_LPIDR       (0x152)
1565#define SPR_BOOKE_TCR         (0x154)
1566#define SPR_BOOKE_TLB0PS      (0x158)
1567#define SPR_BOOKE_TLB1PS      (0x159)
1568#define SPR_BOOKE_TLB2PS      (0x15A)
1569#define SPR_BOOKE_TLB3PS      (0x15B)
1570#define SPR_AMOR              (0x15D)
1571#define SPR_BOOKE_MAS7_MAS3   (0x174)
1572#define SPR_BOOKE_IVOR0       (0x190)
1573#define SPR_BOOKE_IVOR1       (0x191)
1574#define SPR_BOOKE_IVOR2       (0x192)
1575#define SPR_BOOKE_IVOR3       (0x193)
1576#define SPR_BOOKE_IVOR4       (0x194)
1577#define SPR_BOOKE_IVOR5       (0x195)
1578#define SPR_BOOKE_IVOR6       (0x196)
1579#define SPR_BOOKE_IVOR7       (0x197)
1580#define SPR_BOOKE_IVOR8       (0x198)
1581#define SPR_BOOKE_IVOR9       (0x199)
1582#define SPR_BOOKE_IVOR10      (0x19A)
1583#define SPR_BOOKE_IVOR11      (0x19B)
1584#define SPR_BOOKE_IVOR12      (0x19C)
1585#define SPR_BOOKE_IVOR13      (0x19D)
1586#define SPR_BOOKE_IVOR14      (0x19E)
1587#define SPR_BOOKE_IVOR15      (0x19F)
1588#define SPR_BOOKE_IVOR38      (0x1B0)
1589#define SPR_BOOKE_IVOR39      (0x1B1)
1590#define SPR_BOOKE_IVOR40      (0x1B2)
1591#define SPR_BOOKE_IVOR41      (0x1B3)
1592#define SPR_BOOKE_IVOR42      (0x1B4)
1593#define SPR_BOOKE_GIVOR2      (0x1B8)
1594#define SPR_BOOKE_GIVOR3      (0x1B9)
1595#define SPR_BOOKE_GIVOR4      (0x1BA)
1596#define SPR_BOOKE_GIVOR8      (0x1BB)
1597#define SPR_BOOKE_GIVOR13     (0x1BC)
1598#define SPR_BOOKE_GIVOR14     (0x1BD)
1599#define SPR_TIR               (0x1BE)
1600#define SPR_PTCR              (0x1D0)
1601#define SPR_BOOKE_SPEFSCR     (0x200)
1602#define SPR_Exxx_BBEAR        (0x201)
1603#define SPR_Exxx_BBTAR        (0x202)
1604#define SPR_Exxx_L1CFG0       (0x203)
1605#define SPR_Exxx_L1CFG1       (0x204)
1606#define SPR_Exxx_NPIDR        (0x205)
1607#define SPR_ATBL              (0x20E)
1608#define SPR_ATBU              (0x20F)
1609#define SPR_IBAT0U            (0x210)
1610#define SPR_BOOKE_IVOR32      (0x210)
1611#define SPR_RCPU_MI_GRA       (0x210)
1612#define SPR_IBAT0L            (0x211)
1613#define SPR_BOOKE_IVOR33      (0x211)
1614#define SPR_IBAT1U            (0x212)
1615#define SPR_BOOKE_IVOR34      (0x212)
1616#define SPR_IBAT1L            (0x213)
1617#define SPR_BOOKE_IVOR35      (0x213)
1618#define SPR_IBAT2U            (0x214)
1619#define SPR_BOOKE_IVOR36      (0x214)
1620#define SPR_IBAT2L            (0x215)
1621#define SPR_BOOKE_IVOR37      (0x215)
1622#define SPR_IBAT3U            (0x216)
1623#define SPR_IBAT3L            (0x217)
1624#define SPR_DBAT0U            (0x218)
1625#define SPR_RCPU_L2U_GRA      (0x218)
1626#define SPR_DBAT0L            (0x219)
1627#define SPR_DBAT1U            (0x21A)
1628#define SPR_DBAT1L            (0x21B)
1629#define SPR_DBAT2U            (0x21C)
1630#define SPR_DBAT2L            (0x21D)
1631#define SPR_DBAT3U            (0x21E)
1632#define SPR_DBAT3L            (0x21F)
1633#define SPR_IBAT4U            (0x230)
1634#define SPR_RPCU_BBCMCR       (0x230)
1635#define SPR_MPC_IC_CST        (0x230)
1636#define SPR_Exxx_CTXCR        (0x230)
1637#define SPR_IBAT4L            (0x231)
1638#define SPR_MPC_IC_ADR        (0x231)
1639#define SPR_Exxx_DBCR3        (0x231)
1640#define SPR_IBAT5U            (0x232)
1641#define SPR_MPC_IC_DAT        (0x232)
1642#define SPR_Exxx_DBCNT        (0x232)
1643#define SPR_IBAT5L            (0x233)
1644#define SPR_IBAT6U            (0x234)
1645#define SPR_IBAT6L            (0x235)
1646#define SPR_IBAT7U            (0x236)
1647#define SPR_IBAT7L            (0x237)
1648#define SPR_DBAT4U            (0x238)
1649#define SPR_RCPU_L2U_MCR      (0x238)
1650#define SPR_MPC_DC_CST        (0x238)
1651#define SPR_Exxx_ALTCTXCR     (0x238)
1652#define SPR_DBAT4L            (0x239)
1653#define SPR_MPC_DC_ADR        (0x239)
1654#define SPR_DBAT5U            (0x23A)
1655#define SPR_BOOKE_MCSRR0      (0x23A)
1656#define SPR_MPC_DC_DAT        (0x23A)
1657#define SPR_DBAT5L            (0x23B)
1658#define SPR_BOOKE_MCSRR1      (0x23B)
1659#define SPR_DBAT6U            (0x23C)
1660#define SPR_BOOKE_MCSR        (0x23C)
1661#define SPR_DBAT6L            (0x23D)
1662#define SPR_Exxx_MCAR         (0x23D)
1663#define SPR_DBAT7U            (0x23E)
1664#define SPR_BOOKE_DSRR0       (0x23E)
1665#define SPR_DBAT7L            (0x23F)
1666#define SPR_BOOKE_DSRR1       (0x23F)
1667#define SPR_BOOKE_SPRG8       (0x25C)
1668#define SPR_BOOKE_SPRG9       (0x25D)
1669#define SPR_BOOKE_MAS0        (0x270)
1670#define SPR_BOOKE_MAS1        (0x271)
1671#define SPR_BOOKE_MAS2        (0x272)
1672#define SPR_BOOKE_MAS3        (0x273)
1673#define SPR_BOOKE_MAS4        (0x274)
1674#define SPR_BOOKE_MAS5        (0x275)
1675#define SPR_BOOKE_MAS6        (0x276)
1676#define SPR_BOOKE_PID1        (0x279)
1677#define SPR_BOOKE_PID2        (0x27A)
1678#define SPR_MPC_DPDR          (0x280)
1679#define SPR_MPC_IMMR          (0x288)
1680#define SPR_BOOKE_TLB0CFG     (0x2B0)
1681#define SPR_BOOKE_TLB1CFG     (0x2B1)
1682#define SPR_BOOKE_TLB2CFG     (0x2B2)
1683#define SPR_BOOKE_TLB3CFG     (0x2B3)
1684#define SPR_BOOKE_EPR         (0x2BE)
1685#define SPR_PERF0             (0x300)
1686#define SPR_RCPU_MI_RBA0      (0x300)
1687#define SPR_MPC_MI_CTR        (0x300)
1688#define SPR_POWER_USIER       (0x300)
1689#define SPR_PERF1             (0x301)
1690#define SPR_RCPU_MI_RBA1      (0x301)
1691#define SPR_POWER_UMMCR2      (0x301)
1692#define SPR_PERF2             (0x302)
1693#define SPR_RCPU_MI_RBA2      (0x302)
1694#define SPR_MPC_MI_AP         (0x302)
1695#define SPR_POWER_UMMCRA      (0x302)
1696#define SPR_PERF3             (0x303)
1697#define SPR_RCPU_MI_RBA3      (0x303)
1698#define SPR_MPC_MI_EPN        (0x303)
1699#define SPR_POWER_UPMC1       (0x303)
1700#define SPR_PERF4             (0x304)
1701#define SPR_POWER_UPMC2       (0x304)
1702#define SPR_PERF5             (0x305)
1703#define SPR_MPC_MI_TWC        (0x305)
1704#define SPR_POWER_UPMC3       (0x305)
1705#define SPR_PERF6             (0x306)
1706#define SPR_MPC_MI_RPN        (0x306)
1707#define SPR_POWER_UPMC4       (0x306)
1708#define SPR_PERF7             (0x307)
1709#define SPR_POWER_UPMC5       (0x307)
1710#define SPR_PERF8             (0x308)
1711#define SPR_RCPU_L2U_RBA0     (0x308)
1712#define SPR_MPC_MD_CTR        (0x308)
1713#define SPR_POWER_UPMC6       (0x308)
1714#define SPR_PERF9             (0x309)
1715#define SPR_RCPU_L2U_RBA1     (0x309)
1716#define SPR_MPC_MD_CASID      (0x309)
1717#define SPR_970_UPMC7         (0X309)
1718#define SPR_PERFA             (0x30A)
1719#define SPR_RCPU_L2U_RBA2     (0x30A)
1720#define SPR_MPC_MD_AP         (0x30A)
1721#define SPR_970_UPMC8         (0X30A)
1722#define SPR_PERFB             (0x30B)
1723#define SPR_RCPU_L2U_RBA3     (0x30B)
1724#define SPR_MPC_MD_EPN        (0x30B)
1725#define SPR_POWER_UMMCR0      (0X30B)
1726#define SPR_PERFC             (0x30C)
1727#define SPR_MPC_MD_TWB        (0x30C)
1728#define SPR_POWER_USIAR       (0X30C)
1729#define SPR_PERFD             (0x30D)
1730#define SPR_MPC_MD_TWC        (0x30D)
1731#define SPR_POWER_USDAR       (0X30D)
1732#define SPR_PERFE             (0x30E)
1733#define SPR_MPC_MD_RPN        (0x30E)
1734#define SPR_POWER_UMMCR1      (0X30E)
1735#define SPR_PERFF             (0x30F)
1736#define SPR_MPC_MD_TW         (0x30F)
1737#define SPR_UPERF0            (0x310)
1738#define SPR_POWER_SIER        (0x310)
1739#define SPR_UPERF1            (0x311)
1740#define SPR_POWER_MMCR2       (0x311)
1741#define SPR_UPERF2            (0x312)
1742#define SPR_POWER_MMCRA       (0X312)
1743#define SPR_UPERF3            (0x313)
1744#define SPR_POWER_PMC1        (0X313)
1745#define SPR_UPERF4            (0x314)
1746#define SPR_POWER_PMC2        (0X314)
1747#define SPR_UPERF5            (0x315)
1748#define SPR_POWER_PMC3        (0X315)
1749#define SPR_UPERF6            (0x316)
1750#define SPR_POWER_PMC4        (0X316)
1751#define SPR_UPERF7            (0x317)
1752#define SPR_POWER_PMC5        (0X317)
1753#define SPR_UPERF8            (0x318)
1754#define SPR_POWER_PMC6        (0X318)
1755#define SPR_UPERF9            (0x319)
1756#define SPR_970_PMC7          (0X319)
1757#define SPR_UPERFA            (0x31A)
1758#define SPR_970_PMC8          (0X31A)
1759#define SPR_UPERFB            (0x31B)
1760#define SPR_POWER_MMCR0       (0X31B)
1761#define SPR_UPERFC            (0x31C)
1762#define SPR_POWER_SIAR        (0X31C)
1763#define SPR_UPERFD            (0x31D)
1764#define SPR_POWER_SDAR        (0X31D)
1765#define SPR_UPERFE            (0x31E)
1766#define SPR_POWER_MMCR1       (0X31E)
1767#define SPR_UPERFF            (0x31F)
1768#define SPR_RCPU_MI_RA0       (0x320)
1769#define SPR_MPC_MI_DBCAM      (0x320)
1770#define SPR_BESCRS            (0x320)
1771#define SPR_RCPU_MI_RA1       (0x321)
1772#define SPR_MPC_MI_DBRAM0     (0x321)
1773#define SPR_BESCRSU           (0x321)
1774#define SPR_RCPU_MI_RA2       (0x322)
1775#define SPR_MPC_MI_DBRAM1     (0x322)
1776#define SPR_BESCRR            (0x322)
1777#define SPR_RCPU_MI_RA3       (0x323)
1778#define SPR_BESCRRU           (0x323)
1779#define SPR_EBBHR             (0x324)
1780#define SPR_EBBRR             (0x325)
1781#define SPR_BESCR             (0x326)
1782#define SPR_RCPU_L2U_RA0      (0x328)
1783#define SPR_MPC_MD_DBCAM      (0x328)
1784#define SPR_RCPU_L2U_RA1      (0x329)
1785#define SPR_MPC_MD_DBRAM0     (0x329)
1786#define SPR_RCPU_L2U_RA2      (0x32A)
1787#define SPR_MPC_MD_DBRAM1     (0x32A)
1788#define SPR_RCPU_L2U_RA3      (0x32B)
1789#define SPR_TAR               (0x32F)
1790#define SPR_ASDR              (0x330)
1791#define SPR_IC                (0x350)
1792#define SPR_VTB               (0x351)
1793#define SPR_MMCRC             (0x353)
1794#define SPR_PSSCR             (0x357)
1795#define SPR_440_INV0          (0x370)
1796#define SPR_440_INV1          (0x371)
1797#define SPR_440_INV2          (0x372)
1798#define SPR_440_INV3          (0x373)
1799#define SPR_440_ITV0          (0x374)
1800#define SPR_440_ITV1          (0x375)
1801#define SPR_440_ITV2          (0x376)
1802#define SPR_440_ITV3          (0x377)
1803#define SPR_440_CCR1          (0x378)
1804#define SPR_TACR              (0x378)
1805#define SPR_TCSCR             (0x379)
1806#define SPR_CSIGR             (0x37a)
1807#define SPR_DCRIPR            (0x37B)
1808#define SPR_POWER_SPMC1       (0x37C)
1809#define SPR_POWER_SPMC2       (0x37D)
1810#define SPR_POWER_MMCRS       (0x37E)
1811#define SPR_WORT              (0x37F)
1812#define SPR_PPR               (0x380)
1813#define SPR_750_GQR0          (0x390)
1814#define SPR_440_DNV0          (0x390)
1815#define SPR_750_GQR1          (0x391)
1816#define SPR_440_DNV1          (0x391)
1817#define SPR_750_GQR2          (0x392)
1818#define SPR_440_DNV2          (0x392)
1819#define SPR_750_GQR3          (0x393)
1820#define SPR_440_DNV3          (0x393)
1821#define SPR_750_GQR4          (0x394)
1822#define SPR_440_DTV0          (0x394)
1823#define SPR_750_GQR5          (0x395)
1824#define SPR_440_DTV1          (0x395)
1825#define SPR_750_GQR6          (0x396)
1826#define SPR_440_DTV2          (0x396)
1827#define SPR_750_GQR7          (0x397)
1828#define SPR_440_DTV3          (0x397)
1829#define SPR_750_THRM4         (0x398)
1830#define SPR_750CL_HID2        (0x398)
1831#define SPR_440_DVLIM         (0x398)
1832#define SPR_750_WPAR          (0x399)
1833#define SPR_440_IVLIM         (0x399)
1834#define SPR_TSCR              (0x399)
1835#define SPR_750_DMAU          (0x39A)
1836#define SPR_750_DMAL          (0x39B)
1837#define SPR_440_RSTCFG        (0x39B)
1838#define SPR_BOOKE_DCDBTRL     (0x39C)
1839#define SPR_BOOKE_DCDBTRH     (0x39D)
1840#define SPR_BOOKE_ICDBTRL     (0x39E)
1841#define SPR_BOOKE_ICDBTRH     (0x39F)
1842#define SPR_74XX_UMMCR2       (0x3A0)
1843#define SPR_7XX_UPMC5         (0x3A1)
1844#define SPR_7XX_UPMC6         (0x3A2)
1845#define SPR_UBAMR             (0x3A7)
1846#define SPR_7XX_UMMCR0        (0x3A8)
1847#define SPR_7XX_UPMC1         (0x3A9)
1848#define SPR_7XX_UPMC2         (0x3AA)
1849#define SPR_7XX_USIAR         (0x3AB)
1850#define SPR_7XX_UMMCR1        (0x3AC)
1851#define SPR_7XX_UPMC3         (0x3AD)
1852#define SPR_7XX_UPMC4         (0x3AE)
1853#define SPR_USDA              (0x3AF)
1854#define SPR_40x_ZPR           (0x3B0)
1855#define SPR_BOOKE_MAS7        (0x3B0)
1856#define SPR_74XX_MMCR2        (0x3B0)
1857#define SPR_7XX_PMC5          (0x3B1)
1858#define SPR_40x_PID           (0x3B1)
1859#define SPR_7XX_PMC6          (0x3B2)
1860#define SPR_440_MMUCR         (0x3B2)
1861#define SPR_4xx_CCR0          (0x3B3)
1862#define SPR_BOOKE_EPLC        (0x3B3)
1863#define SPR_405_IAC3          (0x3B4)
1864#define SPR_BOOKE_EPSC        (0x3B4)
1865#define SPR_405_IAC4          (0x3B5)
1866#define SPR_405_DVC1          (0x3B6)
1867#define SPR_405_DVC2          (0x3B7)
1868#define SPR_BAMR              (0x3B7)
1869#define SPR_7XX_MMCR0         (0x3B8)
1870#define SPR_7XX_PMC1          (0x3B9)
1871#define SPR_40x_SGR           (0x3B9)
1872#define SPR_7XX_PMC2          (0x3BA)
1873#define SPR_40x_DCWR          (0x3BA)
1874#define SPR_7XX_SIAR          (0x3BB)
1875#define SPR_405_SLER          (0x3BB)
1876#define SPR_7XX_MMCR1         (0x3BC)
1877#define SPR_405_SU0R          (0x3BC)
1878#define SPR_401_SKR           (0x3BC)
1879#define SPR_7XX_PMC3          (0x3BD)
1880#define SPR_405_DBCR1         (0x3BD)
1881#define SPR_7XX_PMC4          (0x3BE)
1882#define SPR_SDA               (0x3BF)
1883#define SPR_403_VTBL          (0x3CC)
1884#define SPR_403_VTBU          (0x3CD)
1885#define SPR_DMISS             (0x3D0)
1886#define SPR_DCMP              (0x3D1)
1887#define SPR_HASH1             (0x3D2)
1888#define SPR_HASH2             (0x3D3)
1889#define SPR_BOOKE_ICDBDR      (0x3D3)
1890#define SPR_TLBMISS           (0x3D4)
1891#define SPR_IMISS             (0x3D4)
1892#define SPR_40x_ESR           (0x3D4)
1893#define SPR_PTEHI             (0x3D5)
1894#define SPR_ICMP              (0x3D5)
1895#define SPR_40x_DEAR          (0x3D5)
1896#define SPR_PTELO             (0x3D6)
1897#define SPR_RPA               (0x3D6)
1898#define SPR_40x_EVPR          (0x3D6)
1899#define SPR_L3PM              (0x3D7)
1900#define SPR_403_CDBCR         (0x3D7)
1901#define SPR_L3ITCR0           (0x3D8)
1902#define SPR_TCR               (0x3D8)
1903#define SPR_40x_TSR           (0x3D8)
1904#define SPR_IBR               (0x3DA)
1905#define SPR_40x_TCR           (0x3DA)
1906#define SPR_ESASRR            (0x3DB)
1907#define SPR_40x_PIT           (0x3DB)
1908#define SPR_403_TBL           (0x3DC)
1909#define SPR_403_TBU           (0x3DD)
1910#define SPR_SEBR              (0x3DE)
1911#define SPR_40x_SRR2          (0x3DE)
1912#define SPR_SER               (0x3DF)
1913#define SPR_40x_SRR3          (0x3DF)
1914#define SPR_L3OHCR            (0x3E8)
1915#define SPR_L3ITCR1           (0x3E9)
1916#define SPR_L3ITCR2           (0x3EA)
1917#define SPR_L3ITCR3           (0x3EB)
1918#define SPR_HID0              (0x3F0)
1919#define SPR_40x_DBSR          (0x3F0)
1920#define SPR_HID1              (0x3F1)
1921#define SPR_IABR              (0x3F2)
1922#define SPR_40x_DBCR0         (0x3F2)
1923#define SPR_601_HID2          (0x3F2)
1924#define SPR_Exxx_L1CSR0       (0x3F2)
1925#define SPR_ICTRL             (0x3F3)
1926#define SPR_HID2              (0x3F3)
1927#define SPR_750CL_HID4        (0x3F3)
1928#define SPR_Exxx_L1CSR1       (0x3F3)
1929#define SPR_440_DBDR          (0x3F3)
1930#define SPR_LDSTDB            (0x3F4)
1931#define SPR_750_TDCL          (0x3F4)
1932#define SPR_40x_IAC1          (0x3F4)
1933#define SPR_MMUCSR0           (0x3F4)
1934#define SPR_970_HID4          (0x3F4)
1935#define SPR_DABR              (0x3F5)
1936#define DABR_MASK (~(target_ulong)0x7)
1937#define SPR_Exxx_BUCSR        (0x3F5)
1938#define SPR_40x_IAC2          (0x3F5)
1939#define SPR_601_HID5          (0x3F5)
1940#define SPR_40x_DAC1          (0x3F6)
1941#define SPR_MSSCR0            (0x3F6)
1942#define SPR_970_HID5          (0x3F6)
1943#define SPR_MSSSR0            (0x3F7)
1944#define SPR_MSSCR1            (0x3F7)
1945#define SPR_DABRX             (0x3F7)
1946#define SPR_40x_DAC2          (0x3F7)
1947#define SPR_MMUCFG            (0x3F7)
1948#define SPR_LDSTCR            (0x3F8)
1949#define SPR_L2PMCR            (0x3F8)
1950#define SPR_750FX_HID2        (0x3F8)
1951#define SPR_Exxx_L1FINV0      (0x3F8)
1952#define SPR_L2CR              (0x3F9)
1953#define SPR_Exxx_L2CSR0       (0x3F9)
1954#define SPR_L3CR              (0x3FA)
1955#define SPR_750_TDCH          (0x3FA)
1956#define SPR_IABR2             (0x3FA)
1957#define SPR_40x_DCCR          (0x3FA)
1958#define SPR_ICTC              (0x3FB)
1959#define SPR_40x_ICCR          (0x3FB)
1960#define SPR_THRM1             (0x3FC)
1961#define SPR_403_PBL1          (0x3FC)
1962#define SPR_SP                (0x3FD)
1963#define SPR_THRM2             (0x3FD)
1964#define SPR_403_PBU1          (0x3FD)
1965#define SPR_604_HID13         (0x3FD)
1966#define SPR_LT                (0x3FE)
1967#define SPR_THRM3             (0x3FE)
1968#define SPR_RCPU_FPECR        (0x3FE)
1969#define SPR_403_PBL2          (0x3FE)
1970#define SPR_PIR               (0x3FF)
1971#define SPR_403_PBU2          (0x3FF)
1972#define SPR_601_HID15         (0x3FF)
1973#define SPR_604_HID15         (0x3FF)
1974#define SPR_E500_SVR          (0x3FF)
1975
1976/* Disable MAS Interrupt Updates for Hypervisor */
1977#define EPCR_DMIUH            (1 << 22)
1978/* Disable Guest TLB Management Instructions */
1979#define EPCR_DGTMI            (1 << 23)
1980/* Guest Interrupt Computation Mode */
1981#define EPCR_GICM             (1 << 24)
1982/* Interrupt Computation Mode */
1983#define EPCR_ICM              (1 << 25)
1984/* Disable Embedded Hypervisor Debug */
1985#define EPCR_DUVD             (1 << 26)
1986/* Instruction Storage Interrupt Directed to Guest State */
1987#define EPCR_ISIGS            (1 << 27)
1988/* Data Storage Interrupt Directed to Guest State */
1989#define EPCR_DSIGS            (1 << 28)
1990/* Instruction TLB Error Interrupt Directed to Guest State */
1991#define EPCR_ITLBGS           (1 << 29)
1992/* Data TLB Error Interrupt Directed to Guest State */
1993#define EPCR_DTLBGS           (1 << 30)
1994/* External Input Interrupt Directed to Guest State */
1995#define EPCR_EXTGS            (1 << 31)
1996
1997#define   L1CSR0_CPE    0x00010000  /* Data Cache Parity Enable */
1998#define   L1CSR0_CUL    0x00000400  /* (D-)Cache Unable to Lock */
1999#define   L1CSR0_DCLFR  0x00000100  /* D-Cache Lock Flash Reset */
2000#define   L1CSR0_DCFI   0x00000002  /* Data Cache Flash Invalidate */

2001#define   L1CSR0_DCE    0x00000001  /* Data Cache Enable */
2002
2003#define   L1CSR1_CPE    0x00010000  /* Instruction Cache Parity Enable */
2004#define   L1CSR1_ICUL   0x00000400  /* I-Cache Unable to Lock */
2005#define   L1CSR1_ICLFR  0x00000100  /* I-Cache Lock Flash Reset */
2006#define   L1CSR1_ICFI   0x00000002  /* Instruction Cache Flash Invalidate */
2007#define   L1CSR1_ICE    0x00000001  /* Instruction Cache Enable */
2008
2009/* E500 L2CSR0 */
2010#define E500_L2CSR0_L2FI    (1 << 21)   /* L2 cache flash invalidate */
2011#define E500_L2CSR0_L2FL    (1 << 11)   /* L2 cache flush */
2012#define E500_L2CSR0_L2LFC   (1 << 10)   /* L2 cache lock flash clear */
2013
2014/* HID0 bits */
2015#define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
2016#define HID0_DOZE           (1 << 23)           /* pre-2.06 */
2017#define HID0_NAP            (1 << 22)           /* pre-2.06 */
2018#define HID0_HILE           PPC_BIT(19) /* POWER8 */
2019#define HID0_POWER9_HILE    PPC_BIT(4)
2020
2021/*****************************************************************************/
2022/* PowerPC Instructions types definitions                                    */
2023enum {
2024    PPC_NONE           = 0x0000000000000000ULL,
2025    /* PowerPC base instructions set                                         */
2026    PPC_INSNS_BASE     = 0x0000000000000001ULL,
2027    /*   integer operations instructions                                     */
2028#define PPC_INTEGER PPC_INSNS_BASE
2029    /*   flow control instructions                                           */
2030#define PPC_FLOW    PPC_INSNS_BASE
2031    /*   virtual memory instructions                                         */
2032#define PPC_MEM     PPC_INSNS_BASE
2033    /*   ld/st with reservation instructions                                 */
2034#define PPC_RES     PPC_INSNS_BASE
2035    /*   spr/msr access instructions                                         */
2036#define PPC_MISC    PPC_INSNS_BASE
2037    /* Deprecated instruction sets                                           */
2038    /*   Original POWER instruction set                                      */
2039    PPC_POWER          = 0x0000000000000002ULL,
2040    /*   POWER2 instruction set extension                                    */
2041    PPC_POWER2         = 0x0000000000000004ULL,
2042    /*   Power RTC support                                                   */
2043    PPC_POWER_RTC      = 0x0000000000000008ULL,
2044    /*   Power-to-PowerPC bridge (601)                                       */
2045    PPC_POWER_BR       = 0x0000000000000010ULL,
2046    /* 64 bits PowerPC instruction set                                       */
2047    PPC_64B            = 0x0000000000000020ULL,
2048    /*   New 64 bits extensions (PowerPC 2.0x)                               */
2049    PPC_64BX           = 0x0000000000000040ULL,
2050    /*   64 bits hypervisor extensions                                       */
2051    PPC_64H            = 0x0000000000000080ULL,
2052    /*   New wait instruction (PowerPC 2.0x)                                 */
2053    PPC_WAIT           = 0x0000000000000100ULL,
2054    /*   Time base mftb instruction                                          */
2055    PPC_MFTB           = 0x0000000000000200ULL,
2056
2057    /* Fixed-point unit extensions                                           */
2058    /*   PowerPC 602 specific                                                */
2059    PPC_602_SPEC       = 0x0000000000000400ULL,
2060    /*   isel instruction                                                    */
2061    PPC_ISEL           = 0x0000000000000800ULL,
2062    /*   popcntb instruction                                                 */
2063    PPC_POPCNTB        = 0x0000000000001000ULL,
2064    /*   string load / store                                                 */
2065    PPC_STRING         = 0x0000000000002000ULL,
2066    /*   real mode cache inhibited load / store                              */
2067    PPC_CILDST         = 0x0000000000004000ULL,
2068
2069    /* Floating-point unit extensions                                        */
2070    /*   Optional floating point instructions                                */
2071    PPC_FLOAT          = 0x0000000000010000ULL,
2072    /* New floating-point extensions (PowerPC 2.0x)                          */
2073    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2074    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2075    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2076    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2077    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2078    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2079    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2080
2081    /* Vector/SIMD extensions                                                */
2082    /*   Altivec support                                                     */
2083    PPC_ALTIVEC        = 0x0000000001000000ULL,
2084    /*   PowerPC 2.03 SPE extension                                          */
2085    PPC_SPE            = 0x0000000002000000ULL,
2086    /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2087    PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2088    /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2089    PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2090
2091    /* Optional memory control instructions                                  */
2092    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2093    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2094    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2095    /*   sync instruction                                                    */
2096    PPC_MEM_SYNC       = 0x0000000080000000ULL,
2097    /*   eieio instruction                                                   */
2098    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2099
2100    /* Cache control instructions                                            */
2101    PPC_CACHE          = 0x0000000200000000ULL,
2102    /*   icbi instruction                                                    */
2103    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2104    /*   dcbz instruction                                                    */
2105    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2106    /*   dcba instruction                                                    */
2107    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2108    /*   Freescale cache locking instructions                                */
2109    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2110
2111    /* MMU related extensions                                                */
2112    /*   external control instructions                                       */
2113    PPC_EXTERN         = 0x0000010000000000ULL,
2114    /*   segment register access instructions                                */
2115    PPC_SEGMENT        = 0x0000020000000000ULL,
2116    /*   PowerPC 6xx TLB management instructions                             */
2117    PPC_6xx_TLB        = 0x0000040000000000ULL,
2118    /* PowerPC 74xx TLB management instructions                              */
2119    PPC_74xx_TLB       = 0x0000080000000000ULL,
2120    /*   PowerPC 40x TLB management instructions                             */
2121    PPC_40x_TLB        = 0x0000100000000000ULL,
2122    /*   segment register access instructions for PowerPC 64 "bridge"        */
2123    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2124    /*   SLB management                                                      */
2125    PPC_SLBI           = 0x0000400000000000ULL,
2126
2127    /* Embedded PowerPC dedicated instructions                               */
2128    PPC_WRTEE          = 0x0001000000000000ULL,
2129    /* PowerPC 40x exception model                                           */
2130    PPC_40x_EXCP       = 0x0002000000000000ULL,
2131    /* PowerPC 405 Mac instructions                                          */
2132    PPC_405_MAC        = 0x0004000000000000ULL,
2133    /* PowerPC 440 specific instructions                                     */
2134    PPC_440_SPEC       = 0x0008000000000000ULL,
2135    /* BookE (embedded) PowerPC specification                                */
2136    PPC_BOOKE          = 0x0010000000000000ULL,
2137    /* mfapidi instruction                                                   */
2138    PPC_MFAPIDI        = 0x0020000000000000ULL,
2139    /* tlbiva instruction                                                    */
2140    PPC_TLBIVA         = 0x0040000000000000ULL,
2141    /* tlbivax instruction                                                   */
2142    PPC_TLBIVAX        = 0x0080000000000000ULL,
2143    /* PowerPC 4xx dedicated instructions                                    */
2144    PPC_4xx_COMMON     = 0x0100000000000000ULL,
2145    /* PowerPC 40x ibct instructions                                         */
2146    PPC_40x_ICBT       = 0x0200000000000000ULL,
2147    /* rfmci is not implemented in all BookE PowerPC                         */
2148    PPC_RFMCI          = 0x0400000000000000ULL,
2149    /* rfdi instruction                                                      */
2150    PPC_RFDI           = 0x0800000000000000ULL,
2151    /* DCR accesses                                                          */
2152    PPC_DCR            = 0x1000000000000000ULL,
2153    /* DCR extended accesse                                                  */
2154    PPC_DCRX           = 0x2000000000000000ULL,
2155    /* user-mode DCR access, implemented in PowerPC 460                      */
2156    PPC_DCRUX          = 0x4000000000000000ULL,
2157    /* popcntw and popcntd instructions                                      */
2158    PPC_POPCNTWD       = 0x8000000000000000ULL,
2159
2160#define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2161                        | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2162                        | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2163                        | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2164                        | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2165                        | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2166                        | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2167                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2168                        | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2169                        | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2170                        | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2171                        | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2172                        | PPC_CACHE | PPC_CACHE_ICBI \
2173                        | PPC_CACHE_DCBZ \
2174                        | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2175                        | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2176                        | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2177                        | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2178                        | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2179                        | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2180                        | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2181                        | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2182                        | PPC_POPCNTWD | PPC_CILDST)
2183
2184    /* extended type values */
2185
2186    /* BookE 2.06 PowerPC specification                                      */
2187    PPC2_BOOKE206      = 0x0000000000000001ULL,
2188    /* VSX (extensions to Altivec / VMX)                                     */
2189    PPC2_VSX           = 0x0000000000000002ULL,
2190    /* Decimal Floating Point (DFP)                                          */
2191    PPC2_DFP           = 0x0000000000000004ULL,
2192    /* Embedded.Processor Control                                            */
2193    PPC2_PRCNTL        = 0x0000000000000008ULL,
2194    /* Byte-reversed, indexed, double-word load and store                    */
2195    PPC2_DBRX          = 0x0000000000000010ULL,
2196    /* Book I 2.05 PowerPC specification                                     */
2197    PPC2_ISA205        = 0x0000000000000020ULL,
2198    /* VSX additions in ISA 2.07                                             */
2199    PPC2_VSX207        = 0x0000000000000040ULL,
2200    /* ISA 2.06B bpermd                                                      */
2201    PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2202    /* ISA 2.06B divide extended variants                                    */
2203    PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2204    /* ISA 2.06B larx/stcx. instructions                                     */
2205    PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2206    /* ISA 2.06B floating point integer conversion                           */
2207    PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2208    /* ISA 2.06B floating point test instructions                            */
2209    PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2210    /* ISA 2.07 bctar instruction                                            */
2211    PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2212    /* ISA 2.07 load/store quadword                                          */
2213    PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2214    /* ISA 2.07 Altivec                                                      */
2215    PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2216    /* PowerISA 2.07 Book3s specification                                    */
2217    PPC2_ISA207S       = 0x0000000000008000ULL,
2218    /* Double precision floating point conversion for signed integer 64      */
2219    PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2220    /* Transactional Memory (ISA 2.07, Book II)                              */
2221    PPC2_TM            = 0x0000000000020000ULL,
2222    /* Server PM instructgions (ISA 2.06, Book III)                          */
2223    PPC2_PM_ISA206     = 0x0000000000040000ULL,
2224    /* POWER ISA 3.0                                                         */
2225    PPC2_ISA300        = 0x0000000000080000ULL,
2226    /* POWER ISA 3.1                                                         */
2227    PPC2_ISA310        = 0x0000000000100000ULL,
2228
2229#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2230                        PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2231                        PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2232                        PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2233                        PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2234                        PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2235                        PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2236                        PPC2_ISA300 | PPC2_ISA310)
2237};
2238
2239/*****************************************************************************/
2240/*
2241 * Memory access type :
2242 * may be needed for precise access rights control and precise exceptions.
2243 */
2244enum {
2245    /* Type of instruction that generated the access */
2246    ACCESS_CODE  = 0x10, /* Code fetch access                */
2247    ACCESS_INT   = 0x20, /* Integer load/store access        */
2248    ACCESS_FLOAT = 0x30, /* floating point load/store access */
2249    ACCESS_RES   = 0x40, /* load/store with reservation      */
2250    ACCESS_EXT   = 0x50, /* external access                  */
2251    ACCESS_CACHE = 0x60, /* Cache manipulation               */
2252};
2253
2254/*
2255 * Hardware interrupt sources:
2256 *   all those exception can be raised simulteaneously
2257 */
2258/* Input pins definitions */
2259enum {
2260    /* 6xx bus input pins */
2261    PPC6xx_INPUT_HRESET     = 0,
2262    PPC6xx_INPUT_SRESET     = 1,
2263    PPC6xx_INPUT_CKSTP_IN   = 2,
2264    PPC6xx_INPUT_MCP        = 3,
2265    PPC6xx_INPUT_SMI        = 4,
2266    PPC6xx_INPUT_INT        = 5,
2267    PPC6xx_INPUT_TBEN       = 6,
2268    PPC6xx_INPUT_WAKEUP     = 7,
2269    PPC6xx_INPUT_NB,
2270};
2271
2272enum {
2273    /* Embedded PowerPC input pins */
2274    PPCBookE_INPUT_HRESET     = 0,
2275    PPCBookE_INPUT_SRESET     = 1,
2276    PPCBookE_INPUT_CKSTP_IN   = 2,
2277    PPCBookE_INPUT_MCP        = 3,
2278    PPCBookE_INPUT_SMI        = 4,
2279    PPCBookE_INPUT_INT        = 5,
2280    PPCBookE_INPUT_CINT       = 6,
2281    PPCBookE_INPUT_NB,
2282};
2283
2284enum {
2285    /* PowerPC E500 input pins */
2286    PPCE500_INPUT_RESET_CORE = 0,
2287    PPCE500_INPUT_MCK        = 1,
2288    PPCE500_INPUT_CINT       = 3,
2289    PPCE500_INPUT_INT        = 4,
2290    PPCE500_INPUT_DEBUG      = 6,
2291    PPCE500_INPUT_NB,
2292};
2293
2294enum {
2295    /* PowerPC 40x input pins */
2296    PPC40x_INPUT_RESET_CORE = 0,
2297    PPC40x_INPUT_RESET_CHIP = 1,
2298    PPC40x_INPUT_RESET_SYS  = 2,
2299    PPC40x_INPUT_CINT       = 3,
2300    PPC40x_INPUT_INT        = 4,
2301    PPC40x_INPUT_HALT       = 5,
2302    PPC40x_INPUT_DEBUG      = 6,
2303    PPC40x_INPUT_NB,
2304};
2305
2306enum {
2307    /* RCPU input pins */
2308    PPCRCPU_INPUT_PORESET   = 0,
2309    PPCRCPU_INPUT_HRESET    = 1,
2310    PPCRCPU_INPUT_SRESET    = 2,
2311    PPCRCPU_INPUT_IRQ0      = 3,
2312    PPCRCPU_INPUT_IRQ1      = 4,
2313    PPCRCPU_INPUT_IRQ2      = 5,
2314    PPCRCPU_INPUT_IRQ3      = 6,
2315    PPCRCPU_INPUT_IRQ4      = 7,
2316    PPCRCPU_INPUT_IRQ5      = 8,
2317    PPCRCPU_INPUT_IRQ6      = 9,
2318    PPCRCPU_INPUT_IRQ7      = 10,
2319    PPCRCPU_INPUT_NB,
2320};
2321
2322#if defined(TARGET_PPC64)
2323enum {
2324    /* PowerPC 970 input pins */
2325    PPC970_INPUT_HRESET     = 0,
2326    PPC970_INPUT_SRESET     = 1,
2327    PPC970_INPUT_CKSTP      = 2,
2328    PPC970_INPUT_TBEN       = 3,
2329    PPC970_INPUT_MCP        = 4,
2330    PPC970_INPUT_INT        = 5,
2331    PPC970_INPUT_THINT      = 6,
2332    PPC970_INPUT_NB,
2333};
2334
2335enum {
2336    /* POWER7 input pins */
2337    POWER7_INPUT_INT        = 0,
2338    /*
2339     * POWER7 probably has other inputs, but we don't care about them
2340     * for any existing machine.  We can wire these up when we need
2341     * them
2342     */
2343    POWER7_INPUT_NB,
2344};
2345
2346enum {
2347    /* POWER9 input pins */
2348    POWER9_INPUT_INT        = 0,
2349    POWER9_INPUT_HINT       = 1,
2350    POWER9_INPUT_NB,
2351};
2352#endif
2353
2354/* Hardware exceptions definitions */
2355enum {
2356    /* External hardware exception sources */
2357    PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2358    PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2359    PPC_INTERRUPT_MCK,            /* Machine check exception              */
2360    PPC_INTERRUPT_EXT,            /* External interrupt                   */
2361    PPC_INTERRUPT_SMI,            /* System management interrupt          */
2362    PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2363    PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2364    PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2365    /* Internal hardware exception sources */
2366    PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2367    PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2368    PPC_INTERRUPT_PIT,            /* Programmable interval timer interrupt */
2369    PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2370    PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2371    PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2372    PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2373    PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2374    PPC_INTERRUPT_HMI,            /* Hypervisor Maintenance interrupt    */
2375    PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2376    PPC_INTERRUPT_HVIRT,          /* Hypervisor virtualization interrupt  */
2377};
2378
2379/* Processor Compatibility mask (PCR) */
2380enum {
2381    PCR_COMPAT_2_05     = PPC_BIT(62),
2382    PCR_COMPAT_2_06     = PPC_BIT(61),
2383    PCR_COMPAT_2_07     = PPC_BIT(60),
2384    PCR_COMPAT_3_00     = PPC_BIT(59),
2385    PCR_COMPAT_3_10     = PPC_BIT(58),
2386    PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2387    PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2388    PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2389};
2390
2391/* HMER/HMEER */
2392enum {
2393    HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
2394    HMER_PROC_RECV_DONE         = PPC_BIT(2),
2395    HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2396    HMER_TFAC_ERROR             = PPC_BIT(4),
2397    HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
2398    HMER_XSCOM_FAIL             = PPC_BIT(8),
2399    HMER_XSCOM_DONE             = PPC_BIT(9),
2400    HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
2401    HMER_WARN_RISE              = PPC_BIT(14),
2402    HMER_WARN_FALL              = PPC_BIT(15),
2403    HMER_SCOM_FIR_HMI           = PPC_BIT(16),
2404    HMER_TRIG_FIR_HMI           = PPC_BIT(17),
2405    HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
2406    HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
2407};
2408
2409/*****************************************************************************/
2410
2411#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2412target_ulong cpu_read_xer(CPUPPCState *env);
2413void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2414
2415/*
2416 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2417 * have PPC_SEGMENT_64B.
2418 */
2419#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2420
2421#ifdef CONFIG_DEBUG_TCG
2422void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2423                          target_ulong *cs_base, uint32_t *flags);
2424#else
2425static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2426                                        target_ulong *cs_base, uint32_t *flags)
2427{
2428    *pc = env->nip;
2429    *cs_base = 0;
2430    *flags = env->hflags;
2431}
2432#endif
2433
2434void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2435void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2436                                      uintptr_t raddr);
2437void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2438                                       uint32_t error_code);
2439void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2440                                          uint32_t error_code, uintptr_t raddr);
2441
2442#if !defined(CONFIG_USER_ONLY)
2443static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2444{
2445    uintptr_t tlbml = (uintptr_t)tlbm;
2446    uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2447
2448    return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2449}
2450
2451static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2452{
2453    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2454    int r = tlbncfg & TLBnCFG_N_ENTRY;
2455    return r;
2456}
2457
2458static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2459{
2460    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2461    int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2462    return r;
2463}
2464
2465static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2466{
2467    int id = booke206_tlbm_id(env, tlbm);
2468    int end = 0;
2469    int i;
2470
2471    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2472        end += booke206_tlb_size(env, i);
2473        if (id < end) {
2474            return i;
2475        }
2476    }
2477
2478    cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2479    return 0;
2480}
2481
2482static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2483{
2484    int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2485    int tlbid = booke206_tlbm_id(env, tlb);
2486    return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2487}
2488
2489static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2490                                              target_ulong ea, int way)
2491{
2492    int r;
2493    uint32_t ways = booke206_tlb_ways(env, tlbn);
2494    int ways_bits = ctz32(ways);
2495    int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2496    int i;
2497
2498    way &= ways - 1;
2499    ea >>= MAS2_EPN_SHIFT;
2500    ea &= (1 << (tlb_bits - ways_bits)) - 1;
2501    r = (ea << ways_bits) | way;
2502
2503    if (r >= booke206_tlb_size(env, tlbn)) {
2504        return NULL;
2505    }
2506
2507    /* bump up to tlbn index */
2508    for (i = 0; i < tlbn; i++) {
2509        r += booke206_tlb_size(env, i);
2510    }
2511
2512    return &env->tlb.tlbm[r];
2513}
2514
2515/* returns bitmap of supported page sizes for a given TLB */
2516static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2517{
2518    uint32_t ret = 0;
2519
2520    if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2521        /* MAV2 */
2522        ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2523    } else {
2524        uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2525        uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2526        uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2527        int i;
2528        for (i = min; i <= max; i++) {
2529            ret |= (1 << (i << 1));
2530        }
2531    }
2532
2533    return ret;
2534}
2535
2536static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2537                                            ppcmas_tlb_t *tlb)
2538{
2539    uint8_t i;
2540    int32_t tsize = -1;
2541
2542    for (i = 0; i < 32; i++) {
2543        if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2544            if (tsize == -1) {
2545                tsize = i;
2546            } else {
2547                return;
2548            }
2549        }
2550    }
2551
2552    /* TLBnPS unimplemented? Odd.. */
2553    assert(tsize != -1);
2554    tlb->mas1 &= ~MAS1_TSIZE_MASK;
2555    tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2556}
2557
2558#endif
2559
2560static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2561{
2562    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2563        return msr & (1ULL << MSR_CM);
2564    }
2565
2566    return msr & (1ULL << MSR_SF);
2567}
2568
2569/**
2570 * Check whether register rx is in the range between start and
2571 * start + nregs (as needed by the LSWX and LSWI instructions)
2572 */
2573static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2574{
2575    return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2576           (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2577}
2578
2579/* Accessors for FP, VMX and VSX registers */
2580#if defined(HOST_WORDS_BIGENDIAN)
2581#define VsrB(i) u8[i]
2582#define VsrSB(i) s8[i]
2583#define VsrH(i) u16[i]
2584#define VsrSH(i) s16[i]
2585#define VsrW(i) u32[i]
2586#define VsrSW(i) s32[i]
2587#define VsrD(i) u64[i]
2588#define VsrSD(i) s64[i]
2589#else
2590#define VsrB(i) u8[15 - (i)]
2591#define VsrSB(i) s8[15 - (i)]
2592#define VsrH(i) u16[7 - (i)]
2593#define VsrSH(i) s16[7 - (i)]
2594#define VsrW(i) u32[3 - (i)]
2595#define VsrSW(i) s32[3 - (i)]
2596#define VsrD(i) u64[1 - (i)]
2597#define VsrSD(i) s64[1 - (i)]
2598#endif
2599
2600static inline int vsr64_offset(int i, bool high)
2601{
2602    return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2603}
2604
2605static inline int vsr_full_offset(int i)
2606{
2607    return offsetof(CPUPPCState, vsr[i].u64[0]);
2608}
2609
2610static inline int fpr_offset(int i)
2611{
2612    return vsr64_offset(i, true);
2613}
2614
2615static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2616{
2617    return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2618}
2619
2620static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2621{
2622    return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2623}
2624
2625static inline long avr64_offset(int i, bool high)
2626{
2627    return vsr64_offset(i + 32, high);
2628}
2629
2630static inline int avr_full_offset(int i)
2631{
2632    return vsr_full_offset(i + 32);
2633}
2634
2635static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2636{
2637    return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2638}
2639
2640static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2641{
2642    /* We can test whether the SPR is defined by checking for a valid name */
2643    return cpu->env.spr_cb[spr].name != NULL;
2644}
2645
2646static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu)
2647{
2648    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2649
2650    /*
2651     * Only models that have an LPCR and know about LPCR_ILE can do little
2652     * endian.
2653     */
2654    if (pcc->lpcr_mask & LPCR_ILE) {
2655        return !!(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
2656    }
2657
2658    return false;
2659}
2660
2661void dump_mmu(CPUPPCState *env);
2662
2663void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2664void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
2665uint32_t ppc_get_vscr(CPUPPCState *env);
2666#endif /* PPC_CPU_H */
2667