LXR qemu/tests/tcg/mips/include/wrappers

   1/*
   2 *  Header file for wrappers around MIPS64R6 instructions assembler
   3 *  invocations
   4 *
   5 *  Copyright (C) 2019  Wave Computing, Inc.
   6 *  Copyright (C) 2019  Aleksandar Markovic <amarkovic@wavecomp.com>
   7 *
   8 *  This program is free software: you can redistribute it and/or modify
   9 *  it under the terms of the GNU General Public License as published by
  10 *  the Free Software Foundation, either version 2 of the License, or
  11 *  (at your option) any later version.
  12 *
  13 *  This program is distributed in the hope that it will be useful,
  14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 *  GNU General Public License for more details.
  17 *
  18 *  You should have received a copy of the GNU General Public License
  19 *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
  20 *
  21 */
  22
  23#ifndef WRAPPERS_MIPS64R6_H
  24#define WRAPPERS_MIPS64R6_H
  25
  26
  27#define DO_MIPS64R6__RD__RS(suffix, mnemonic)                          \
  28static inline void do_mips64r6_##suffix(const void *input,             \
  29                                        void *output)                  \
  30{                                                                      \
  31   __asm__ volatile (                                                  \
  32      "ld $t1, 0(%0)\n\t"                                              \
  33      #mnemonic " $t0, $t1\n\t"                                        \
  34      "sd $t0, 0(%1)\n\t"                                              \
  35      :                                                                \
  36      : "r" (input), "r" (output)                                      \
  37      : "t0", "t1", "memory"                                           \
  38   );                                                                  \
  39}
  40
  41DO_MIPS64R6__RD__RS(CLO, clo)
  42DO_MIPS64R6__RD__RS(CLZ, clz)
  43DO_MIPS64R6__RD__RS(DCLO, dclo)
  44DO_MIPS64R6__RD__RS(DCLZ, dclz)
  45
  46DO_MIPS64R6__RD__RS(BITSWAP, bitswap)
  47DO_MIPS64R6__RD__RS(DBITSWAP, dbitswap)
  48
  49
  50#define DO_MIPS64R6__RD__RS_RT(suffix, mnemonic)                       \
  51static inline void do_mips64r6_##suffix(const void *input1,            \
  52                                        const void *input2,            \
  53                                        void *output)                  \
  54{                                                                      \
  55   __asm__ volatile (                                                  \
  56      "ld $t1, 0(%0)\n\t"                                              \
  57      "ld $t2, 0(%1)\n\t"                                              \
  58      #mnemonic " $t0, $t1, $t2\n\t"                                   \
  59      "sd $t0, 0(%2)\n\t"                                              \
  60      :                                                                \
  61      : "r" (input1), "r" (input2), "r" (output)                       \
  62      : "t0", "t1", "memory"                                           \
  63   );                                                                  \
  64}
  65
  66DO_MIPS64R6__RD__RS_RT(SLLV, sllv)
  67DO_MIPS64R6__RD__RS_RT(SRLV, srlv)
  68DO_MIPS64R6__RD__RS_RT(SRAV, srav)
  69DO_MIPS64R6__RD__RS_RT(DSLLV, dsllv)
  70DO_MIPS64R6__RD__RS_RT(DSRLV, dsrlv)
  71DO_MIPS64R6__RD__RS_RT(DSRAV, dsrav)
  72
  73DO_MIPS64R6__RD__RS_RT(MUL, mul)
  74DO_MIPS64R6__RD__RS_RT(MUH, muh)
  75DO_MIPS64R6__RD__RS_RT(MULU, mulu)
  76DO_MIPS64R6__RD__RS_RT(MUHU, muhu)
  77DO_MIPS64R6__RD__RS_RT(DMUL, dmul)
  78DO_MIPS64R6__RD__RS_RT(DMUH, dmuh)
  79DO_MIPS64R6__RD__RS_RT(DMULU, dmulu)
  80DO_MIPS64R6__RD__RS_RT(DMUHU, dmuhu)
  81
  82
  83#endif
  84