1#include "macros.inc"
2
3test_suite break
4
5
6
7#define debug_level XCHAL_DEBUGLEVEL
8#define debug_vector glue(level, XCHAL_DEBUGLEVEL)
9#define EPC_DEBUG glue(epc, XCHAL_DEBUGLEVEL)
10
11test break
12 set_vector debug_vector, 0
13 rsil a2, debug_level
14 _break 0, 0
15
16 set_vector debug_vector, 2f
17 rsil a2, debug_level - 1
181:
19 _break 0, 0
20 test_fail
212:
22 rsr a2, ps
23 movi a3, 0x1f
24 and a2, a2, a3
25 movi a3, 0x10 | debug_level
26 assert eq, a2, a3
27 rsr a2, EPC_DEBUG
28 movi a3, 1b
29 assert eq, a2, a3
30 rsr a2, debugcause
31 movi a3, 0x8
32 assert eq, a2, a3
33test_end
34
35test breakn
36 set_vector debug_vector, 0
37 rsil a2, debug_level
38 _break.n 0
39
40 set_vector debug_vector, 2f
41 rsil a2, debug_level - 1
421:
43 _break.n 0
44 test_fail
452:
46 rsr a2, ps
47 movi a3, 0x1f
48 and a2, a2, a3
49 movi a3, 0x10 | debug_level
50 assert eq, a2, a3
51 rsr a2, EPC_DEBUG
52 movi a3, 1b
53 assert eq, a2, a3
54 rsr a2, debugcause
55 movi a3, 0x10
56 assert eq, a2, a3
57test_end
58
59
60test ibreak
61 set_vector debug_vector, 0
62 rsil a2, debug_level
63 movi a2, 1f
64 wsr a2, ibreaka0
65 movi a2, 1
66 wsr a2, ibreakenable
67 isync
681:
69 rsil a2, debug_level - 1
70 movi a2, 1f
71 wsr a2, ibreaka0
72 movi a2, 0
73 wsr a2, ibreakenable
74 isync
751:
76 set_vector debug_vector, 2f
77 movi a2, 1f
78 wsr a2, ibreaka0
79 movi a2, 1
80 wsr a2, ibreakenable
81 isync
821:
83 test_fail
842:
85 rsr a2, ps
86 movi a3, 0x1f
87 and a2, a2, a3
88 movi a3, 0x10 | debug_level
89 assert eq, a2, a3
90 rsr a2, EPC_DEBUG
91 movi a3, 1b
92 assert eq, a2, a3
93 rsr a2, debugcause
94 movi a3, 0x2
95 assert eq, a2, a3
96test_end
97
98test ibreak_remove
99 set_vector debug_vector, 3f
100 rsil a2, debug_level - 1
101 movi a2, 2f
102 wsr a2, ibreaka0
103 movi a3, 1
1041:
105 wsr a3, ibreakenable
106 isync
1072:
108 beqz a3, 4f
109 test_fail
1103:
111 assert eqi, a3, 1
112 rsr a2, ps
113 movi a3, 0x1f
114 and a2, a2, a3
115 movi a3, 0x10 | debug_level
116 assert eq, a2, a3
117 rsr a2, EPC_DEBUG
118 movi a3, 2b
119 assert eq, a2, a3
120 rsr a2, debugcause
121 movi a3, 0x2
122 assert eq, a2, a3
123
124 movi a2, 0x40000
125 wsr a2, ps
126 isync
127 movi a3, 0
128 j 1b
1294:
130test_end
131
132test ibreak_priority
133 set_vector debug_vector, 2f
134 rsil a2, debug_level - 1
135 movi a2, 1f
136 wsr a2, ibreaka0
137 movi a2, 1
138 wsr a2, ibreakenable
139 isync
1401:
141 break 0, 0
142 test_fail
1432:
144 rsr a2, debugcause
145 movi a3, 0x2
146 assert eq, a2, a3
147test_end
148#endif
149
150test icount
151 set_vector debug_vector, 2f
152 rsil a2, debug_level - 1
153 movi a2, -2
154 wsr a2, icount
155 movi a2, 1
156 wsr a2, icountlevel
157 isync
158 rsil a2, 0
159 nop
1601:
161 break 0, 0
162 test_fail
1632:
164 movi a2, 0
165 wsr a2, icountlevel
166 rsr a2, EPC_DEBUG
167 movi a3, 1b
168 assert eq, a2, a3
169 rsr a2, debugcause
170 movi a3, 0x1
171 assert eq, a2, a3
172test_end
173
174.macro check_dbreak dr
175 rsr a2, EPC_DEBUG
176 movi a3, 1b
177 assert eq, a2, a3
178 rsr a2, debugcause
179 movi a3, 0x4 | (\dr << 8)
180 assert eq, a2, a3
181 movi a2, 0
182 wsr a2, dbreakc\dr
183.endm
184
185.macro dbreak_test dr, ctl, break, access, op
186 set_vector debug_vector, 2f
187 rsil a2, debug_level - 1
188 movi a2, \ctl
189 wsr a2, dbreakc\dr
190 movi a2, \break
191 wsr a2, dbreaka\dr
192 movi a2, \access
193 isync
1941:
195 \op a3, a2, 0
196 test_fail
1972:
198 check_dbreak \dr
199 reset_ps
200.endm
201
202
203test dbreak_exact
204 dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
205 dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
206 dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007c, l32i
207
208 dbreak_test 1, 0x8000003f, 0xd000007f, 0xd000007f, s8i
209 dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007e, s16i
210 dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s32i
211test_end
212
213test dbreak_overlap
214 dbreak_test 0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui
215 dbreak_test 1, 0x4000003f, 0xd000007d, 0xd000007c, l32i
216
217 dbreak_test 0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui
218 dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007c, l32i
219
220 dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui
221 dbreak_test 1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui
222
223 dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007b, l8ui
224 dbreak_test 1, 0x40000038, 0xd0000078, 0xd000007a, l16ui
225 dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007c, l32i
226
227 dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000075, l8ui
228 dbreak_test 0, 0x40000030, 0xd0000070, 0xd0000076, l16ui
229 dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000078, l32i
230
231 dbreak_test 0, 0x40000020, 0xd0000060, 0xd000006f, l8ui
232 dbreak_test 1, 0x40000020, 0xd0000060, 0xd0000070, l16ui
233 dbreak_test 0, 0x40000020, 0xd0000060, 0xd0000074, l32i
234
235
236 dbreak_test 0, 0x8000003f, 0xd000007d, 0xd000007c, s16i
237 dbreak_test 1, 0x8000003f, 0xd000007d, 0xd000007c, s32i
238
239 dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007f, s8i
240 dbreak_test 1, 0x8000003e, 0xd000007e, 0xd000007c, s32i
241
242 dbreak_test 0, 0x8000003c, 0xd000007c, 0xd000007d, s8i
243 dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s16i
244
245 dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007b, s8i
246 dbreak_test 1, 0x80000038, 0xd0000078, 0xd000007a, s16i
247 dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007c, s32i
248
249 dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000075, s8i
250 dbreak_test 0, 0x80000030, 0xd0000070, 0xd0000076, s16i
251 dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000078, s32i
252
253 dbreak_test 0, 0x80000020, 0xd0000060, 0xd000006f, s8i
254 dbreak_test 1, 0x80000020, 0xd0000060, 0xd0000070, s16i
255 dbreak_test 0, 0x80000020, 0xd0000060, 0xd0000074, s32i
256test_end
257
258test dbreak_invalid
259 dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
260 dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i
261test_end
262#endif
263
264#endif
265
266test_suite_end
267
