LXR qemu/tests/tcg/xtensa/test

   1#include "macros.inc"
   2
   3#define CCOUNT_SHIFT 4
   4#define WAIT_LOOPS 20
   5#define level1 kernel
   6#define INTERRUPT_LEVEL(n) glue3(XCHAL_INT, n, _LEVEL)
   7
   8.macro      make_ccount_delta target, delta
   9    rsr     \delta, ccount
  10    rsr     \target, ccount
  11    sub     \delta, \target, \delta
  12    slli    \delta, \delta, CCOUNT_SHIFT
  13    add     \target, \target, \delta
  14.endm
  15
  16test_suite timer
  17
  18#if XCHAL_HAVE_CCOUNT
  19
  20test ccount
  21    rsr     a3, ccount
  22    rsr     a4, ccount
  23    assert  ne, a3, a4
  24test_end
  25
  26test ccount_write
  27    rsr     a3, ccount
  28    rsr     a4, ccount
  29    sub     a4, a4, a3
  30    movi    a2, 0x12345678
  31    wsr     a2, ccount
  32    esync
  33    rsr     a3, ccount
  34    sub     a3, a3, a2
  35    slli    a4, a4, 2
  36    assert  ltu, a3, a4
  37test_end
  38
  39#if XCHAL_NUM_TIMERS
  40
  41test ccount_update_deadline
  42    movi    a2, 0
  43    wsr     a2, intenable
  44    rsr     a2, interrupt
  45    wsr     a2, intclear
  46    movi    a2, 0
  47#if XCHAL_NUM_TIMERS > 1
  48    wsr     a2, ccompare1
  49#endif
  50#if XCHAL_NUM_TIMERS > 2
  51    wsr     a2, ccompare2
  52#endif
  53    movi    a2, 0x12345678
  54    wsr     a2, ccompare0
  55    rsr     a3, interrupt
  56    assert  eqi, a3, 0
  57    movi    a2, 0x12345677
  58    wsr     a2, ccount
  59    esync
  60    nop
  61    rsr     a2, interrupt
  62    movi    a3, 1 << XCHAL_TIMER0_INTERRUPT
  63    assert  eq, a2, a3
  64test_end
  65
  66test ccompare
  67    movi    a2, 0
  68    wsr     a2, intenable
  69    rsr     a2, interrupt
  70    wsr     a2, intclear
  71    movi    a2, 0
  72#if XCHAL_NUM_TIMERS > 1
  73    wsr     a2, ccompare1
  74#endif
  75#if XCHAL_NUM_TIMERS > 2
  76    wsr     a2, ccompare2
  77#endif
  78
  79    make_ccount_delta a2, a15
  80    wsr     a2, ccompare0
  811:
  82    rsr     a3, interrupt
  83    rsr     a4, ccount
  84    rsr     a5, interrupt
  85    sub     a4, a4, a2
  86    bgez    a4, 2f
  87    assert  eqi, a3, 0
  88    j       1b
  892:
  90    assert  nei, a5, 0
  91test_end
  92
  93#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
  94test ccompare0_interrupt
  95    set_vector kernel, 2f
  96    movi    a2, 0
  97    wsr     a2, intenable
  98    rsr     a2, interrupt
  99    wsr     a2, intclear
 100    movi    a2, 0
 101#if XCHAL_NUM_TIMERS > 1
 102    wsr     a2, ccompare1
 103#endif
 104#if XCHAL_NUM_TIMERS > 2
 105    wsr     a2, ccompare2
 106#endif
 107
 108    movi    a3, WAIT_LOOPS
 109    make_ccount_delta a2, a15
 110    wsr     a2, ccompare0
 111    rsync
 112    rsr     a2, interrupt
 113    assert  eqi, a2, 0
 114
 115    movi    a2, 1 << XCHAL_TIMER0_INTERRUPT
 116    wsr     a2, intenable
 117    rsil    a2, 0
 118    loop    a3, 1f
 119    nop
 1201:
 121    test_fail
 1222:
 123    rsr     a2, exccause
 124    assert  eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
 125test_end
 126#endif
 127
 128#if XCHAL_NUM_TIMERS > 1
 129
 130test ccompare1_interrupt
 131    set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)), 2f
 132    movi    a2, 0
 133    wsr     a2, intenable
 134    rsr     a2, interrupt
 135    wsr     a2, intclear
 136    movi    a2, 0
 137    wsr     a2, ccompare0
 138#if XCHAL_NUM_TIMERS > 2
 139    wsr     a2, ccompare2
 140#endif
 141
 142    movi    a3, WAIT_LOOPS
 143    make_ccount_delta a2, a15
 144    wsr     a2, ccompare1
 145    rsync
 146    rsr     a2, interrupt
 147    assert  eqi, a2, 0
 148    movi    a2, 1 << XCHAL_TIMER1_INTERRUPT
 149    wsr     a2, intenable
 150    rsil    a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1
 151    loop    a3, 1f
 152    nop
 1531:
 154    test_fail
 1552:
 156test_end
 157
 158#endif
 159#if XCHAL_NUM_TIMERS > 2
 160
 161test ccompare2_interrupt
 162    set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)), 2f
 163    movi    a2, 0
 164    wsr     a2, intenable
 165    rsr     a2, interrupt
 166    wsr     a2, intclear
 167    movi    a2, 0
 168    wsr     a2, ccompare0
 169    wsr     a2, ccompare1
 170
 171    movi    a3, WAIT_LOOPS
 172    make_ccount_delta a2, a15
 173    wsr     a2, ccompare2
 174    rsync
 175    rsr     a2, interrupt
 176    assert  eqi, a2, 0
 177    movi    a2, 1 << XCHAL_TIMER2_INTERRUPT
 178    wsr     a2, intenable
 179    rsil    a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1
 180    loop    a3, 1f
 181    nop
 1821:
 183    test_fail
 1842:
 185test_end
 186
 187#endif
 188
 189test ccompare_interrupt_masked
 190    set_vector kernel, 2f
 191    movi    a2, 0
 192    wsr     a2, intenable
 193    rsr     a2, interrupt
 194    wsr     a2, intclear
 195    movi    a2, 0
 196#if XCHAL_NUM_TIMERS > 2
 197    wsr     a2, ccompare2
 198#endif
 199
 200    movi    a3, 2 * WAIT_LOOPS
 201    make_ccount_delta a2, a15
 202#if XCHAL_NUM_TIMERS > 1
 203    wsr     a2, ccompare1
 204#endif
 205    add     a2, a2, a15
 206    wsr     a2, ccompare0
 207    rsync
 208    rsr     a2, interrupt
 209    assert  eqi, a2, 0
 210
 211    movi    a2, 1 << XCHAL_TIMER0_INTERRUPT
 212    wsr     a2, intenable
 213    rsil    a2, 0
 214    loop    a3, 1f
 215    nop
 2161:
 217    test_fail
 2182:
 219    rsr     a2, exccause
 220    assert  eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
 221test_end
 222
 223test ccompare_interrupt_masked_waiti
 224    set_vector kernel, 2f
 225    movi    a2, 0
 226    wsr     a2, intenable
 227    rsr     a2, interrupt
 228    wsr     a2, intclear
 229    movi    a2, 0
 230#if XCHAL_NUM_TIMERS > 2
 231    wsr     a2, ccompare2
 232#endif
 233
 234    movi    a3, 2 * WAIT_LOOPS
 235    make_ccount_delta a2, a15
 236#if XCHAL_NUM_TIMERS > 1
 237    wsr     a2, ccompare1
 238#endif
 239    add     a2, a2, a15
 240    wsr     a2, ccompare0
 241    rsync
 242    rsr     a2, interrupt
 243    assert  eqi, a2, 0
 244
 245    movi    a2, 1 << XCHAL_TIMER0_INTERRUPT
 246    wsr     a2, intenable
 247    waiti   0
 248    test_fail
 2492:
 250    rsr     a2, exccause
 251    assert  eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
 252test_end
 253
 254#endif
 255#endif
 256
 257test_suite_end
 258