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29#include "qemu/osdep.h"
30#include "qapi/error.h"
31#include "qemu/bitmap.h"
32#include "trace.h"
33#include "hw/core/cpu.h"
34#include "target/arm/cpu.h"
35#include "hw/acpi/acpi-defs.h"
36#include "hw/acpi/acpi.h"
37#include "hw/nvram/fw_cfg.h"
38#include "hw/acpi/bios-linker-loader.h"
39#include "hw/acpi/aml-build.h"
40#include "hw/acpi/utils.h"
41#include "hw/acpi/pci.h"
42#include "hw/acpi/memory_hotplug.h"
43#include "hw/acpi/generic_event_device.h"
44#include "hw/acpi/tpm.h"
45#include "hw/pci/pcie_host.h"
46#include "hw/pci/pci.h"
47#include "hw/pci/pci_bus.h"
48#include "hw/pci-host/gpex.h"
49#include "hw/arm/virt.h"
50#include "hw/mem/nvdimm.h"
51#include "hw/platform-bus.h"
52#include "sysemu/numa.h"
53#include "sysemu/reset.h"
54#include "sysemu/tpm.h"
55#include "kvm_arm.h"
56#include "migration/vmstate.h"
57#include "hw/acpi/ghes.h"
58
59#define ARM_SPI_BASE 32
60
61#define ACPI_BUILD_TABLE_SIZE 0x20000
62
63static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
64{
65 MachineState *ms = MACHINE(vms);
66 uint16_t i;
67
68 for (i = 0; i < ms->smp.cpus; i++) {
69 Aml *dev = aml_device("C%.03X", i);
70 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
71 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
72 aml_append(scope, dev);
73 }
74}
75
76static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
77 uint32_t uart_irq)
78{
79 Aml *dev = aml_device("COM0");
80 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
81 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
82
83 Aml *crs = aml_resource_template();
84 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
85 uart_memmap->size, AML_READ_WRITE));
86 aml_append(crs,
87 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
88 AML_EXCLUSIVE, &uart_irq, 1));
89 aml_append(dev, aml_name_decl("_CRS", crs));
90
91 aml_append(scope, dev);
92}
93
94static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
95{
96 Aml *dev = aml_device("FWCF");
97 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
98
99 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
100 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
101
102 Aml *crs = aml_resource_template();
103 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
104 fw_cfg_memmap->size, AML_READ_WRITE));
105 aml_append(dev, aml_name_decl("_CRS", crs));
106 aml_append(scope, dev);
107}
108
109static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
110{
111 Aml *dev, *crs;
112 hwaddr base = flash_memmap->base;
113 hwaddr size = flash_memmap->size / 2;
114
115 dev = aml_device("FLS0");
116 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
117 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
118
119 crs = aml_resource_template();
120 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
121 aml_append(dev, aml_name_decl("_CRS", crs));
122 aml_append(scope, dev);
123
124 dev = aml_device("FLS1");
125 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
126 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
127 crs = aml_resource_template();
128 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
129 aml_append(dev, aml_name_decl("_CRS", crs));
130 aml_append(scope, dev);
131}
132
133static void acpi_dsdt_add_virtio(Aml *scope,
134 const MemMapEntry *virtio_mmio_memmap,
135 uint32_t mmio_irq, int num)
136{
137 hwaddr base = virtio_mmio_memmap->base;
138 hwaddr size = virtio_mmio_memmap->size;
139 int i;
140
141 for (i = 0; i < num; i++) {
142 uint32_t irq = mmio_irq + i;
143 Aml *dev = aml_device("VR%02u", i);
144 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
145 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
146 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
147
148 Aml *crs = aml_resource_template();
149 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
150 aml_append(crs,
151 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
152 AML_EXCLUSIVE, &irq, 1));
153 aml_append(dev, aml_name_decl("_CRS", crs));
154 aml_append(scope, dev);
155 base += size;
156 }
157}
158
159static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
160 uint32_t irq, bool use_highmem, bool highmem_ecam,
161 VirtMachineState *vms)
162{
163 int ecam_id = VIRT_ECAM_ID(highmem_ecam);
164 struct GPEXConfig cfg = {
165 .mmio32 = memmap[VIRT_PCIE_MMIO],
166 .pio = memmap[VIRT_PCIE_PIO],
167 .ecam = memmap[ecam_id],
168 .irq = irq,
169 .bus = vms->bus,
170 };
171
172 if (use_highmem) {
173 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];
174 }
175
176 acpi_dsdt_add_gpex(scope, &cfg);
177}
178
179static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
180 uint32_t gpio_irq)
181{
182 Aml *dev = aml_device("GPO0");
183 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
184 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
185
186 Aml *crs = aml_resource_template();
187 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
188 AML_READ_WRITE));
189 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
190 AML_EXCLUSIVE, &gpio_irq, 1));
191 aml_append(dev, aml_name_decl("_CRS", crs));
192
193 Aml *aei = aml_resource_template();
194
195 const uint32_t pin_list[1] = {3};
196 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
197 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
198 "GPO0", NULL, 0));
199 aml_append(dev, aml_name_decl("_AEI", aei));
200
201
202 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
203 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
204 aml_int(0x80)));
205 aml_append(dev, method);
206 aml_append(scope, dev);
207}
208
209#ifdef CONFIG_TPM
210static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
211{
212 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
213 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
214 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
215 MemoryRegion *sbdev_mr;
216 hwaddr tpm_base;
217
218 if (!sbdev) {
219 return;
220 }
221
222 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
223 assert(tpm_base != -1);
224
225 tpm_base += pbus_base;
226
227 sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
228
229 Aml *dev = aml_device("TPM0");
230 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
231 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
232
233 Aml *crs = aml_resource_template();
234 aml_append(crs,
235 aml_memory32_fixed(tpm_base,
236 (uint32_t)memory_region_size(sbdev_mr),
237 AML_READ_WRITE));
238 aml_append(dev, aml_name_decl("_CRS", crs));
239 aml_append(scope, dev);
240}
241#endif
242
243#define ID_MAPPING_ENTRY_SIZE 20
244#define SMMU_V3_ENTRY_SIZE 68
245#define ROOT_COMPLEX_ENTRY_SIZE 36
246#define IORT_NODE_OFFSET 48
247
248static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
249 uint32_t id_count, uint32_t out_ref)
250{
251
252 build_append_int_noprefix(table_data, input_base, 4);
253 build_append_int_noprefix(table_data, id_count, 4);
254 build_append_int_noprefix(table_data, input_base, 4);
255 build_append_int_noprefix(table_data, out_ref, 4);
256
257 build_append_int_noprefix(table_data, 0 , 4);
258}
259
260struct AcpiIortIdMapping {
261 uint32_t input_base;
262 uint32_t id_count;
263};
264typedef struct AcpiIortIdMapping AcpiIortIdMapping;
265
266
267static int
268iort_host_bridges(Object *obj, void *opaque)
269{
270 GArray *idmap_blob = opaque;
271
272 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
273 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
274
275 if (bus && !pci_bus_bypass_iommu(bus)) {
276 int min_bus, max_bus;
277
278 pci_bus_range(bus, &min_bus, &max_bus);
279
280 AcpiIortIdMapping idmap = {
281 .input_base = min_bus << 8,
282 .id_count = (max_bus - min_bus + 1) << 8,
283 };
284 g_array_append_val(idmap_blob, idmap);
285 }
286 }
287
288 return 0;
289}
290
291static int iort_idmap_compare(gconstpointer a, gconstpointer b)
292{
293 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a;
294 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b;
295
296 return idmap_a->input_base - idmap_b->input_base;
297}
298
299
300
301
302
303
304static void
305build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
306{
307 int i, nb_nodes, rc_mapping_count;
308 const uint32_t iort_node_offset = IORT_NODE_OFFSET;
309 size_t node_size, smmu_offset = 0;
310 AcpiIortIdMapping *idmap;
311 uint32_t id = 0;
312 GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
313 GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
314
315 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id,
316 .oem_table_id = vms->oem_table_id };
317
318 acpi_table_begin(&table, table_data);
319
320 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
321 AcpiIortIdMapping next_range = {0};
322
323 object_child_foreach_recursive(object_get_root(),
324 iort_host_bridges, smmu_idmaps);
325
326
327 g_array_sort(smmu_idmaps, iort_idmap_compare);
328
329
330
331
332
333 for (i = 0; i < smmu_idmaps->len; i++) {
334 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
335
336 if (next_range.input_base < idmap->input_base) {
337 next_range.id_count = idmap->input_base - next_range.input_base;
338 g_array_append_val(its_idmaps, next_range);
339 }
340
341 next_range.input_base = idmap->input_base + idmap->id_count;
342 }
343
344
345 if (next_range.input_base < 0xFFFF) {
346 next_range.id_count = 0xFFFF - next_range.input_base;
347 g_array_append_val(its_idmaps, next_range);
348 }
349
350 nb_nodes = 3;
351 rc_mapping_count = smmu_idmaps->len + its_idmaps->len;
352 } else {
353 nb_nodes = 2;
354 rc_mapping_count = 1;
355 }
356
357 build_append_int_noprefix(table_data, nb_nodes, 4);
358
359
360 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
361 build_append_int_noprefix(table_data, 0, 4);
362
363
364 build_append_int_noprefix(table_data, 0 , 1);
365 node_size = 20 + 4 ;
366 build_append_int_noprefix(table_data, node_size, 2);
367 build_append_int_noprefix(table_data, 1, 1);
368 build_append_int_noprefix(table_data, id++, 4);
369 build_append_int_noprefix(table_data, 0, 4);
370 build_append_int_noprefix(table_data, 0, 4);
371 build_append_int_noprefix(table_data, 1, 4);
372
373 build_append_int_noprefix(table_data, 0 , 4);
374
375 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
376 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
377
378 smmu_offset = table_data->len - table.table_offset;
379
380 build_append_int_noprefix(table_data, 4 , 1);
381 node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE;
382 build_append_int_noprefix(table_data, node_size, 2);
383 build_append_int_noprefix(table_data, 4, 1);
384 build_append_int_noprefix(table_data, id++, 4);
385 build_append_int_noprefix(table_data, 1, 4);
386
387 build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4);
388
389 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
390
391 build_append_int_noprefix(table_data, 1 , 4);
392 build_append_int_noprefix(table_data, 0, 4);
393 build_append_int_noprefix(table_data, 0, 8);
394
395 build_append_int_noprefix(table_data, 0 , 4);
396 build_append_int_noprefix(table_data, irq, 4);
397 build_append_int_noprefix(table_data, irq + 1, 4);
398 build_append_int_noprefix(table_data, irq + 3, 4);
399 build_append_int_noprefix(table_data, irq + 2, 4);
400 build_append_int_noprefix(table_data, 0, 4);
401
402 build_append_int_noprefix(table_data, 0, 4);
403
404
405 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
406 }
407
408
409 build_append_int_noprefix(table_data, 2 , 1);
410 node_size = ROOT_COMPLEX_ENTRY_SIZE +
411 ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
412 build_append_int_noprefix(table_data, node_size, 2);
413 build_append_int_noprefix(table_data, 3, 1);
414 build_append_int_noprefix(table_data, id++, 4);
415
416 build_append_int_noprefix(table_data, rc_mapping_count, 4);
417
418 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
419
420
421
422 build_append_int_noprefix(table_data, 1 , 4);
423 build_append_int_noprefix(table_data, 0, 1);
424 build_append_int_noprefix(table_data, 0, 2);
425
426 build_append_int_noprefix(table_data, 0x3 , 1);
427
428 build_append_int_noprefix(table_data, 0, 4);
429
430 build_append_int_noprefix(table_data, 0, 4);
431
432
433 build_append_int_noprefix(table_data, 64, 1);
434
435 build_append_int_noprefix(table_data, 0, 3);
436
437
438 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
439 AcpiIortIdMapping *range;
440
441
442 for (i = 0; i < smmu_idmaps->len; i++) {
443 range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
444
445 build_iort_id_mapping(table_data, range->input_base,
446 range->id_count, smmu_offset);
447 }
448
449
450 for (i = 0; i < its_idmaps->len; i++) {
451 range = &g_array_index(its_idmaps, AcpiIortIdMapping, i);
452
453 build_iort_id_mapping(table_data, range->input_base,
454 range->id_count, iort_node_offset);
455 }
456 } else {
457
458 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
459 }
460
461 acpi_table_end(linker, &table);
462 g_array_free(smmu_idmaps, true);
463 g_array_free(its_idmaps, true);
464}
465
466
467
468
469
470static void
471build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
472{
473 AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id,
474 .oem_table_id = vms->oem_table_id };
475
476 acpi_table_begin(&table, table_data);
477
478
479 build_append_int_noprefix(table_data, 3, 1);
480 build_append_int_noprefix(table_data, 0, 3);
481
482 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
483 vms->memmap[VIRT_UART].base);
484
485 build_append_int_noprefix(table_data,
486 (1 << 3) , 1);
487 build_append_int_noprefix(table_data, 0, 1);
488
489 build_append_int_noprefix(table_data,
490 vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4);
491 build_append_int_noprefix(table_data, 3 , 1);
492 build_append_int_noprefix(table_data, 0 , 1);
493
494 build_append_int_noprefix(table_data, 1 , 1);
495
496 build_append_int_noprefix(table_data,
497 (1 << 1) , 1);
498
499 build_append_int_noprefix(table_data, 0 , 1);
500 build_append_int_noprefix(table_data, 0, 1);
501
502 build_append_int_noprefix(table_data, 0xffff , 2);
503
504 build_append_int_noprefix(table_data, 0xffff , 2);
505 build_append_int_noprefix(table_data, 0, 1);
506 build_append_int_noprefix(table_data, 0, 1);
507 build_append_int_noprefix(table_data, 0, 1);
508 build_append_int_noprefix(table_data, 0, 4);
509 build_append_int_noprefix(table_data, 0, 1);
510 build_append_int_noprefix(table_data, 0, 4);
511
512 acpi_table_end(linker, &table);
513}
514
515
516
517
518
519static void
520build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
521{
522 int i;
523 uint64_t mem_base;
524 MachineClass *mc = MACHINE_GET_CLASS(vms);
525 MachineState *ms = MACHINE(vms);
526 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
527 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
528 .oem_table_id = vms->oem_table_id };
529
530 acpi_table_begin(&table, table_data);
531 build_append_int_noprefix(table_data, 1, 4);
532 build_append_int_noprefix(table_data, 0, 8);
533
534 for (i = 0; i < cpu_list->len; ++i) {
535 uint32_t nodeid = cpu_list->cpus[i].props.node_id;
536
537
538
539 build_append_int_noprefix(table_data, 3, 1);
540 build_append_int_noprefix(table_data, 18, 1);
541 build_append_int_noprefix(table_data, nodeid, 4);
542 build_append_int_noprefix(table_data, i, 4);
543
544 build_append_int_noprefix(table_data, 1 , 4);
545 build_append_int_noprefix(table_data, 0, 4);
546 }
547
548 mem_base = vms->memmap[VIRT_MEM].base;
549 for (i = 0; i < ms->numa_state->num_nodes; ++i) {
550 if (ms->numa_state->nodes[i].node_mem > 0) {
551 build_srat_memory(table_data, mem_base,
552 ms->numa_state->nodes[i].node_mem, i,
553 MEM_AFFINITY_ENABLED);
554 mem_base += ms->numa_state->nodes[i].node_mem;
555 }
556 }
557
558 if (ms->nvdimms_state->is_enabled) {
559 nvdimm_build_srat(table_data);
560 }
561
562 if (ms->device_memory) {
563 build_srat_memory(table_data, ms->device_memory->base,
564 memory_region_size(&ms->device_memory->mr),
565 ms->numa_state->num_nodes - 1,
566 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
567 }
568
569 acpi_table_end(linker, &table);
570}
571
572
573
574
575
576static void
577build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
578{
579 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
580
581
582
583
584
585 uint32_t irqflags = vmc->claim_edge_triggered_timers ?
586 1 :
587 0;
588 AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
589 .oem_table_id = vms->oem_table_id };
590
591 acpi_table_begin(&table, table_data);
592
593
594
595 build_append_int_noprefix(table_data, 0, 8);
596 build_append_int_noprefix(table_data, 0, 4);
597
598
599
600
601
602 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);
603
604 build_append_int_noprefix(table_data, irqflags, 4);
605
606 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);
607
608 build_append_int_noprefix(table_data, irqflags |
609 1UL << 2,
610 4);
611
612 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);
613
614 build_append_int_noprefix(table_data, irqflags, 4);
615
616 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);
617
618 build_append_int_noprefix(table_data, irqflags, 4);
619
620 build_append_int_noprefix(table_data, 0, 8);
621
622 build_append_int_noprefix(table_data, 0, 4);
623
624 build_append_int_noprefix(table_data, 0, 4);
625
626 acpi_table_end(linker, &table);
627}
628
629
630static void
631build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
632{
633 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id,
634 .oem_table_id = vms->oem_table_id };
635 int dbg2devicelength;
636 const char name[] = "COM0";
637 const int namespace_length = sizeof(name);
638
639 acpi_table_begin(&table, table_data);
640
641 dbg2devicelength = 22 +
642 12 +
643 4 +
644 namespace_length ;
645
646
647 build_append_int_noprefix(table_data, 44, 4);
648
649 build_append_int_noprefix(table_data, 1, 4);
650
651
652 build_append_int_noprefix(table_data, 0, 1);
653 build_append_int_noprefix(table_data, dbg2devicelength, 2);
654
655 build_append_int_noprefix(table_data, 1, 1);
656
657 build_append_int_noprefix(table_data, namespace_length, 2);
658 build_append_int_noprefix(table_data, 38, 2);
659 build_append_int_noprefix(table_data, 0, 2);
660
661 build_append_int_noprefix(table_data, 0, 2);
662
663
664 build_append_int_noprefix(table_data, 0x8000 , 2);
665
666 build_append_int_noprefix(table_data, 0x3 , 2);
667 build_append_int_noprefix(table_data, 0, 2);
668
669 build_append_int_noprefix(table_data, 22, 2);
670
671 build_append_int_noprefix(table_data, 34, 2);
672
673
674 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
675 vms->memmap[VIRT_UART].base);
676
677
678 build_append_int_noprefix(table_data,
679 vms->memmap[VIRT_UART].size, 4);
680
681
682 g_array_append_vals(table_data, name, namespace_length);
683
684 acpi_table_end(linker, &table);
685};
686
687
688
689
690
691static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
692{
693 build_append_int_noprefix(table_data, 0xE, 1);
694 build_append_int_noprefix(table_data, 16, 1);
695 build_append_int_noprefix(table_data, 0, 2);
696
697 build_append_int_noprefix(table_data, base, 8);
698 build_append_int_noprefix(table_data, size, 4);
699}
700
701static void
702build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
703{
704 int i;
705 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
706 const MemMapEntry *memmap = vms->memmap;
707 AcpiTable table = { .sig = "APIC", .rev = 3, .oem_id = vms->oem_id,
708 .oem_table_id = vms->oem_table_id };
709
710 acpi_table_begin(&table, table_data);
711
712 build_append_int_noprefix(table_data, 0, 4);
713 build_append_int_noprefix(table_data, 0, 4);
714
715
716 build_append_int_noprefix(table_data, 0xC, 1);
717 build_append_int_noprefix(table_data, 24, 1);
718 build_append_int_noprefix(table_data, 0, 2);
719 build_append_int_noprefix(table_data, 0, 4);
720
721 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8);
722 build_append_int_noprefix(table_data, 0, 4);
723
724 build_append_int_noprefix(table_data, vms->gic_version, 1);
725 build_append_int_noprefix(table_data, 0, 3);
726
727 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
728 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
729 uint64_t physical_base_address = 0, gich = 0, gicv = 0;
730 uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
731 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
732 PPI(VIRTUAL_PMU_IRQ) : 0;
733
734 if (vms->gic_version == 2) {
735 physical_base_address = memmap[VIRT_GIC_CPU].base;
736 gicv = memmap[VIRT_GIC_VCPU].base;
737 gich = memmap[VIRT_GIC_HYP].base;
738 }
739
740
741 build_append_int_noprefix(table_data, 0xB, 1);
742 build_append_int_noprefix(table_data, 76, 1);
743 build_append_int_noprefix(table_data, 0, 2);
744 build_append_int_noprefix(table_data, i, 4);
745 build_append_int_noprefix(table_data, i, 4);
746
747 build_append_int_noprefix(table_data, 1, 4);
748
749 build_append_int_noprefix(table_data, 0, 4);
750
751 build_append_int_noprefix(table_data, pmu_interrupt, 4);
752 build_append_int_noprefix(table_data, 0, 8);
753
754 build_append_int_noprefix(table_data, physical_base_address, 8);
755 build_append_int_noprefix(table_data, gicv, 8);
756 build_append_int_noprefix(table_data, gich, 8);
757
758 build_append_int_noprefix(table_data, vgic_interrupt, 4);
759 build_append_int_noprefix(table_data, 0, 8);
760
761 build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
762 }
763
764 if (vms->gic_version == 3) {
765 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
766 memmap[VIRT_GIC_REDIST].size);
767 if (virt_gicv3_redist_region_count(vms) == 2) {
768 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base,
769 memmap[VIRT_HIGH_GIC_REDIST2].size);
770 }
771
772 if (its_class_name() && !vmc->no_its) {
773
774
775
776
777
778
779
780
781
782
783
784 build_append_int_noprefix(table_data, 0xF, 1);
785 build_append_int_noprefix(table_data, 20, 1);
786 build_append_int_noprefix(table_data, 0, 2);
787 build_append_int_noprefix(table_data, 0, 4);
788
789 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);
790 build_append_int_noprefix(table_data, 0, 4);
791 }
792 } else {
793 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;
794
795
796 build_append_int_noprefix(table_data, 0xD, 1);
797 build_append_int_noprefix(table_data, 24, 1);
798 build_append_int_noprefix(table_data, 0, 2);
799 build_append_int_noprefix(table_data, 0, 4);
800
801 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8);
802 build_append_int_noprefix(table_data, 1, 4);
803
804 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2);
805 build_append_int_noprefix(table_data, spi_base, 2);
806 }
807 acpi_table_end(linker, &table);
808}
809
810
811static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
812 VirtMachineState *vms, unsigned dsdt_tbl_offset)
813{
814
815 AcpiFadtData fadt = {
816 .rev = 5,
817 .minor_ver = 1,
818 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
819 .xdsdt_tbl_offset = &dsdt_tbl_offset,
820 };
821
822 switch (vms->psci_conduit) {
823 case QEMU_PSCI_CONDUIT_DISABLED:
824 fadt.arm_boot_arch = 0;
825 break;
826 case QEMU_PSCI_CONDUIT_HVC:
827 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
828 ACPI_FADT_ARM_PSCI_USE_HVC;
829 break;
830 case QEMU_PSCI_CONDUIT_SMC:
831 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
832 break;
833 default:
834 g_assert_not_reached();
835 }
836
837 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);
838}
839
840
841static void
842build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
843{
844 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
845 Aml *scope, *dsdt;
846 MachineState *ms = MACHINE(vms);
847 const MemMapEntry *memmap = vms->memmap;
848 const int *irqmap = vms->irqmap;
849 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
850 .oem_table_id = vms->oem_table_id };
851
852 acpi_table_begin(&table, table_data);
853 dsdt = init_aml_allocator();
854
855
856
857
858
859
860 scope = aml_scope("\\_SB");
861 acpi_dsdt_add_cpus(scope, vms);
862 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
863 (irqmap[VIRT_UART] + ARM_SPI_BASE));
864 if (vmc->acpi_expose_flash) {
865 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
866 }
867 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
868 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
869 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
870 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
871 vms->highmem, vms->highmem_ecam, vms);
872 if (vms->acpi_dev) {
873 build_ged_aml(scope, "\\_SB."GED_DEVICE,
874 HOTPLUG_HANDLER(vms->acpi_dev),
875 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY,
876 memmap[VIRT_ACPI_GED].base);
877 } else {
878 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
879 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
880 }
881
882 if (vms->acpi_dev) {
883 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev),
884 "ged-event", &error_abort);
885
886 if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
887 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL,
888 AML_SYSTEM_MEMORY,
889 memmap[VIRT_PCDIMM_ACPI].base);
890 }
891 }
892
893 acpi_dsdt_add_power_button(scope);
894#ifdef CONFIG_TPM
895 acpi_dsdt_add_tpm(scope, vms);
896#endif
897
898 aml_append(dsdt, scope);
899
900
901 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
902
903 acpi_table_end(linker, &table);
904 free_aml_allocator();
905}
906
907typedef
908struct AcpiBuildState {
909
910 MemoryRegion *table_mr;
911 MemoryRegion *rsdp_mr;
912 MemoryRegion *linker_mr;
913
914 bool patched;
915} AcpiBuildState;
916
917static void acpi_align_size(GArray *blob, unsigned align)
918{
919
920
921
922
923 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
924}
925
926static
927void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
928{
929 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
930 GArray *table_offsets;
931 unsigned dsdt, xsdt;
932 GArray *tables_blob = tables->table_data;
933 MachineState *ms = MACHINE(vms);
934
935 table_offsets = g_array_new(false, true ,
936 sizeof(uint32_t));
937
938 bios_linker_loader_alloc(tables->linker,
939 ACPI_BUILD_TABLE_FILE, tables_blob,
940 64, false );
941
942
943 dsdt = tables_blob->len;
944 build_dsdt(tables_blob, tables->linker, vms);
945
946
947 acpi_add_table(table_offsets, tables_blob);
948 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt);
949
950 acpi_add_table(table_offsets, tables_blob);
951 build_madt(tables_blob, tables->linker, vms);
952
953 if (!vmc->no_cpu_topology) {
954 acpi_add_table(table_offsets, tables_blob);
955 build_pptt(tables_blob, tables->linker, ms,
956 vms->oem_id, vms->oem_table_id);
957 }
958
959 acpi_add_table(table_offsets, tables_blob);
960 build_gtdt(tables_blob, tables->linker, vms);
961
962 acpi_add_table(table_offsets, tables_blob);
963 {
964 AcpiMcfgInfo mcfg = {
965 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
966 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
967 };
968 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id,
969 vms->oem_table_id);
970 }
971
972 acpi_add_table(table_offsets, tables_blob);
973 build_spcr(tables_blob, tables->linker, vms);
974
975 acpi_add_table(table_offsets, tables_blob);
976 build_dbg2(tables_blob, tables->linker, vms);
977
978 if (vms->ras) {
979 build_ghes_error_table(tables->hardware_errors, tables->linker);
980 acpi_add_table(table_offsets, tables_blob);
981 acpi_build_hest(tables_blob, tables->linker, vms->oem_id,
982 vms->oem_table_id);
983 }
984
985 if (ms->numa_state->num_nodes > 0) {
986 acpi_add_table(table_offsets, tables_blob);
987 build_srat(tables_blob, tables->linker, vms);
988 if (ms->numa_state->have_numa_distance) {
989 acpi_add_table(table_offsets, tables_blob);
990 build_slit(tables_blob, tables->linker, ms, vms->oem_id,
991 vms->oem_table_id);
992 }
993 }
994
995 if (ms->nvdimms_state->is_enabled) {
996 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
997 ms->nvdimms_state, ms->ram_slots, vms->oem_id,
998 vms->oem_table_id);
999 }
1000
1001 if (its_class_name() && !vmc->no_its) {
1002 acpi_add_table(table_offsets, tables_blob);
1003 build_iort(tables_blob, tables->linker, vms);
1004 }
1005
1006#ifdef CONFIG_TPM
1007 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
1008 acpi_add_table(table_offsets, tables_blob);
1009 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id,
1010 vms->oem_table_id);
1011 }
1012#endif
1013
1014
1015 xsdt = tables_blob->len;
1016 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
1017 vms->oem_table_id);
1018
1019
1020 {
1021 AcpiRsdpData rsdp_data = {
1022 .revision = 2,
1023 .oem_id = vms->oem_id,
1024 .xsdt_tbl_offset = &xsdt,
1025 .rsdt_tbl_offset = NULL,
1026 };
1027 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
1028 }
1029
1030
1031
1032
1033
1034 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1035 warn_report("ACPI table size %u exceeds %d bytes,"
1036 " migration may not work",
1037 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
1038 error_printf("Try removing CPUs, NUMA nodes, memory slots"
1039 " or PCI bridges.");
1040 }
1041 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1042
1043
1044
1045 g_array_free(table_offsets, true);
1046}
1047
1048static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1049{
1050 uint32_t size = acpi_data_len(data);
1051
1052
1053
1054 memory_region_ram_resize(mr, size, &error_abort);
1055
1056 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1057 memory_region_set_dirty(mr, 0, size);
1058}
1059
1060static void virt_acpi_build_update(void *build_opaque)
1061{
1062 AcpiBuildState *build_state = build_opaque;
1063 AcpiBuildTables tables;
1064
1065
1066 if (!build_state || build_state->patched) {
1067 return;
1068 }
1069 build_state->patched = true;
1070
1071 acpi_build_tables_init(&tables);
1072
1073 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
1074
1075 acpi_ram_update(build_state->table_mr, tables.table_data);
1076 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1077 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
1078
1079 acpi_build_tables_cleanup(&tables, true);
1080}
1081
1082static void virt_acpi_build_reset(void *build_opaque)
1083{
1084 AcpiBuildState *build_state = build_opaque;
1085 build_state->patched = false;
1086}
1087
1088static const VMStateDescription vmstate_virt_acpi_build = {
1089 .name = "virt_acpi_build",
1090 .version_id = 1,
1091 .minimum_version_id = 1,
1092 .fields = (VMStateField[]) {
1093 VMSTATE_BOOL(patched, AcpiBuildState),
1094 VMSTATE_END_OF_LIST()
1095 },
1096};
1097
1098void virt_acpi_setup(VirtMachineState *vms)
1099{
1100 AcpiBuildTables tables;
1101 AcpiBuildState *build_state;
1102 AcpiGedState *acpi_ged_state;
1103
1104 if (!vms->fw_cfg) {
1105 trace_virt_acpi_setup();
1106 return;
1107 }
1108
1109 if (!virt_is_acpi_enabled(vms)) {
1110 trace_virt_acpi_setup();
1111 return;
1112 }
1113
1114 build_state = g_malloc0(sizeof *build_state);
1115
1116 acpi_build_tables_init(&tables);
1117 virt_acpi_build(vms, &tables);
1118
1119
1120 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
1121 build_state, tables.table_data,
1122 ACPI_BUILD_TABLE_FILE);
1123 assert(build_state->table_mr != NULL);
1124
1125 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
1126 build_state,
1127 tables.linker->cmd_blob,
1128 ACPI_BUILD_LOADER_FILE);
1129
1130 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
1131 acpi_data_len(tables.tcpalog));
1132
1133 if (vms->ras) {
1134 assert(vms->acpi_dev);
1135 acpi_ged_state = ACPI_GED(vms->acpi_dev);
1136 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state,
1137 vms->fw_cfg, tables.hardware_errors);
1138 }
1139
1140 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
1141 build_state, tables.rsdp,
1142 ACPI_BUILD_RSDP_FILE);
1143
1144 qemu_register_reset(virt_acpi_build_reset, build_state);
1145 virt_acpi_build_reset(build_state);
1146 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
1147
1148
1149
1150
1151 acpi_build_tables_cleanup(&tables, false);
1152}
1153